diff options
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_wm_sampler_state.c | 19 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 16 |
2 files changed, 12 insertions, 23 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c b/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c index f2117a48e1a..1f46f918575 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c @@ -33,6 +33,7 @@ #include "brw_context.h" #include "brw_state.h" #include "brw_defines.h" +#include "intel_mipmap_tree.h" #include "main/macros.h" #include "main/samplerobj.h" @@ -201,6 +202,8 @@ static void brw_update_sampler_state(struct brw_context *brw, struct gl_context *ctx = &brw->ctx; struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit]; struct gl_texture_object *texObj = texUnit->_Current; + struct intel_texture_image *intel_image = + intel_texture_image(texObj->Image[0][texObj->BaseLevel]); struct gl_sampler_object *gl_sampler = _mesa_get_samplerobj(ctx, unit); bool using_nearest = false; @@ -319,17 +322,13 @@ static void brw_update_sampler_state(struct brw_context *brw, sampler->ss0.lod_preclamp = 1; /* OpenGL mode */ sampler->ss0.default_color_mode = 0; /* OpenGL/DX10 mode */ - /* Set BaseMipLevel, MaxLOD, MinLOD: - * - * XXX: I don't think that using firstLevel, lastLevel works, - * because we always setup the surface state as if firstLevel == - * level zero. Probably have to subtract firstLevel from each of - * these: - */ - sampler->ss0.base_level = U_FIXED(0, 1); + int baselevel = texObj->BaseLevel - intel_image->mt->first_level; + sampler->ss0.base_level = U_FIXED(baselevel, 1); - sampler->ss1.max_lod = U_FIXED(CLAMP(gl_sampler->MaxLod, 0, 13), 6); - sampler->ss1.min_lod = U_FIXED(CLAMP(gl_sampler->MinLod, 0, 13), 6); + sampler->ss1.max_lod = U_FIXED(CLAMP(baselevel + + gl_sampler->MaxLod, 0, 13), 6); + sampler->ss1.min_lod = U_FIXED(CLAMP(baselevel + + gl_sampler->MinLod, 0, 13), 6); /* On Gen6+, the sampler can handle non-normalized texture * rectangle coordinates natively diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index e2c7b77472d..8bc3938bb26 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -255,9 +255,9 @@ brw_update_texture_surface(struct gl_context *ctx, struct intel_texture_object *intelObj = intel_texture_object(tObj); struct intel_mipmap_tree *mt = intelObj->mt; struct gl_texture_image *firstImage = tObj->Image[0][tObj->BaseLevel]; + struct intel_texture_image *intel_image = intel_texture_image(firstImage); struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit); uint32_t *surf; - uint32_t tile_x, tile_y; if (tObj->Target == GL_TEXTURE_BUFFER) { brw_update_buffer_texture_surface(ctx, unit, binding_table, surf_index); @@ -277,10 +277,8 @@ brw_update_texture_surface(struct gl_context *ctx, BRW_SURFACE_FORMAT_SHIFT)); surf[1] = intelObj->mt->region->bo->offset + intelObj->mt->offset; /* reloc */ - surf[1] += intel_miptree_get_tile_offsets(intelObj->mt, firstImage->Level, 0, - &tile_x, &tile_y); - surf[2] = ((intelObj->_MaxLevel - tObj->BaseLevel) << BRW_SURFACE_LOD_SHIFT | + surf[2] = ((intelObj->_MaxLevel - intel_image->mt->first_level) << BRW_SURFACE_LOD_SHIFT | (mt->logical_width0 - 1) << BRW_SURFACE_WIDTH_SHIFT | (mt->logical_height0 - 1) << BRW_SURFACE_HEIGHT_SHIFT); @@ -291,15 +289,7 @@ brw_update_texture_surface(struct gl_context *ctx, surf[4] = brw_get_surface_num_multisamples(intelObj->mt->num_samples); - assert(brw->has_surface_tile_offset || (tile_x == 0 && tile_y == 0)); - /* Note that the low bits of these fields are missing, so - * there's the possibility of getting in trouble. - */ - assert(tile_x % 4 == 0); - assert(tile_y % 2 == 0); - surf[5] = ((tile_x / 4) << BRW_SURFACE_X_OFFSET_SHIFT | - (tile_y / 2) << BRW_SURFACE_Y_OFFSET_SHIFT | - (mt->align_h == 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0)); + surf[5] = mt->align_h == 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0; /* Emit relocation to surface contents */ drm_intel_bo_emit_reloc(brw->batch.bo, |