diff options
| -rw-r--r-- | src/mesa/drivers/dri/i965/Makefile.sources | 1 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_defines.h | 7 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_state.h | 2 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_state_upload.c | 2 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/gen7_disable.c | 33 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/gen7_gs_state.c | 144 |
6 files changed, 156 insertions, 33 deletions
diff --git a/src/mesa/drivers/dri/i965/Makefile.sources b/src/mesa/drivers/dri/i965/Makefile.sources index 5299d0d9ae0..07c1053e84b 100644 --- a/src/mesa/drivers/dri/i965/Makefile.sources +++ b/src/mesa/drivers/dri/i965/Makefile.sources @@ -122,6 +122,7 @@ i965_FILES = \ gen7_blorp.cpp \ gen7_clip_state.c \ gen7_disable.c \ + gen7_gs_state.c \ gen7_misc_state.c \ gen7_sampler_state.c \ gen7_sf_state.c \ diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index d5a12f10ca2..0406c4d75e8 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -1328,15 +1328,22 @@ enum brw_message_target { # define GEN6_GS_FLOATING_POINT_MODE_IEEE_754 (0 << 16) # define GEN6_GS_FLOATING_POINT_MODE_ALT (1 << 16) /* DW4 */ +# define GEN7_GS_OUTPUT_VERTEX_SIZE_SHIFT 23 +# define GEN7_GS_OUTPUT_TOPOLOGY_SHIFT 17 # define GEN6_GS_URB_READ_LENGTH_SHIFT 11 # define GEN7_GS_INCLUDE_VERTEX_HANDLES (1 << 10) # define GEN6_GS_URB_ENTRY_READ_OFFSET_SHIFT 4 # define GEN6_GS_DISPATCH_START_GRF_SHIFT 0 /* DW5 */ # define GEN6_GS_MAX_THREADS_SHIFT 25 +# define HSW_GS_MAX_THREADS_SHIFT 24 +# define GEN7_GS_DISPATCH_MODE_SINGLE (0 << 11) +# define GEN7_GS_DISPATCH_MODE_DUAL_INSTANCE (1 << 11) +# define GEN7_GS_DISPATCH_MODE_DUAL_OBJECT (2 << 11) # define GEN6_GS_STATISTICS_ENABLE (1 << 10) # define GEN6_GS_SO_STATISTICS_ENABLE (1 << 9) # define GEN6_GS_RENDERING_ENABLE (1 << 8) +# define GEN7_GS_INCLUDE_PRIMITIVE_ID (1 << 4) # define GEN7_GS_ENABLE (1 << 0) /* DW6 */ # define GEN6_GS_REORDER (1 << 30) diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h index 4c4a536c505..04c1a972d5d 100644 --- a/src/mesa/drivers/dri/i965/brw_state.h +++ b/src/mesa/drivers/dri/i965/brw_state.h @@ -116,6 +116,8 @@ extern const struct brw_tracked_state gen7_depthbuffer; extern const struct brw_tracked_state gen7_cc_viewport_state_pointer; extern const struct brw_tracked_state gen7_clip_state; extern const struct brw_tracked_state gen7_disable_stages; +extern const struct brw_tracked_state gen7_gs_push_constants; +extern const struct brw_tracked_state gen7_gs_state; extern const struct brw_tracked_state gen7_ps_state; extern const struct brw_tracked_state gen7_push_constant_space; extern const struct brw_tracked_state gen7_sbe_state; diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c index b6a6a0a727f..8f21f06ac0c 100644 --- a/src/mesa/drivers/dri/i965/brw_state_upload.c +++ b/src/mesa/drivers/dri/i965/brw_state_upload.c @@ -196,6 +196,7 @@ static const struct brw_tracked_state *gen7_atoms[] = &gen6_depth_stencil_state, /* must do before cc unit */ &gen6_vs_push_constants, /* Before vs_state */ + &gen7_gs_push_constants, /* Before gs_state */ &gen6_wm_push_constants, /* Before wm_surfaces and constant_buffer */ /* Surface state setup. Must come before the VS/WM unit. The binding @@ -220,6 +221,7 @@ static const struct brw_tracked_state *gen7_atoms[] = &gen7_disable_stages, &gen7_vs_state, + &gen7_gs_state, &gen7_sol_state, &gen7_clip_state, &gen7_sbe_state, diff --git a/src/mesa/drivers/dri/i965/gen7_disable.c b/src/mesa/drivers/dri/i965/gen7_disable.c index 860aa951df0..98d115b9e22 100644 --- a/src/mesa/drivers/dri/i965/gen7_disable.c +++ b/src/mesa/drivers/dri/i965/gen7_disable.c @@ -29,39 +29,6 @@ static void disable_stages(struct brw_context *brw) { - assert(!brw->ff_gs.prog_active); - - /* Disable the Geometry Shader (GS) Unit */ - BEGIN_BATCH(7); - OUT_BATCH(_3DSTATE_CONSTANT_GS << 16 | (7 - 2)); - OUT_BATCH(0); - OUT_BATCH(0); - OUT_BATCH(0); - OUT_BATCH(0); - OUT_BATCH(0); - OUT_BATCH(0); - ADVANCE_BATCH(); - - BEGIN_BATCH(7); - OUT_BATCH(_3DSTATE_GS << 16 | (7 - 2)); - OUT_BATCH(0); /* prog_bo */ - OUT_BATCH((0 << GEN6_GS_SAMPLER_COUNT_SHIFT) | - (0 << GEN6_GS_BINDING_TABLE_ENTRY_COUNT_SHIFT)); - OUT_BATCH(0); /* scratch space base offset */ - OUT_BATCH((1 << GEN6_GS_DISPATCH_START_GRF_SHIFT) | - (0 << GEN6_GS_URB_READ_LENGTH_SHIFT) | - GEN7_GS_INCLUDE_VERTEX_HANDLES | - (0 << GEN6_GS_URB_ENTRY_READ_OFFSET_SHIFT)); - OUT_BATCH((0 << GEN6_GS_MAX_THREADS_SHIFT) | - GEN6_GS_STATISTICS_ENABLE); - OUT_BATCH(0); - ADVANCE_BATCH(); - - BEGIN_BATCH(2); - OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_GS << 16 | (2 - 2)); - OUT_BATCH(0); - ADVANCE_BATCH(); - /* Disable the HS Unit */ BEGIN_BATCH(7); OUT_BATCH(_3DSTATE_CONSTANT_HS << 16 | (7 - 2)); diff --git a/src/mesa/drivers/dri/i965/gen7_gs_state.c b/src/mesa/drivers/dri/i965/gen7_gs_state.c new file mode 100644 index 00000000000..3e3c33123a4 --- /dev/null +++ b/src/mesa/drivers/dri/i965/gen7_gs_state.c @@ -0,0 +1,144 @@ +/* + * Copyright © 2013 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "brw_context.h" +#include "brw_state.h" +#include "brw_defines.h" +#include "intel_batchbuffer.h" + + +static void +gen7_upload_gs_push_constants(struct brw_context *brw) +{ + /* BRW_NEW_GEOMETRY_PROGRAM */ + const struct brw_geometry_program *vp = + (struct brw_geometry_program *) brw->geometry_program; + if (!vp) + return; + + /* CACHE_NEW_GS_PROG */ + const struct brw_vec4_prog_data *prog_data = &brw->gs.prog_data->base; + struct brw_stage_state *stage_state = &brw->gs.base; + + gen6_upload_vec4_push_constants(brw, &vp->program.Base, prog_data, + stage_state, AUB_TRACE_VS_CONSTANTS); +} + +const struct brw_tracked_state gen7_gs_push_constants = { + .dirty = { + .mesa = _NEW_TRANSFORM | _NEW_PROGRAM_CONSTANTS, + .brw = (BRW_NEW_BATCH | + BRW_NEW_GEOMETRY_PROGRAM), + .cache = CACHE_NEW_GS_PROG, + }, + .emit = gen7_upload_gs_push_constants, +}; + + +static void +upload_gs_state(struct brw_context *brw) +{ + const struct brw_stage_state *stage_state = &brw->gs.base; + const int max_threads_shift = brw->is_haswell ? + HSW_GS_MAX_THREADS_SHIFT : GEN6_GS_MAX_THREADS_SHIFT; + /* BRW_NEW_GEOMETRY_PROGRAM */ + bool active = brw->geometry_program; + /* CACHE_NEW_GS_PROG */ + const struct brw_vec4_prog_data *prog_data = &brw->gs.prog_data->base; + + /* BRW_NEW_GS_BINDING_TABLE */ + BEGIN_BATCH(2); + OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_GS << 16 | (2 - 2)); + OUT_BATCH(stage_state->bind_bo_offset); + ADVANCE_BATCH(); + + /* CACHE_NEW_SAMPLER */ + BEGIN_BATCH(2); + OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS_GS << 16 | (2 - 2)); + OUT_BATCH(stage_state->sampler_offset); + ADVANCE_BATCH(); + + gen7_upload_constant_state(brw, stage_state, active, _3DSTATE_CONSTANT_GS); + + if (active) { + BEGIN_BATCH(7); + OUT_BATCH(_3DSTATE_GS << 16 | (7 - 2)); + OUT_BATCH(stage_state->prog_offset); + OUT_BATCH(((ALIGN(stage_state->sampler_count, 4)/4) << + GEN6_GS_SAMPLER_COUNT_SHIFT)); + + if (brw->gs.prog_data->base.total_scratch) { + OUT_RELOC(stage_state->scratch_bo, + I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, + ffs(brw->gs.prog_data->base.total_scratch) - 11); + } else { + OUT_BATCH(0); + } + + OUT_BATCH(((brw->gs.prog_data->output_vertex_size_hwords * 2 - 1) << + GEN7_GS_OUTPUT_VERTEX_SIZE_SHIFT) | + (brw->gs.prog_data->output_topology << + GEN7_GS_OUTPUT_TOPOLOGY_SHIFT) | + (prog_data->urb_read_length << + GEN6_GS_URB_READ_LENGTH_SHIFT) | + (0 << GEN6_GS_URB_ENTRY_READ_OFFSET_SHIFT) | + (prog_data->dispatch_grf_start_reg << + GEN6_GS_DISPATCH_START_GRF_SHIFT)); + + OUT_BATCH(((brw->max_gs_threads - 1) << max_threads_shift) | + GEN7_GS_DISPATCH_MODE_DUAL_OBJECT | + GEN6_GS_STATISTICS_ENABLE | + GEN7_GS_ENABLE); + + OUT_BATCH(0); + ADVANCE_BATCH(); + } else { + BEGIN_BATCH(7); + OUT_BATCH(_3DSTATE_GS << 16 | (7 - 2)); + OUT_BATCH(0); /* prog_bo */ + OUT_BATCH((0 << GEN6_GS_SAMPLER_COUNT_SHIFT) | + (0 << GEN6_GS_BINDING_TABLE_ENTRY_COUNT_SHIFT)); + OUT_BATCH(0); /* scratch space base offset */ + OUT_BATCH((1 << GEN6_GS_DISPATCH_START_GRF_SHIFT) | + (0 << GEN6_GS_URB_READ_LENGTH_SHIFT) | + GEN7_GS_INCLUDE_VERTEX_HANDLES | + (0 << GEN6_GS_URB_ENTRY_READ_OFFSET_SHIFT)); + OUT_BATCH((0 << GEN6_GS_MAX_THREADS_SHIFT) | + GEN6_GS_STATISTICS_ENABLE); + OUT_BATCH(0); + ADVANCE_BATCH(); + } +} + +const struct brw_tracked_state gen7_gs_state = { + .dirty = { + .mesa = _NEW_TRANSFORM | _NEW_PROGRAM_CONSTANTS, + .brw = (BRW_NEW_CONTEXT | + BRW_NEW_GEOMETRY_PROGRAM | + BRW_NEW_GS_BINDING_TABLE | + BRW_NEW_BATCH | + BRW_NEW_PUSH_CONSTANT_ALLOCATION), + .cache = CACHE_NEW_GS_PROG | CACHE_NEW_SAMPLER + }, + .emit = upload_gs_state, +}; |