diff options
| -rw-r--r-- | src/amd/common/r600d_common.h | 165 | ||||
| -rw-r--r-- | src/amd/common/sid.h | 17 | ||||
| -rw-r--r-- | src/amd/vulkan/radv_cmd_buffer.c | 6 | ||||
| -rw-r--r-- | src/amd/vulkan/radv_pipeline.c | 6 | ||||
| -rw-r--r-- | src/amd/vulkan/si_cmd_buffer.c | 28 | ||||
| -rw-r--r-- | src/gallium/drivers/r600/cayman_msaa.c | 1 | ||||
| -rw-r--r-- | src/gallium/drivers/r600/evergreen_state.c | 4 | ||||
| -rw-r--r-- | src/gallium/drivers/r600/evergreend.h | 110 | ||||
| -rw-r--r-- | src/gallium/drivers/r600/r600_streamout.c | 14 | ||||
| -rw-r--r-- | src/gallium/drivers/r600/r600_viewport.c | 23 | ||||
| -rw-r--r-- | src/gallium/drivers/radeon/r600_cs.h | 14 | ||||
| -rw-r--r-- | src/gallium/drivers/radeon/r600_perfcounter.c | 2 | ||||
| -rw-r--r-- | src/gallium/drivers/radeon/r600_pipe_common.c | 1 | ||||
| -rw-r--r-- | src/gallium/drivers/radeon/r600_query.c | 21 | ||||
| -rw-r--r-- | src/gallium/drivers/radeon/r600_texture.c | 35 | ||||
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_perfcounter.c | 8 | ||||
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_state.c | 26 | ||||
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_state_msaa.c | 28 | ||||
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_state_streamout.c | 4 |
19 files changed, 252 insertions, 261 deletions
diff --git a/src/amd/common/r600d_common.h b/src/amd/common/r600d_common.h index 76c5c4f5f9b..ed1d46076c0 100644 --- a/src/amd/common/r600d_common.h +++ b/src/amd/common/r600d_common.h @@ -39,8 +39,6 @@ #define PKT3_PREDICATE(x) (((x) >> 0) & 0x1) #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate)) -#define RADEON_CP_PACKET3_COMPUTE_MODE 0x00000002 - #define PKT3_NOP 0x10 #define PKT3_SET_PREDICATION 0x20 #define PKT3_STRMOUT_BUFFER_UPDATE 0x34 @@ -126,175 +124,12 @@ #define PREDICATION_DRAW_NOT_VISIBLE (0 << 8) #define PREDICATION_DRAW_VISIBLE (1 << 8) -/* R600-R700*/ -#define R_008490_CP_STRMOUT_CNTL 0x008490 -#define S_008490_OFFSET_UPDATE_DONE(x) (((unsigned)(x) & 0x1) << 0) -#define R_028AB0_VGT_STRMOUT_EN 0x028AB0 -#define S_028AB0_STREAMOUT(x) (((unsigned)(x) & 0x1) << 0) -#define G_028AB0_STREAMOUT(x) (((x) >> 0) & 0x1) -#define C_028AB0_STREAMOUT 0xFFFFFFFE -#define R_028B20_VGT_STRMOUT_BUFFER_EN 0x028B20 -#define S_028B20_BUFFER_0_EN(x) (((unsigned)(x) & 0x1) << 0) -#define G_028B20_BUFFER_0_EN(x) (((x) >> 0) & 0x1) -#define C_028B20_BUFFER_0_EN 0xFFFFFFFE -#define S_028B20_BUFFER_1_EN(x) (((unsigned)(x) & 0x1) << 1) -#define G_028B20_BUFFER_1_EN(x) (((x) >> 1) & 0x1) -#define C_028B20_BUFFER_1_EN 0xFFFFFFFD -#define S_028B20_BUFFER_2_EN(x) (((unsigned)(x) & 0x1) << 2) -#define G_028B20_BUFFER_2_EN(x) (((x) >> 2) & 0x1) -#define C_028B20_BUFFER_2_EN 0xFFFFFFFB -#define S_028B20_BUFFER_3_EN(x) (((unsigned)(x) & 0x1) << 3) -#define G_028B20_BUFFER_3_EN(x) (((x) >> 3) & 0x1) -#define C_028B20_BUFFER_3_EN 0xFFFFFFF7 -#define R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 0x028AD0 - #define V_0280A0_SWAP_STD 0x00000000 #define V_0280A0_SWAP_ALT 0x00000001 #define V_0280A0_SWAP_STD_REV 0x00000002 #define V_0280A0_SWAP_ALT_REV 0x00000003 -/* EG+ */ -#define R_0084FC_CP_STRMOUT_CNTL 0x0084FC -#define S_0084FC_OFFSET_UPDATE_DONE(x) (((unsigned)(x) & 0x1) << 0) -#define R_028B94_VGT_STRMOUT_CONFIG 0x028B94 -#define S_028B94_STREAMOUT_0_EN(x) (((unsigned)(x) & 0x1) << 0) -#define G_028B94_STREAMOUT_0_EN(x) (((x) >> 0) & 0x1) -#define C_028B94_STREAMOUT_0_EN 0xFFFFFFFE -#define S_028B94_STREAMOUT_1_EN(x) (((unsigned)(x) & 0x1) << 1) -#define G_028B94_STREAMOUT_1_EN(x) (((x) >> 1) & 0x1) -#define C_028B94_STREAMOUT_1_EN 0xFFFFFFFD -#define S_028B94_STREAMOUT_2_EN(x) (((unsigned)(x) & 0x1) << 2) -#define G_028B94_STREAMOUT_2_EN(x) (((x) >> 2) & 0x1) -#define C_028B94_STREAMOUT_2_EN 0xFFFFFFFB -#define S_028B94_STREAMOUT_3_EN(x) (((unsigned)(x) & 0x1) << 3) -#define G_028B94_STREAMOUT_3_EN(x) (((x) >> 3) & 0x1) -#define C_028B94_STREAMOUT_3_EN 0xFFFFFFF7 -#define S_028B94_RAST_STREAM(x) (((unsigned)(x) & 0x07) << 4) -#define G_028B94_RAST_STREAM(x) (((x) >> 4) & 0x07) -#define C_028B94_RAST_STREAM 0xFFFFFF8F -#define S_028B94_RAST_STREAM_MASK(x) (((unsigned)(x) & 0x0F) << 8) /* SI+ */ -#define G_028B94_RAST_STREAM_MASK(x) (((x) >> 8) & 0x0F) -#define C_028B94_RAST_STREAM_MASK 0xFFFFF0FF -#define S_028B94_USE_RAST_STREAM_MASK(x) (((unsigned)(x) & 0x1) << 31) /* SI+ */ -#define G_028B94_USE_RAST_STREAM_MASK(x) (((x) >> 31) & 0x1) -#define C_028B94_USE_RAST_STREAM_MASK 0x7FFFFFFF -#define R_028B98_VGT_STRMOUT_BUFFER_CONFIG 0x028B98 -#define S_028B98_STREAM_0_BUFFER_EN(x) (((unsigned)(x) & 0x0F) << 0) -#define G_028B98_STREAM_0_BUFFER_EN(x) (((x) >> 0) & 0x0F) -#define C_028B98_STREAM_0_BUFFER_EN 0xFFFFFFF0 -#define S_028B98_STREAM_1_BUFFER_EN(x) (((unsigned)(x) & 0x0F) << 4) -#define G_028B98_STREAM_1_BUFFER_EN(x) (((x) >> 4) & 0x0F) -#define C_028B98_STREAM_1_BUFFER_EN 0xFFFFFF0F -#define S_028B98_STREAM_2_BUFFER_EN(x) (((unsigned)(x) & 0x0F) << 8) -#define G_028B98_STREAM_2_BUFFER_EN(x) (((x) >> 8) & 0x0F) -#define C_028B98_STREAM_2_BUFFER_EN 0xFFFFF0FF -#define S_028B98_STREAM_3_BUFFER_EN(x) (((unsigned)(x) & 0x0F) << 12) -#define G_028B98_STREAM_3_BUFFER_EN(x) (((x) >> 12) & 0x0F) -#define C_028B98_STREAM_3_BUFFER_EN 0xFFFF0FFF - -#define EG_R_028A4C_PA_SC_MODE_CNTL_1 0x028A4C -#define EG_S_028A4C_PS_ITER_SAMPLE(x) (((unsigned)(x) & 0x1) << 16) -#define EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(x) (((unsigned)(x) & 0x1) << 25) -#define EG_S_028A4C_FORCE_EOV_REZ_ENABLE(x) (((unsigned)(x) & 0x1) << 26) - -#define CM_R_028804_DB_EQAA 0x00028804 -#define S_028804_MAX_ANCHOR_SAMPLES(x) (((unsigned)(x) & 0x07) << 0) -#define G_028804_MAX_ANCHOR_SAMPLES(x) (((x) >> 0) & 0x07) -#define C_028804_MAX_ANCHOR_SAMPLES 0xFFFFFFF8 -#define S_028804_PS_ITER_SAMPLES(x) (((unsigned)(x) & 0x07) << 4) -#define G_028804_PS_ITER_SAMPLES(x) (((x) >> 4) & 0x07) -#define C_028804_PS_ITER_SAMPLES 0xFFFFFF8F -#define S_028804_MASK_EXPORT_NUM_SAMPLES(x) (((unsigned)(x) & 0x07) << 8) -#define G_028804_MASK_EXPORT_NUM_SAMPLES(x) (((x) >> 8) & 0x07) -#define C_028804_MASK_EXPORT_NUM_SAMPLES 0xFFFFF8FF -#define S_028804_ALPHA_TO_MASK_NUM_SAMPLES(x) (((unsigned)(x) & 0x07) << 12) -#define G_028804_ALPHA_TO_MASK_NUM_SAMPLES(x) (((x) >> 12) & 0x07) -#define C_028804_ALPHA_TO_MASK_NUM_SAMPLES 0xFFFF8FFF -#define S_028804_HIGH_QUALITY_INTERSECTIONS(x) (((unsigned)(x) & 0x1) << 16) -#define G_028804_HIGH_QUALITY_INTERSECTIONS(x) (((x) >> 16) & 0x1) -#define C_028804_HIGH_QUALITY_INTERSECTIONS 0xFFFEFFFF -#define S_028804_INCOHERENT_EQAA_READS(x) (((unsigned)(x) & 0x1) << 17) -#define G_028804_INCOHERENT_EQAA_READS(x) (((x) >> 17) & 0x1) -#define C_028804_INCOHERENT_EQAA_READS 0xFFFDFFFF -#define S_028804_INTERPOLATE_COMP_Z(x) (((unsigned)(x) & 0x1) << 18) -#define G_028804_INTERPOLATE_COMP_Z(x) (((x) >> 18) & 0x1) -#define C_028804_INTERPOLATE_COMP_Z 0xFFFBFFFF -#define S_028804_INTERPOLATE_SRC_Z(x) (((unsigned)(x) & 0x1) << 19) -#define G_028804_INTERPOLATE_SRC_Z(x) (((x) >> 19) & 0x1) -#define C_028804_INTERPOLATE_SRC_Z 0xFFF7FFFF -#define S_028804_STATIC_ANCHOR_ASSOCIATIONS(x) (((unsigned)(x) & 0x1) << 20) -#define G_028804_STATIC_ANCHOR_ASSOCIATIONS(x) (((x) >> 20) & 0x1) -#define C_028804_STATIC_ANCHOR_ASSOCIATIONS 0xFFEFFFFF -#define S_028804_ALPHA_TO_MASK_EQAA_DISABLE(x) (((unsigned)(x) & 0x1) << 21) -#define G_028804_ALPHA_TO_MASK_EQAA_DISABLE(x) (((x) >> 21) & 0x1) -#define C_028804_ALPHA_TO_MASK_EQAA_DISABLE 0xFFDFFFFF -#define S_028804_OVERRASTERIZATION_AMOUNT(x) (((unsigned)(x) & 0x07) << 24) -#define G_028804_OVERRASTERIZATION_AMOUNT(x) (((x) >> 24) & 0x07) -#define C_028804_OVERRASTERIZATION_AMOUNT 0xF8FFFFFF -#define S_028804_ENABLE_POSTZ_OVERRASTERIZATION(x) (((unsigned)(x) & 0x1) << 27) -#define G_028804_ENABLE_POSTZ_OVERRASTERIZATION(x) (((x) >> 27) & 0x1) -#define C_028804_ENABLE_POSTZ_OVERRASTERIZATION 0xF7FFFFFF -#define CM_R_028BDC_PA_SC_LINE_CNTL 0x28bdc -#define S_028BDC_EXPAND_LINE_WIDTH(x) (((unsigned)(x) & 0x1) << 9) -#define G_028BDC_EXPAND_LINE_WIDTH(x) (((x) >> 9) & 0x1) -#define C_028BDC_EXPAND_LINE_WIDTH 0xFFFFFDFF -#define S_028BDC_LAST_PIXEL(x) (((unsigned)(x) & 0x1) << 10) -#define G_028BDC_LAST_PIXEL(x) (((x) >> 10) & 0x1) -#define C_028BDC_LAST_PIXEL 0xFFFFFBFF -#define S_028BDC_PERPENDICULAR_ENDCAP_ENA(x) (((unsigned)(x) & 0x1) << 11) -#define G_028BDC_PERPENDICULAR_ENDCAP_ENA(x) (((x) >> 11) & 0x1) -#define C_028BDC_PERPENDICULAR_ENDCAP_ENA 0xFFFFF7FF -#define S_028BDC_DX10_DIAMOND_TEST_ENA(x) (((unsigned)(x) & 0x1) << 12) -#define G_028BDC_DX10_DIAMOND_TEST_ENA(x) (((x) >> 12) & 0x1) -#define C_028BDC_DX10_DIAMOND_TEST_ENA 0xFFFFEFFF -#define CM_R_028BE0_PA_SC_AA_CONFIG 0x28be0 -#define S_028BE0_MSAA_NUM_SAMPLES(x) (((unsigned)(x) & 0x07) << 0) -#define G_028BE0_MSAA_NUM_SAMPLES(x) (((x) >> 0) & 0x07) -#define C_028BE0_MSAA_NUM_SAMPLES 0xFFFFFFF8 -#define S_028BE0_AA_MASK_CENTROID_DTMN(x) (((unsigned)(x) & 0x1) << 4) -#define G_028BE0_AA_MASK_CENTROID_DTMN(x) (((x) >> 4) & 0x1) -#define C_028BE0_AA_MASK_CENTROID_DTMN 0xFFFFFFEF -#define S_028BE0_MAX_SAMPLE_DIST(x) (((unsigned)(x) & 0x0F) << 13) -#define G_028BE0_MAX_SAMPLE_DIST(x) (((x) >> 13) & 0x0F) -#define C_028BE0_MAX_SAMPLE_DIST 0xFFFE1FFF -#define S_028BE0_MSAA_EXPOSED_SAMPLES(x) (((unsigned)(x) & 0x07) << 20) -#define G_028BE0_MSAA_EXPOSED_SAMPLES(x) (((x) >> 20) & 0x07) -#define C_028BE0_MSAA_EXPOSED_SAMPLES 0xFF8FFFFF -#define S_028BE0_DETAIL_TO_EXPOSED_MODE(x) (((unsigned)(x) & 0x03) << 24) -#define G_028BE0_DETAIL_TO_EXPOSED_MODE(x) (((x) >> 24) & 0x03) -#define C_028BE0_DETAIL_TO_EXPOSED_MODE 0xFCFFFFFF -#define CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 0x28bf8 -#define CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 0x28c08 -#define CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 0x28c18 -#define CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 0x28c28 - #define EG_S_028C70_FAST_CLEAR(x) (((unsigned)(x) & 0x1) << 17) #define SI_S_028C70_FAST_CLEAR(x) (((unsigned)(x) & 0x1) << 13) -/*CIK+*/ -#define R_0300FC_CP_STRMOUT_CNTL 0x0300FC - -#define R600_R_028C0C_PA_CL_GB_VERT_CLIP_ADJ 0x028C0C -#define CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ 0x28be8 -#define R_02843C_PA_CL_VPORT_XSCALE 0x02843C - -#define R_028250_PA_SC_VPORT_SCISSOR_0_TL 0x028250 -#define S_028250_TL_X(x) (((unsigned)(x) & 0x7FFF) << 0) -#define G_028250_TL_X(x) (((x) >> 0) & 0x7FFF) -#define C_028250_TL_X 0xFFFF8000 -#define S_028250_TL_Y(x) (((unsigned)(x) & 0x7FFF) << 16) -#define G_028250_TL_Y(x) (((x) >> 16) & 0x7FFF) -#define C_028250_TL_Y 0x8000FFFF -#define S_028250_WINDOW_OFFSET_DISABLE(x) (((unsigned)(x) & 0x1) << 31) -#define G_028250_WINDOW_OFFSET_DISABLE(x) (((x) >> 31) & 0x1) -#define C_028250_WINDOW_OFFSET_DISABLE 0x7FFFFFFF -#define S_028254_BR_X(x) (((unsigned)(x) & 0x7FFF) << 0) -#define G_028254_BR_X(x) (((x) >> 0) & 0x7FFF) -#define C_028254_BR_X 0xFFFF8000 -#define S_028254_BR_Y(x) (((unsigned)(x) & 0x7FFF) << 16) -#define G_028254_BR_Y(x) (((x) >> 16) & 0x7FFF) -#define C_028254_BR_Y 0x8000FFFF -#define R_0282D0_PA_SC_VPORT_ZMIN_0 0x0282D0 -#define R_0282D4_PA_SC_VPORT_ZMAX_0 0x0282D4 - #endif diff --git a/src/amd/common/sid.h b/src/amd/common/sid.h index 1016f674707..15ebd9b267f 100644 --- a/src/amd/common/sid.h +++ b/src/amd/common/sid.h @@ -113,6 +113,13 @@ #define PKT3_INDIRECT_BUFFER_SI 0x32 /* not on CIK */ #define PKT3_INDIRECT_BUFFER_CONST 0x33 #define PKT3_STRMOUT_BUFFER_UPDATE 0x34 +#define STRMOUT_STORE_BUFFER_FILLED_SIZE 1 +#define STRMOUT_OFFSET_SOURCE(x) (((unsigned)(x) & 0x3) << 1) +#define STRMOUT_OFFSET_FROM_PACKET 0 +#define STRMOUT_OFFSET_FROM_VGT_FILLED_SIZE 1 +#define STRMOUT_OFFSET_FROM_MEM 2 +#define STRMOUT_OFFSET_NONE 3 +#define STRMOUT_SELECT_BUFFER(x) (((unsigned)(x) & 0x3) << 8) #define PKT3_DRAW_INDEX_OFFSET_2 0x35 #define PKT3_WRITE_DATA 0x37 #define R_370_CONTROL 0x370 /* 0x[packet number][word index] */ @@ -137,6 +144,7 @@ #define PKT3_MPEG_INDEX 0x3A /* not on CIK */ #define PKT3_WAIT_REG_MEM 0x3C #define WAIT_REG_MEM_EQUAL 3 +#define WAIT_REG_MEM_MEM_SPACE(x) (((unsigned)(x) & 0x3) << 4) #define PKT3_MEM_WRITE 0x3D /* not on CIK */ #define PKT3_INDIRECT_BUFFER_CIK 0x3F /* new on CIK */ #define R_3F0_IB_BASE_LO 0x3F0 @@ -156,6 +164,7 @@ #define COPY_DATA_IMM 5 #define COPY_DATA_TIMESTAMP 9 #define COPY_DATA_DST_SEL(x) (((unsigned)(x) & 0xf) << 8) +#define COPY_DATA_MEM_ASYNC 5 #define COPY_DATA_COUNT_SEL (1 << 16) #define COPY_DATA_WR_CONFIRM (1 << 20) #define PKT3_PFP_SYNC_ME 0x42 @@ -164,6 +173,14 @@ #define PKT3_COND_WRITE 0x45 #define PKT3_EVENT_WRITE 0x46 #define PKT3_EVENT_WRITE_EOP 0x47 /* not on GFX9 */ +#define EOP_INT_SEL(x) ((x) << 24) +#define EOP_INT_SEL_NONE 0 +#define EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM 3 +#define EOP_DATA_SEL(x) ((x) << 29) +#define EOP_DATA_SEL_DISCARD 0 +#define EOP_DATA_SEL_VALUE_32BIT 1 +#define EOP_DATA_SEL_VALUE_64BIT 2 +#define EOP_DATA_SEL_TIMESTAMP 3 /* CP DMA bug: Any use of CP_DMA.DST_SEL=TC must be avoided when EOS packets * are used. Use DST_SEL=MC instead. For prefetch, use SRC_SEL=TC and * DST_SEL=MC. Only CIK chips are affected. diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 6a0640e2776..aaa2a5064ee 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -525,13 +525,13 @@ radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer, radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[0]); radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[1]); - radeon_set_context_reg(cmd_buffer->cs, CM_R_028804_DB_EQAA, ms->db_eqaa); - radeon_set_context_reg(cmd_buffer->cs, EG_R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1); + radeon_set_context_reg(cmd_buffer->cs, R_028804_DB_EQAA, ms->db_eqaa); + radeon_set_context_reg(cmd_buffer->cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1); if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples) return; - radeon_set_context_reg_seq(cmd_buffer->cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2); + radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2); radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl); radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config); diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 7266fe02d67..37512e82dd9 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -1071,8 +1071,8 @@ radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline, S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) | S_028A4C_TILE_WALK_ORDER_ENABLE(1) | S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) | - EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) | - EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1); + S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) | + S_028A4C_FORCE_EOV_REZ_ENABLE(1); ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->device->physical_device->rad_info.chip_class >= GFX9); if (ms->num_samples > 1) { @@ -1087,7 +1087,7 @@ radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline, ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) | S_028BE0_MAX_SAMPLE_DIST(radv_cayman_get_maxdist(log_samples)) | S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /* CM_R_028BE0_PA_SC_AA_CONFIG */ - ms->pa_sc_mode_cntl_1 |= EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1); + ms->pa_sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1); } const struct VkPipelineRasterizationStateRasterizationOrderAMD *raster_order = diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c index b8eb9b4c7e1..8011eaf1384 100644 --- a/src/amd/vulkan/si_cmd_buffer.c +++ b/src/amd/vulkan/si_cmd_buffer.c @@ -1425,25 +1425,25 @@ void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_sampl switch (nr_samples) { default: case 1: - radeon_set_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 0); - radeon_set_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, 0); - radeon_set_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, 0); - radeon_set_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, 0); + radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 0); + radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, 0); + radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, 0); + radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, 0); break; case 2: - radeon_set_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, eg_sample_locs_2x[0]); - radeon_set_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, eg_sample_locs_2x[1]); - radeon_set_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, eg_sample_locs_2x[2]); - radeon_set_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, eg_sample_locs_2x[3]); + radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, eg_sample_locs_2x[0]); + radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, eg_sample_locs_2x[1]); + radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, eg_sample_locs_2x[2]); + radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, eg_sample_locs_2x[3]); break; case 4: - radeon_set_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, eg_sample_locs_4x[0]); - radeon_set_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, eg_sample_locs_4x[1]); - radeon_set_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, eg_sample_locs_4x[2]); - radeon_set_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, eg_sample_locs_4x[3]); + radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, eg_sample_locs_4x[0]); + radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, eg_sample_locs_4x[1]); + radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, eg_sample_locs_4x[2]); + radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, eg_sample_locs_4x[3]); break; case 8: - radeon_set_context_reg_seq(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 14); + radeon_set_context_reg_seq(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 14); radeon_emit(cs, cm_sample_locs_8x[0]); radeon_emit(cs, cm_sample_locs_8x[4]); radeon_emit(cs, 0); @@ -1460,7 +1460,7 @@ void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_sampl radeon_emit(cs, cm_sample_locs_8x[7]); break; case 16: - radeon_set_context_reg_seq(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 16); + radeon_set_context_reg_seq(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 16); radeon_emit(cs, cm_sample_locs_16x[0]); radeon_emit(cs, cm_sample_locs_16x[4]); radeon_emit(cs, cm_sample_locs_16x[8]); diff --git a/src/gallium/drivers/r600/cayman_msaa.c b/src/gallium/drivers/r600/cayman_msaa.c index 33f1040185a..6bc307a4bc1 100644 --- a/src/gallium/drivers/r600/cayman_msaa.c +++ b/src/gallium/drivers/r600/cayman_msaa.c @@ -25,6 +25,7 @@ */ #include "r600_cs.h" +#include "evergreend.h" /* 2xMSAA * There are two locations (4, 4), (-4, -4). */ diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c index 5e9c77d7921..4ffc2684d56 100644 --- a/src/gallium/drivers/r600/evergreen_state.c +++ b/src/gallium/drivers/r600/evergreen_state.c @@ -1650,7 +1650,7 @@ static void evergreen_emit_msaa_state(struct r600_context *rctx, int nr_samples, S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */ radeon_emit(cs, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples)) | S_028C04_MAX_SAMPLE_DIST(max_dist)); /* R_028C04_PA_SC_AA_CONFIG */ - radeon_set_context_reg(cs, EG_R_028A4C_PA_SC_MODE_CNTL_1, + radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1, EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1) | EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) | EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1)); @@ -1658,7 +1658,7 @@ static void evergreen_emit_msaa_state(struct r600_context *rctx, int nr_samples, radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2); radeon_emit(cs, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */ radeon_emit(cs, 0); /* R_028C04_PA_SC_AA_CONFIG */ - radeon_set_context_reg(cs, EG_R_028A4C_PA_SC_MODE_CNTL_1, + radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1, EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) | EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1)); } diff --git a/src/gallium/drivers/r600/evergreend.h b/src/gallium/drivers/r600/evergreend.h index 2e54928f08c..af79bb74e60 100644 --- a/src/gallium/drivers/r600/evergreend.h +++ b/src/gallium/drivers/r600/evergreend.h @@ -201,6 +201,116 @@ /* Registers */ #define R_0084FC_CP_STRMOUT_CNTL 0x0084FC #define S_0084FC_OFFSET_UPDATE_DONE(x) (((unsigned)(x) & 0x1) << 0) +#define R_028B94_VGT_STRMOUT_CONFIG 0x028B94 +#define S_028B94_STREAMOUT_0_EN(x) (((unsigned)(x) & 0x1) << 0) +#define G_028B94_STREAMOUT_0_EN(x) (((x) >> 0) & 0x1) +#define C_028B94_STREAMOUT_0_EN 0xFFFFFFFE +#define S_028B94_STREAMOUT_1_EN(x) (((unsigned)(x) & 0x1) << 1) +#define G_028B94_STREAMOUT_1_EN(x) (((x) >> 1) & 0x1) +#define C_028B94_STREAMOUT_1_EN 0xFFFFFFFD +#define S_028B94_STREAMOUT_2_EN(x) (((unsigned)(x) & 0x1) << 2) +#define G_028B94_STREAMOUT_2_EN(x) (((x) >> 2) & 0x1) +#define C_028B94_STREAMOUT_2_EN 0xFFFFFFFB +#define S_028B94_STREAMOUT_3_EN(x) (((unsigned)(x) & 0x1) << 3) +#define G_028B94_STREAMOUT_3_EN(x) (((x) >> 3) & 0x1) +#define C_028B94_STREAMOUT_3_EN 0xFFFFFFF7 +#define S_028B94_RAST_STREAM(x) (((unsigned)(x) & 0x07) << 4) +#define G_028B94_RAST_STREAM(x) (((x) >> 4) & 0x07) +#define C_028B94_RAST_STREAM 0xFFFFFF8F +#define S_028B94_RAST_STREAM_MASK(x) (((unsigned)(x) & 0x0F) << 8) /* SI+ */ +#define G_028B94_RAST_STREAM_MASK(x) (((x) >> 8) & 0x0F) +#define C_028B94_RAST_STREAM_MASK 0xFFFFF0FF +#define S_028B94_USE_RAST_STREAM_MASK(x) (((unsigned)(x) & 0x1) << 31) /* SI+ */ +#define G_028B94_USE_RAST_STREAM_MASK(x) (((x) >> 31) & 0x1) +#define C_028B94_USE_RAST_STREAM_MASK 0x7FFFFFFF +#define R_028B98_VGT_STRMOUT_BUFFER_CONFIG 0x028B98 +#define S_028B98_STREAM_0_BUFFER_EN(x) (((unsigned)(x) & 0x0F) << 0) +#define G_028B98_STREAM_0_BUFFER_EN(x) (((x) >> 0) & 0x0F) +#define C_028B98_STREAM_0_BUFFER_EN 0xFFFFFFF0 +#define S_028B98_STREAM_1_BUFFER_EN(x) (((unsigned)(x) & 0x0F) << 4) +#define G_028B98_STREAM_1_BUFFER_EN(x) (((x) >> 4) & 0x0F) +#define C_028B98_STREAM_1_BUFFER_EN 0xFFFFFF0F +#define S_028B98_STREAM_2_BUFFER_EN(x) (((unsigned)(x) & 0x0F) << 8) +#define G_028B98_STREAM_2_BUFFER_EN(x) (((x) >> 8) & 0x0F) +#define C_028B98_STREAM_2_BUFFER_EN 0xFFFFF0FF +#define S_028B98_STREAM_3_BUFFER_EN(x) (((unsigned)(x) & 0x0F) << 12) +#define G_028B98_STREAM_3_BUFFER_EN(x) (((x) >> 12) & 0x0F) +#define C_028B98_STREAM_3_BUFFER_EN 0xFFFF0FFF + +#define EG_R_028A4C_PA_SC_MODE_CNTL_1 0x028A4C +#define EG_S_028A4C_PS_ITER_SAMPLE(x) (((unsigned)(x) & 0x1) << 16) +#define EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(x) (((unsigned)(x) & 0x1) << 25) +#define EG_S_028A4C_FORCE_EOV_REZ_ENABLE(x) (((unsigned)(x) & 0x1) << 26) +#define CM_R_028804_DB_EQAA 0x00028804 +#define S_028804_MAX_ANCHOR_SAMPLES(x) (((unsigned)(x) & 0x07) << 0) +#define G_028804_MAX_ANCHOR_SAMPLES(x) (((x) >> 0) & 0x07) +#define C_028804_MAX_ANCHOR_SAMPLES 0xFFFFFFF8 +#define S_028804_PS_ITER_SAMPLES(x) (((unsigned)(x) & 0x07) << 4) +#define G_028804_PS_ITER_SAMPLES(x) (((x) >> 4) & 0x07) +#define C_028804_PS_ITER_SAMPLES 0xFFFFFF8F +#define S_028804_MASK_EXPORT_NUM_SAMPLES(x) (((unsigned)(x) & 0x07) << 8) +#define G_028804_MASK_EXPORT_NUM_SAMPLES(x) (((x) >> 8) & 0x07) +#define C_028804_MASK_EXPORT_NUM_SAMPLES 0xFFFFF8FF +#define S_028804_ALPHA_TO_MASK_NUM_SAMPLES(x) (((unsigned)(x) & 0x07) << 12) +#define G_028804_ALPHA_TO_MASK_NUM_SAMPLES(x) (((x) >> 12) & 0x07) +#define C_028804_ALPHA_TO_MASK_NUM_SAMPLES 0xFFFF8FFF +#define S_028804_HIGH_QUALITY_INTERSECTIONS(x) (((unsigned)(x) & 0x1) << 16) +#define G_028804_HIGH_QUALITY_INTERSECTIONS(x) (((x) >> 16) & 0x1) +#define C_028804_HIGH_QUALITY_INTERSECTIONS 0xFFFEFFFF +#define S_028804_INCOHERENT_EQAA_READS(x) (((unsigned)(x) & 0x1) << 17) +#define G_028804_INCOHERENT_EQAA_READS(x) (((x) >> 17) & 0x1) +#define C_028804_INCOHERENT_EQAA_READS 0xFFFDFFFF +#define S_028804_INTERPOLATE_COMP_Z(x) (((unsigned)(x) & 0x1) << 18) +#define G_028804_INTERPOLATE_COMP_Z(x) (((x) >> 18) & 0x1) +#define C_028804_INTERPOLATE_COMP_Z 0xFFFBFFFF +#define S_028804_INTERPOLATE_SRC_Z(x) (((unsigned)(x) & 0x1) << 19) +#define G_028804_INTERPOLATE_SRC_Z(x) (((x) >> 19) & 0x1) +#define C_028804_INTERPOLATE_SRC_Z 0xFFF7FFFF +#define S_028804_STATIC_ANCHOR_ASSOCIATIONS(x) (((unsigned)(x) & 0x1) << 20) +#define G_028804_STATIC_ANCHOR_ASSOCIATIONS(x) (((x) >> 20) & 0x1) +#define C_028804_STATIC_ANCHOR_ASSOCIATIONS 0xFFEFFFFF +#define S_028804_ALPHA_TO_MASK_EQAA_DISABLE(x) (((unsigned)(x) & 0x1) << 21) +#define G_028804_ALPHA_TO_MASK_EQAA_DISABLE(x) (((x) >> 21) & 0x1) +#define C_028804_ALPHA_TO_MASK_EQAA_DISABLE 0xFFDFFFFF +#define S_028804_OVERRASTERIZATION_AMOUNT(x) (((unsigned)(x) & 0x07) << 24) +#define G_028804_OVERRASTERIZATION_AMOUNT(x) (((x) >> 24) & 0x07) +#define C_028804_OVERRASTERIZATION_AMOUNT 0xF8FFFFFF +#define S_028804_ENABLE_POSTZ_OVERRASTERIZATION(x) (((unsigned)(x) & 0x1) << 27) +#define G_028804_ENABLE_POSTZ_OVERRASTERIZATION(x) (((x) >> 27) & 0x1) +#define C_028804_ENABLE_POSTZ_OVERRASTERIZATION 0xF7FFFFFF +#define CM_R_028BDC_PA_SC_LINE_CNTL 0x28bdc +#define S_028BDC_EXPAND_LINE_WIDTH(x) (((unsigned)(x) & 0x1) << 9) +#define G_028BDC_EXPAND_LINE_WIDTH(x) (((x) >> 9) & 0x1) +#define C_028BDC_EXPAND_LINE_WIDTH 0xFFFFFDFF +#define S_028BDC_LAST_PIXEL(x) (((unsigned)(x) & 0x1) << 10) +#define G_028BDC_LAST_PIXEL(x) (((x) >> 10) & 0x1) +#define C_028BDC_LAST_PIXEL 0xFFFFFBFF +#define S_028BDC_PERPENDICULAR_ENDCAP_ENA(x) (((unsigned)(x) & 0x1) << 11) +#define G_028BDC_PERPENDICULAR_ENDCAP_ENA(x) (((x) >> 11) & 0x1) +#define C_028BDC_PERPENDICULAR_ENDCAP_ENA 0xFFFFF7FF +#define S_028BDC_DX10_DIAMOND_TEST_ENA(x) (((unsigned)(x) & 0x1) << 12) +#define G_028BDC_DX10_DIAMOND_TEST_ENA(x) (((x) >> 12) & 0x1) +#define C_028BDC_DX10_DIAMOND_TEST_ENA 0xFFFFEFFF +#define CM_R_028BE0_PA_SC_AA_CONFIG 0x28be0 +#define S_028BE0_MSAA_NUM_SAMPLES(x) (((unsigned)(x) & 0x07) << 0) +#define G_028BE0_MSAA_NUM_SAMPLES(x) (((x) >> 0) & 0x07) +#define C_028BE0_MSAA_NUM_SAMPLES 0xFFFFFFF8 +#define S_028BE0_AA_MASK_CENTROID_DTMN(x) (((unsigned)(x) & 0x1) << 4) +#define G_028BE0_AA_MASK_CENTROID_DTMN(x) (((x) >> 4) & 0x1) +#define C_028BE0_AA_MASK_CENTROID_DTMN 0xFFFFFFEF +#define S_028BE0_MAX_SAMPLE_DIST(x) (((unsigned)(x) & 0x0F) << 13) +#define G_028BE0_MAX_SAMPLE_DIST(x) (((x) >> 13) & 0x0F) +#define C_028BE0_MAX_SAMPLE_DIST 0xFFFE1FFF +#define S_028BE0_MSAA_EXPOSED_SAMPLES(x) (((unsigned)(x) & 0x07) << 20) +#define G_028BE0_MSAA_EXPOSED_SAMPLES(x) (((x) >> 20) & 0x07) +#define C_028BE0_MSAA_EXPOSED_SAMPLES 0xFF8FFFFF +#define S_028BE0_DETAIL_TO_EXPOSED_MODE(x) (((unsigned)(x) & 0x03) << 24) +#define G_028BE0_DETAIL_TO_EXPOSED_MODE(x) (((x) >> 24) & 0x03) +#define C_028BE0_DETAIL_TO_EXPOSED_MODE 0xFCFFFFFF +#define CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 0x28bf8 +#define CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 0x28c08 +#define CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 0x28c18 +#define CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 0x28c28 #define R_008960_VGT_STRMOUT_BUFFER_FILLED_SIZE_0 0x008960 /* read-only */ #define R_008964_VGT_STRMOUT_BUFFER_FILLED_SIZE_1 0x008964 /* read-only */ #define R_008968_VGT_STRMOUT_BUFFER_FILLED_SIZE_2 0x008968 /* read-only */ diff --git a/src/gallium/drivers/r600/r600_streamout.c b/src/gallium/drivers/r600/r600_streamout.c index a18089a3b39..6d45a07d5c9 100644 --- a/src/gallium/drivers/r600/r600_streamout.c +++ b/src/gallium/drivers/r600/r600_streamout.c @@ -28,6 +28,11 @@ #include "r600_cs.h" #include "util/u_memory.h" +#include "evergreend.h" + +#define R_008490_CP_STRMOUT_CNTL 0x008490 +#define R_028AB0_VGT_STRMOUT_EN 0x028AB0 +#define R_028B20_VGT_STRMOUT_BUFFER_EN 0x028B20 static void r600_set_streamout_enable(struct r600_common_context *rctx, bool enable); @@ -157,9 +162,7 @@ static void r600_flush_vgt_streamout(struct r600_common_context *rctx) unsigned reg_strmout_cntl; /* The register is at different places on different ASICs. */ - if (rctx->chip_class >= CIK) { - reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL; - } else if (rctx->chip_class >= EVERGREEN) { + if (rctx->chip_class >= EVERGREEN) { reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL; } else { reg_strmout_cntl = R_008490_CP_STRMOUT_CNTL; @@ -178,8 +181,8 @@ static void r600_flush_vgt_streamout(struct r600_common_context *rctx) radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */ radeon_emit(cs, reg_strmout_cntl >> 2); /* register */ radeon_emit(cs, 0); - radeon_emit(cs, S_008490_OFFSET_UPDATE_DONE(1)); /* reference value */ - radeon_emit(cs, S_008490_OFFSET_UPDATE_DONE(1)); /* mask */ + radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */ + radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */ radeon_emit(cs, 4); /* poll interval */ } @@ -326,7 +329,6 @@ static void r600_emit_streamout_enable(struct r600_common_context *rctx, strmout_config_reg = R_028B94_VGT_STRMOUT_CONFIG; strmout_config_val |= - S_028B94_RAST_STREAM(0) | S_028B94_STREAMOUT_1_EN(r600_get_strmout_en(rctx)) | S_028B94_STREAMOUT_2_EN(r600_get_strmout_en(rctx)) | S_028B94_STREAMOUT_3_EN(r600_get_strmout_en(rctx)); diff --git a/src/gallium/drivers/r600/r600_viewport.c b/src/gallium/drivers/r600/r600_viewport.c index 2de13820545..0797f932fb8 100644 --- a/src/gallium/drivers/r600/r600_viewport.c +++ b/src/gallium/drivers/r600/r600_viewport.c @@ -25,6 +25,29 @@ #include "util/u_viewport.h" #include "tgsi/tgsi_scan.h" +#define R600_R_028C0C_PA_CL_GB_VERT_CLIP_ADJ 0x028C0C +#define CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ 0x28be8 +#define R_02843C_PA_CL_VPORT_XSCALE 0x02843C + +#define R_028250_PA_SC_VPORT_SCISSOR_0_TL 0x028250 +#define S_028250_TL_X(x) (((unsigned)(x) & 0x7FFF) << 0) +#define G_028250_TL_X(x) (((x) >> 0) & 0x7FFF) +#define C_028250_TL_X 0xFFFF8000 +#define S_028250_TL_Y(x) (((unsigned)(x) & 0x7FFF) << 16) +#define G_028250_TL_Y(x) (((x) >> 16) & 0x7FFF) +#define C_028250_TL_Y 0x8000FFFF +#define S_028250_WINDOW_OFFSET_DISABLE(x) (((unsigned)(x) & 0x1) << 31) +#define G_028250_WINDOW_OFFSET_DISABLE(x) (((x) >> 31) & 0x1) +#define C_028250_WINDOW_OFFSET_DISABLE 0x7FFFFFFF +#define S_028254_BR_X(x) (((unsigned)(x) & 0x7FFF) << 0) +#define G_028254_BR_X(x) (((x) >> 0) & 0x7FFF) +#define C_028254_BR_X 0xFFFF8000 +#define S_028254_BR_Y(x) (((unsigned)(x) & 0x7FFF) << 16) +#define G_028254_BR_Y(x) (((x) >> 16) & 0x7FFF) +#define C_028254_BR_Y 0x8000FFFF +#define R_0282D0_PA_SC_VPORT_ZMIN_0 0x0282D0 +#define R_0282D4_PA_SC_VPORT_ZMAX_0 0x0282D4 + #define GET_MAX_SCISSOR(rctx) (rctx->chip_class >= EVERGREEN ? 16384 : 8192) static void r600_set_scissor_states(struct pipe_context *ctx, diff --git a/src/gallium/drivers/radeon/r600_cs.h b/src/gallium/drivers/radeon/r600_cs.h index b4af5a6b633..5bfce1ca724 100644 --- a/src/gallium/drivers/radeon/r600_cs.h +++ b/src/gallium/drivers/radeon/r600_cs.h @@ -31,7 +31,7 @@ #define R600_CS_H #include "r600_pipe_common.h" -#include "amd/common/r600d_common.h" +#include "amd/common/sid.h" /** * Return true if there is enough memory in VRAM and GTT for the buffers @@ -115,10 +115,10 @@ radeon_add_to_buffer_list_check_mem(struct r600_common_context *rctx, static inline void radeon_set_config_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) { - assert(reg < R600_CONTEXT_REG_OFFSET); + assert(reg < SI_CONTEXT_REG_OFFSET); assert(cs->current.cdw + 2 + num <= cs->current.max_dw); radeon_emit(cs, PKT3(PKT3_SET_CONFIG_REG, num, 0)); - radeon_emit(cs, (reg - R600_CONFIG_REG_OFFSET) >> 2); + radeon_emit(cs, (reg - SI_CONFIG_REG_OFFSET) >> 2); } static inline void radeon_set_config_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) @@ -129,10 +129,10 @@ static inline void radeon_set_config_reg(struct radeon_winsys_cs *cs, unsigned r static inline void radeon_set_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) { - assert(reg >= R600_CONTEXT_REG_OFFSET); + assert(reg >= SI_CONTEXT_REG_OFFSET); assert(cs->current.cdw + 2 + num <= cs->current.max_dw); radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, num, 0)); - radeon_emit(cs, (reg - R600_CONTEXT_REG_OFFSET) >> 2); + radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2); } static inline void radeon_set_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) @@ -145,10 +145,10 @@ static inline void radeon_set_context_reg_idx(struct radeon_winsys_cs *cs, unsigned reg, unsigned idx, unsigned value) { - assert(reg >= R600_CONTEXT_REG_OFFSET); + assert(reg >= SI_CONTEXT_REG_OFFSET); assert(cs->current.cdw + 3 <= cs->current.max_dw); radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, 1, 0)); - radeon_emit(cs, (reg - R600_CONTEXT_REG_OFFSET) >> 2 | (idx << 28)); + radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2 | (idx << 28)); radeon_emit(cs, value); } diff --git a/src/gallium/drivers/radeon/r600_perfcounter.c b/src/gallium/drivers/radeon/r600_perfcounter.c index 13fd1e99e59..6c68dc4695d 100644 --- a/src/gallium/drivers/radeon/r600_perfcounter.c +++ b/src/gallium/drivers/radeon/r600_perfcounter.c @@ -28,7 +28,7 @@ #include "util/u_memory.h" #include "r600_query.h" #include "r600_pipe_common.h" -#include "amd/common/r600d_common.h" +#include "amd/common/sid.h" /* Max counters per HW block */ #define R600_QUERY_MAX_COUNTERS 16 diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c b/src/gallium/drivers/radeon/r600_pipe_common.c index f8a826fc07b..44ff5890356 100644 --- a/src/gallium/drivers/radeon/r600_pipe_common.c +++ b/src/gallium/drivers/radeon/r600_pipe_common.c @@ -36,6 +36,7 @@ #include "vl/vl_decoder.h" #include "vl/vl_video_buffer.h" #include "radeon/radeon_video.h" +#include "amd/common/sid.h" #include <inttypes.h> #include <sys/utsname.h> diff --git a/src/gallium/drivers/radeon/r600_query.c b/src/gallium/drivers/radeon/r600_query.c index e4dbb1d8690..b2809f84dfa 100644 --- a/src/gallium/drivers/radeon/r600_query.c +++ b/src/gallium/drivers/radeon/r600_query.c @@ -28,6 +28,7 @@ #include "util/u_upload_mgr.h" #include "os/os_time.h" #include "tgsi/tgsi_text.h" +#include "amd/common/sid.h" /* TODO: remove this: */ void si_update_prims_generated_query_state(struct r600_common_context *rctx, @@ -727,10 +728,10 @@ static unsigned event_type_for_stream(unsigned stream) { switch (stream) { default: - case 0: return EVENT_TYPE_SAMPLE_STREAMOUTSTATS; - case 1: return EVENT_TYPE_SAMPLE_STREAMOUTSTATS1; - case 2: return EVENT_TYPE_SAMPLE_STREAMOUTSTATS2; - case 3: return EVENT_TYPE_SAMPLE_STREAMOUTSTATS3; + case 0: return V_028A90_SAMPLE_STREAMOUTSTATS; + case 1: return V_028A90_SAMPLE_STREAMOUTSTATS1; + case 2: return V_028A90_SAMPLE_STREAMOUTSTATS2; + case 3: return V_028A90_SAMPLE_STREAMOUTSTATS3; } } @@ -755,7 +756,7 @@ static void r600_query_hw_do_emit_start(struct r600_common_context *ctx, case PIPE_QUERY_OCCLUSION_PREDICATE: case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE: radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0)); - radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1)); + radeon_emit(cs, EVENT_TYPE(V_028A90_ZPASS_DONE) | EVENT_INDEX(1)); radeon_emit(cs, va); radeon_emit(cs, va >> 32); break; @@ -784,7 +785,7 @@ static void r600_query_hw_do_emit_start(struct r600_common_context *ctx, break; case PIPE_QUERY_PIPELINE_STATISTICS: radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0)); - radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SAMPLE_PIPELINESTAT) | EVENT_INDEX(2)); + radeon_emit(cs, EVENT_TYPE(V_028A90_SAMPLE_PIPELINESTAT) | EVENT_INDEX(2)); radeon_emit(cs, va); radeon_emit(cs, va >> 32); break; @@ -842,7 +843,7 @@ static void r600_query_hw_do_emit_stop(struct r600_common_context *ctx, case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE: va += 8; radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0)); - radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1)); + radeon_emit(cs, EVENT_TYPE(V_028A90_ZPASS_DONE) | EVENT_INDEX(1)); radeon_emit(cs, va); radeon_emit(cs, va >> 32); @@ -864,7 +865,7 @@ static void r600_query_hw_do_emit_stop(struct r600_common_context *ctx, va += 8; /* fall through */ case PIPE_QUERY_TIMESTAMP: - si_gfx_write_event_eop(ctx, EVENT_TYPE_BOTTOM_OF_PIPE_TS, + si_gfx_write_event_eop(ctx, V_028A90_BOTTOM_OF_PIPE_TS, 0, EOP_DATA_SEL_TIMESTAMP, NULL, va, 0, query->b.type); fence_va = va + 8; @@ -874,7 +875,7 @@ static void r600_query_hw_do_emit_stop(struct r600_common_context *ctx, va += sample_size; radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0)); - radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SAMPLE_PIPELINESTAT) | EVENT_INDEX(2)); + radeon_emit(cs, EVENT_TYPE(V_028A90_SAMPLE_PIPELINESTAT) | EVENT_INDEX(2)); radeon_emit(cs, va); radeon_emit(cs, va >> 32); @@ -888,7 +889,7 @@ static void r600_query_hw_do_emit_stop(struct r600_common_context *ctx, RADEON_PRIO_QUERY); if (fence_va) - si_gfx_write_event_eop(ctx, EVENT_TYPE_BOTTOM_OF_PIPE_TS, 0, + si_gfx_write_event_eop(ctx, V_028A90_BOTTOM_OF_PIPE_TS, 0, EOP_DATA_SEL_VALUE_32BIT, query->buffer.buf, fence_va, 0x80000000, query->b.type); diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c index d9dc10bbb08..78d49c289d1 100644 --- a/src/gallium/drivers/radeon/r600_texture.c +++ b/src/gallium/drivers/radeon/r600_texture.c @@ -36,6 +36,7 @@ #include <errno.h> #include <inttypes.h> #include "state_tracker/drm_driver.h" +#include "amd/common/sid.h" static void r600_texture_discard_cmask(struct r600_common_screen *rscreen, struct r600_texture *rtex); @@ -408,7 +409,7 @@ static void r600_texture_discard_cmask(struct r600_common_screen *rscreen, rtex->cmask.base_address_reg = rtex->resource.gpu_address >> 8; rtex->dirty_level_mask = 0; - rtex->cb_color_info &= ~SI_S_028C70_FAST_CLEAR(1); + rtex->cb_color_info &= ~S_028C70_FAST_CLEAR(1); if (rtex->cmask_buffer != &rtex->resource) r600_resource_reference(&rtex->cmask_buffer, NULL); @@ -849,7 +850,7 @@ static void r600_texture_allocate_cmask(struct r600_common_screen *rscreen, rtex->cmask.offset = align64(rtex->size, rtex->cmask.alignment); rtex->size = rtex->cmask.offset + rtex->cmask.size; - rtex->cb_color_info |= SI_S_028C70_FAST_CLEAR(1); + rtex->cb_color_info |= S_028C70_FAST_CLEAR(1); } static void r600_texture_alloc_cmask_separate(struct r600_common_screen *rscreen, @@ -876,7 +877,7 @@ static void r600_texture_alloc_cmask_separate(struct r600_common_screen *rscreen /* update colorbuffer state bits */ rtex->cmask.base_address_reg = rtex->cmask_buffer->gpu_address >> 8; - rtex->cb_color_info |= SI_S_028C70_FAST_CLEAR(1); + rtex->cb_color_info |= S_028C70_FAST_CLEAR(1); p_atomic_inc(&rscreen->compressed_colortex_counter); } @@ -2062,7 +2063,7 @@ unsigned si_translate_colorswap(enum pipe_format format, bool do_endian_swap) #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == PIPE_SWIZZLE_##swz) if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */ - return V_0280A0_SWAP_STD; + return V_028C70_SWAP_STD; if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN) return ~0U; @@ -2070,45 +2071,45 @@ unsigned si_translate_colorswap(enum pipe_format format, bool do_endian_swap) switch (desc->nr_channels) { case 1: if (HAS_SWIZZLE(0,X)) - return V_0280A0_SWAP_STD; /* X___ */ + return V_028C70_SWAP_STD; /* X___ */ else if (HAS_SWIZZLE(3,X)) - return V_0280A0_SWAP_ALT_REV; /* ___X */ + return V_028C70_SWAP_ALT_REV; /* ___X */ break; case 2: if ((HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,Y)) || (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,NONE)) || (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,Y))) - return V_0280A0_SWAP_STD; /* XY__ */ + return V_028C70_SWAP_STD; /* XY__ */ else if ((HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,X)) || (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,NONE)) || (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,X))) /* YX__ */ - return (do_endian_swap ? V_0280A0_SWAP_STD : V_0280A0_SWAP_STD_REV); + return (do_endian_swap ? V_028C70_SWAP_STD : V_028C70_SWAP_STD_REV); else if (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(3,Y)) - return V_0280A0_SWAP_ALT; /* X__Y */ + return V_028C70_SWAP_ALT; /* X__Y */ else if (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(3,X)) - return V_0280A0_SWAP_ALT_REV; /* Y__X */ + return V_028C70_SWAP_ALT_REV; /* Y__X */ break; case 3: if (HAS_SWIZZLE(0,X)) - return (do_endian_swap ? V_0280A0_SWAP_STD_REV : V_0280A0_SWAP_STD); + return (do_endian_swap ? V_028C70_SWAP_STD_REV : V_028C70_SWAP_STD); else if (HAS_SWIZZLE(0,Z)) - return V_0280A0_SWAP_STD_REV; /* ZYX */ + return V_028C70_SWAP_STD_REV; /* ZYX */ break; case 4: /* check the middle channels, the 1st and 4th channel can be NONE */ if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,Z)) { - return V_0280A0_SWAP_STD; /* XYZW */ + return V_028C70_SWAP_STD; /* XYZW */ } else if (HAS_SWIZZLE(1,Z) && HAS_SWIZZLE(2,Y)) { - return V_0280A0_SWAP_STD_REV; /* WZYX */ + return V_028C70_SWAP_STD_REV; /* WZYX */ } else if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,X)) { - return V_0280A0_SWAP_ALT; /* ZYXW */ + return V_028C70_SWAP_ALT; /* ZYXW */ } else if (HAS_SWIZZLE(1,Z) && HAS_SWIZZLE(2,W)) { /* YZWX */ if (desc->is_array) - return V_0280A0_SWAP_ALT_REV; + return V_028C70_SWAP_ALT_REV; else - return (do_endian_swap ? V_0280A0_SWAP_ALT : V_0280A0_SWAP_ALT_REV); + return (do_endian_swap ? V_028C70_SWAP_ALT : V_028C70_SWAP_ALT_REV); } break; } diff --git a/src/gallium/drivers/radeonsi/si_perfcounter.c b/src/gallium/drivers/radeonsi/si_perfcounter.c index cb3377a9737..116e0b9d1aa 100644 --- a/src/gallium/drivers/radeonsi/si_perfcounter.c +++ b/src/gallium/drivers/radeonsi/si_perfcounter.c @@ -602,7 +602,7 @@ static void si_pc_emit_start(struct r600_common_context *ctx, radeon_set_uconfig_reg(cs, R_036020_CP_PERFMON_CNTL, S_036020_PERFMON_STATE(V_036020_DISABLE_AND_RESET)); radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); - radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_PERFCOUNTER_START) | EVENT_INDEX(0)); + radeon_emit(cs, EVENT_TYPE(V_028A90_PERFCOUNTER_START) | EVENT_INDEX(0)); radeon_set_uconfig_reg(cs, R_036020_CP_PERFMON_CNTL, S_036020_PERFMON_STATE(V_036020_START_COUNTING)); } @@ -614,15 +614,15 @@ static void si_pc_emit_stop(struct r600_common_context *ctx, { struct radeon_winsys_cs *cs = ctx->gfx.cs; - si_gfx_write_event_eop(ctx, EVENT_TYPE_BOTTOM_OF_PIPE_TS, 0, + si_gfx_write_event_eop(ctx, V_028A90_BOTTOM_OF_PIPE_TS, 0, EOP_DATA_SEL_VALUE_32BIT, buffer, va, 0, R600_NOT_QUERY); si_gfx_wait_fence(ctx, va, 0, 0xffffffff); radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); - radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_PERFCOUNTER_SAMPLE) | EVENT_INDEX(0)); + radeon_emit(cs, EVENT_TYPE(V_028A90_PERFCOUNTER_SAMPLE) | EVENT_INDEX(0)); radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); - radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_PERFCOUNTER_STOP) | EVENT_INDEX(0)); + radeon_emit(cs, EVENT_TYPE(V_028A90_PERFCOUNTER_STOP) | EVENT_INDEX(0)); radeon_set_uconfig_reg(cs, R_036020_CP_PERFMON_CNTL, S_036020_PERFMON_STATE(V_036020_STOP_COUNTING) | S_036020_PERFMON_SAMPLE_ENABLE(1)); diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index 3c6b7ca3f5f..4bfd5272db0 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -209,10 +209,10 @@ static void si_emit_cb_render_state(struct si_context *sctx, struct r600_atom *a break; case V_028C70_COLOR_32: - if (swap == V_0280A0_SWAP_STD && + if (swap == V_028C70_SWAP_STD && spi_format == V_028714_SPI_SHADER_32_R) sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4); - else if (swap == V_0280A0_SWAP_ALT_REV && + else if (swap == V_028C70_SWAP_ALT_REV && spi_format == V_028714_SPI_SHADER_32_AR) sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4); break; @@ -224,8 +224,8 @@ static void si_emit_cb_render_state(struct si_context *sctx, struct r600_atom *a spi_format == V_028714_SPI_SHADER_SNORM16_ABGR || spi_format == V_028714_SPI_SHADER_UINT16_ABGR || spi_format == V_028714_SPI_SHADER_SINT16_ABGR) { - if (swap == V_0280A0_SWAP_STD || - swap == V_0280A0_SWAP_STD_REV) + if (swap == V_028C70_SWAP_STD || + swap == V_028C70_SWAP_STD_REV) sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4); else sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4); @@ -3328,7 +3328,7 @@ static void si_emit_msaa_config(struct si_context *sctx, struct r600_atom *atom) unsigned log_ps_iter_samples = util_logbase2(util_next_power_of_two(sctx->ps_iter_samples)); - radeon_set_context_reg_seq(cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2); + radeon_set_context_reg_seq(cs, R_028BDC_PA_SC_LINE_CNTL, 2); radeon_emit(cs, sc_line_cntl | S_028BDC_EXPAND_LINE_WIDTH(1)); /* CM_R_028BDC_PA_SC_LINE_CNTL */ radeon_emit(cs, S_028BE0_MSAA_NUM_SAMPLES(log_samples) | @@ -3336,33 +3336,33 @@ static void si_emit_msaa_config(struct si_context *sctx, struct r600_atom *atom) S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples)); /* CM_R_028BE0_PA_SC_AA_CONFIG */ if (sctx->framebuffer.nr_samples > 1) { - radeon_set_context_reg(cs, CM_R_028804_DB_EQAA, + radeon_set_context_reg(cs, R_028804_DB_EQAA, S_028804_MAX_ANCHOR_SAMPLES(log_samples) | S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) | S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) | S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples) | S_028804_HIGH_QUALITY_INTERSECTIONS(1) | S_028804_STATIC_ANCHOR_ASSOCIATIONS(1)); - radeon_set_context_reg(cs, EG_R_028A4C_PA_SC_MODE_CNTL_1, - EG_S_028A4C_PS_ITER_SAMPLE(sctx->ps_iter_samples > 1) | + radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1, + S_028A4C_PS_ITER_SAMPLE(sctx->ps_iter_samples > 1) | sc_mode_cntl_1); } else if (sctx->smoothing_enabled) { - radeon_set_context_reg(cs, CM_R_028804_DB_EQAA, + radeon_set_context_reg(cs, R_028804_DB_EQAA, S_028804_HIGH_QUALITY_INTERSECTIONS(1) | S_028804_STATIC_ANCHOR_ASSOCIATIONS(1) | S_028804_OVERRASTERIZATION_AMOUNT(log_samples)); - radeon_set_context_reg(cs, EG_R_028A4C_PA_SC_MODE_CNTL_1, + radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1, sc_mode_cntl_1); } } else { - radeon_set_context_reg_seq(cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2); + radeon_set_context_reg_seq(cs, R_028BDC_PA_SC_LINE_CNTL, 2); radeon_emit(cs, sc_line_cntl); /* CM_R_028BDC_PA_SC_LINE_CNTL */ radeon_emit(cs, 0); /* CM_R_028BE0_PA_SC_AA_CONFIG */ - radeon_set_context_reg(cs, CM_R_028804_DB_EQAA, + radeon_set_context_reg(cs, R_028804_DB_EQAA, S_028804_HIGH_QUALITY_INTERSECTIONS(1) | S_028804_STATIC_ANCHOR_ASSOCIATIONS(1)); - radeon_set_context_reg(cs, EG_R_028A4C_PA_SC_MODE_CNTL_1, + radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1, sc_mode_cntl_1); } diff --git a/src/gallium/drivers/radeonsi/si_state_msaa.c b/src/gallium/drivers/radeonsi/si_state_msaa.c index 977f54b9078..133f1e4aac5 100644 --- a/src/gallium/drivers/radeonsi/si_state_msaa.c +++ b/src/gallium/drivers/radeonsi/si_state_msaa.c @@ -134,25 +134,25 @@ void si_emit_sample_locations(struct radeon_winsys_cs *cs, int nr_samples) switch (nr_samples) { default: case 1: - radeon_set_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 0); - radeon_set_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, 0); - radeon_set_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, 0); - radeon_set_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, 0); + radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 0); + radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, 0); + radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, 0); + radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, 0); break; case 2: - radeon_set_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_2x[0]); - radeon_set_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_2x[1]); - radeon_set_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_2x[2]); - radeon_set_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_2x[3]); + radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_2x[0]); + radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_2x[1]); + radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_2x[2]); + radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_2x[3]); break; case 4: - radeon_set_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_4x[0]); - radeon_set_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_4x[1]); - radeon_set_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_4x[2]); - radeon_set_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_4x[3]); + radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_4x[0]); + radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_4x[1]); + radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_4x[2]); + radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_4x[3]); break; case 8: - radeon_set_context_reg_seq(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 14); + radeon_set_context_reg_seq(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 14); radeon_emit(cs, sample_locs_8x[0]); radeon_emit(cs, sample_locs_8x[4]); radeon_emit(cs, 0); @@ -169,7 +169,7 @@ void si_emit_sample_locations(struct radeon_winsys_cs *cs, int nr_samples) radeon_emit(cs, sample_locs_8x[7]); break; case 16: - radeon_set_context_reg_seq(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 16); + radeon_set_context_reg_seq(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 16); radeon_emit(cs, sample_locs_16x[0]); radeon_emit(cs, sample_locs_16x[4]); radeon_emit(cs, sample_locs_16x[8]); diff --git a/src/gallium/drivers/radeonsi/si_state_streamout.c b/src/gallium/drivers/radeonsi/si_state_streamout.c index f4fcf70e342..9971bc815ec 100644 --- a/src/gallium/drivers/radeonsi/si_state_streamout.c +++ b/src/gallium/drivers/radeonsi/si_state_streamout.c @@ -253,8 +253,8 @@ static void si_flush_vgt_streamout(struct si_context *sctx) radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */ radeon_emit(cs, reg_strmout_cntl >> 2); /* register */ radeon_emit(cs, 0); - radeon_emit(cs, S_008490_OFFSET_UPDATE_DONE(1)); /* reference value */ - radeon_emit(cs, S_008490_OFFSET_UPDATE_DONE(1)); /* mask */ + radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */ + radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */ radeon_emit(cs, 4); /* poll interval */ } |