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-rw-r--r--src/compiler/shader_info.h1
-rw-r--r--src/compiler/spirv/spirv_to_nir.c9
2 files changed, 10 insertions, 0 deletions
diff --git a/src/compiler/shader_info.h b/src/compiler/shader_info.h
index 3b95d5962c0..e9ca222dea8 100644
--- a/src/compiler/shader_info.h
+++ b/src/compiler/shader_info.h
@@ -59,6 +59,7 @@ struct spirv_supported_capabilities {
bool stencil_export;
bool atomic_storage;
bool storage_8bit;
+ bool post_depth_coverage;
};
typedef struct shader_info {
diff --git a/src/compiler/spirv/spirv_to_nir.c b/src/compiler/spirv/spirv_to_nir.c
index bbef3fcf4df..79104695f5f 100644
--- a/src/compiler/spirv/spirv_to_nir.c
+++ b/src/compiler/spirv/spirv_to_nir.c
@@ -3542,6 +3542,10 @@ vtn_handle_preamble_instruction(struct vtn_builder *b, SpvOp opcode,
spv_check_supported(stencil_export, cap);
break;
+ case SpvCapabilitySampleMaskPostDepthCoverage:
+ spv_check_supported(post_depth_coverage, cap);
+ break;
+
default:
vtn_fail("Unhandled capability");
}
@@ -3609,6 +3613,11 @@ vtn_handle_execution_mode(struct vtn_builder *b, struct vtn_value *entry_point,
b->shader->info.fs.early_fragment_tests = true;
break;
+ case SpvExecutionModePostDepthCoverage:
+ vtn_assert(b->shader->info.stage == MESA_SHADER_FRAGMENT);
+ b->shader->info.fs.post_depth_coverage = true;
+ break;
+
case SpvExecutionModeInvocations:
vtn_assert(b->shader->info.stage == MESA_SHADER_GEOMETRY);
b->shader->info.gs.invocations = MAX2(1, mode->literals[0]);