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-rw-r--r--src/mesa/drivers/dri/i965/brw_vtbl.c12
-rw-r--r--src/mesa/drivers/dri/intel/intel_mipmap_tree.c6
2 files changed, 14 insertions, 4 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_vtbl.c b/src/mesa/drivers/dri/i965/brw_vtbl.c
index dd2e05a3669..c0a0b52434d 100644
--- a/src/mesa/drivers/dri/i965/brw_vtbl.c
+++ b/src/mesa/drivers/dri/i965/brw_vtbl.c
@@ -214,8 +214,16 @@ static void brw_invalidate_state( struct intel_context *intel, GLuint new_state
static bool brw_is_hiz_depth_format(struct intel_context *intel,
gl_format format)
{
- /* In the future, this will support Z_FLOAT32. */
- return intel->has_hiz && (format == MESA_FORMAT_X8_Z24);
+ if (!intel->has_hiz)
+ return false;
+
+ switch (format) {
+ case MESA_FORMAT_X8_Z24:
+ case MESA_FORMAT_S8_Z24:
+ return true;
+ default:
+ return false;
+ }
}
void brwInitVtbl( struct brw_context *brw )
diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
index f8ef2625df3..3e4baa1bfb5 100644
--- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
@@ -119,8 +119,10 @@ intel_miptree_create_internal(struct intel_context *intel,
brw_miptree_layout(intel, mt);
#endif
- if (intel->has_separate_stencil &&
- _mesa_is_depthstencil_format(_mesa_get_format_base_format(format))) {
+ if (_mesa_is_depthstencil_format(_mesa_get_format_base_format(format)) &&
+ (intel->must_use_separate_stencil ||
+ (intel->has_separate_stencil &&
+ intel->vtbl.is_hiz_depth_format(intel, format)))) {
mt->stencil_mt = intel_miptree_create(intel,
mt->target,
MESA_FORMAT_S8,