diff options
| -rw-r--r-- | src/panfrost/midgard/helpers.h | 1 | ||||
| -rw-r--r-- | src/panfrost/midgard/midgard_compile.c | 25 | ||||
| -rw-r--r-- | src/panfrost/midgard/midgard_emit.c | 3 | ||||
| -rw-r--r-- | src/panfrost/midgard/midgard_opt_dce.c | 4 | ||||
| -rw-r--r-- | src/panfrost/midgard/midgard_ra.c | 3 | ||||
| -rw-r--r-- | src/panfrost/midgard/midgard_schedule.c | 3 |
6 files changed, 37 insertions, 2 deletions
diff --git a/src/panfrost/midgard/helpers.h b/src/panfrost/midgard/helpers.h index 6d1031841a5..9854cf72759 100644 --- a/src/panfrost/midgard/helpers.h +++ b/src/panfrost/midgard/helpers.h @@ -131,6 +131,7 @@ #define TAG_TEXTURE_4_VTX 0x2 #define TAG_TEXTURE_4 0x3 +#define TAG_TEXTURE_4_BARRIER 0x4 #define TAG_LOAD_STORE_4 0x5 #define TAG_ALU_4 0x8 #define TAG_ALU_8 0x9 diff --git a/src/panfrost/midgard/midgard_compile.c b/src/panfrost/midgard/midgard_compile.c index dca502bd425..4bc494ca1be 100644 --- a/src/panfrost/midgard/midgard_compile.c +++ b/src/panfrost/midgard/midgard_compile.c @@ -1505,6 +1505,21 @@ emit_vertex_builtin(compiler_context *ctx, nir_intrinsic_instr *instr) emit_attr_read(ctx, reg, vertex_builtin_arg(instr->intrinsic), 1, nir_type_int); } +static void +emit_control_barrier(compiler_context *ctx) +{ + midgard_instruction ins = { + .type = TAG_TEXTURE_4, + .src = { ~0, ~0, ~0, ~0 }, + .texture = { + .op = TEXTURE_OP_BARRIER, + .unknown4 = 3 /* (control |) buffers | shared */ + } + }; + + emit_mir_instruction(ctx, ins); +} + static const nir_variable * search_var(struct exec_list *vars, unsigned driver_loc) { @@ -1814,6 +1829,16 @@ emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr) emit_vertex_builtin(ctx, instr); break; + case nir_intrinsic_memory_barrier_buffer: + case nir_intrinsic_memory_barrier_shared: + break; + + case nir_intrinsic_control_barrier: + schedule_barrier(ctx); + emit_control_barrier(ctx); + schedule_barrier(ctx); + break; + default: printf ("Unhandled intrinsic %s\n", nir_intrinsic_infos[instr->intrinsic].name); assert(0); diff --git a/src/panfrost/midgard/midgard_emit.c b/src/panfrost/midgard/midgard_emit.c index 7e948fd19c5..1db5980e374 100644 --- a/src/panfrost/midgard/midgard_emit.c +++ b/src/panfrost/midgard/midgard_emit.c @@ -450,7 +450,8 @@ emit_binary_bundle(compiler_context *ctx, } case TAG_TEXTURE_4: - case TAG_TEXTURE_4_VTX: { + case TAG_TEXTURE_4_VTX: + case TAG_TEXTURE_4_BARRIER: { /* Texture instructions are easy, since there is no pipelining * nor VLIW to worry about. We may need to set .cont/.last * flags. */ diff --git a/src/panfrost/midgard/midgard_opt_dce.c b/src/panfrost/midgard/midgard_opt_dce.c index 0b2823be782..f55db21cef2 100644 --- a/src/panfrost/midgard/midgard_opt_dce.c +++ b/src/panfrost/midgard/midgard_opt_dce.c @@ -56,6 +56,10 @@ can_dce(midgard_instruction *ins) if (load_store_opcode_props[ins->load_store.op].props & LDST_SIDE_FX) return false; + if (ins->type == TAG_TEXTURE_4) + if (ins->texture.op == TEXTURE_OP_BARRIER) + return false; + return true; } diff --git a/src/panfrost/midgard/midgard_ra.c b/src/panfrost/midgard/midgard_ra.c index eec4876eefe..09354f3eb53 100644 --- a/src/panfrost/midgard/midgard_ra.c +++ b/src/panfrost/midgard/midgard_ra.c @@ -686,6 +686,9 @@ install_registers_instr( } case TAG_TEXTURE_4: { + if (ins->texture.op == TEXTURE_OP_BARRIER) + break; + /* Grab RA results */ struct phys_reg dest = index_to_reg(ctx, l, ins->dest, mir_typesize(ins)); struct phys_reg coord = index_to_reg(ctx, l, ins->src[1], mir_srcsize(ins, 1)); diff --git a/src/panfrost/midgard/midgard_schedule.c b/src/panfrost/midgard/midgard_schedule.c index 2f12640f7ac..c6055a71140 100644 --- a/src/panfrost/midgard/midgard_schedule.c +++ b/src/panfrost/midgard/midgard_schedule.c @@ -811,7 +811,8 @@ mir_schedule_texture( mir_update_worklist(worklist, len, instructions, ins); struct midgard_bundle out = { - .tag = TAG_TEXTURE_4, + .tag = ins->texture.op == TEXTURE_OP_BARRIER ? + TAG_TEXTURE_4_BARRIER : TAG_TEXTURE_4, .instruction_count = 1, .instructions = { ins } }; |