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-rw-r--r--src/mesa/drivers/dri/i965/brw_fs.cpp17
-rw-r--r--src/mesa/drivers/dri/i965/brw_fs.h2
-rw-r--r--src/mesa/drivers/dri/i965/brw_fs_fp.cpp3
-rw-r--r--src/mesa/drivers/dri/i965/brw_fs_visitor.cpp18
-rw-r--r--src/mesa/drivers/dri/i965/brw_wm_iz.cpp5
5 files changed, 36 insertions, 9 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
index e840d292974..66705a1d7be 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -1009,6 +1009,8 @@ fs_visitor::setup_builtin_uniform_values(ir_variable *ir)
fs_reg *
fs_visitor::emit_fragcoord_interpolation(ir_variable *ir)
{
+ assert(stage == MESA_SHADER_FRAGMENT);
+ brw_wm_prog_key *key = (brw_wm_prog_key*) this->key;
fs_reg *reg = new(this->mem_ctx) fs_reg(this, ir->type);
fs_reg wpos = *reg;
bool flip = !ir->data.origin_upper_left ^ key->render_to_fbo;
@@ -1098,6 +1100,7 @@ fs_visitor::emit_general_interpolation(ir_variable *ir)
assert(stage == MESA_SHADER_FRAGMENT);
brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
+ brw_wm_prog_key *key = (brw_wm_prog_key*) this->key;
unsigned int array_elements;
const glsl_type *type;
@@ -1234,6 +1237,8 @@ fs_visitor::emit_frontfacing_interpolation()
void
fs_visitor::compute_sample_position(fs_reg dst, fs_reg int_sample_pos)
{
+ assert(stage == MESA_SHADER_FRAGMENT);
+ brw_wm_prog_key *key = (brw_wm_prog_key*) this->key;
assert(dst.type == BRW_REGISTER_TYPE_F);
if (key->compute_pos_offset) {
@@ -1303,6 +1308,8 @@ fs_visitor::emit_samplepos_setup()
fs_reg *
fs_visitor::emit_sampleid_setup(ir_variable *ir)
{
+ assert(stage == MESA_SHADER_FRAGMENT);
+ brw_wm_prog_key *key = (brw_wm_prog_key*) this->key;
assert(brw->gen >= 6);
this->current_annotation = "compute sample id";
@@ -1505,6 +1512,7 @@ fs_visitor::calculate_urb_setup()
{
assert(stage == MESA_SHADER_FRAGMENT);
brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
+ brw_wm_prog_key *key = (brw_wm_prog_key*) this->key;
for (unsigned int i = 0; i < VARYING_SLOT_MAX; i++) {
prog_data->urb_setup[i] = -1;
@@ -3104,6 +3112,7 @@ fs_visitor::setup_payload_gen6()
if (stage == MESA_SHADER_FRAGMENT) {
brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
+ brw_wm_prog_key *key = (brw_wm_prog_key*) this->key;
prog_data->uses_pos_offset = key->compute_pos_offset;
/* R31: MSAA position offsets. */
if (prog_data->uses_pos_offset) {
@@ -3136,6 +3145,7 @@ fs_visitor::assign_binding_table_offsets()
{
assert(stage == MESA_SHADER_FRAGMENT);
brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
+ brw_wm_prog_key *key = (brw_wm_prog_key*) this->key;
uint32_t next_binding_table_offset = 0;
/* If there are no color regions, we still perform an FB write to a null
@@ -3225,7 +3235,10 @@ fs_visitor::run()
bool uses_kill =
(stage == MESA_SHADER_FRAGMENT) &&
((brw_wm_prog_data*) this->prog_data)->uses_kill;
- if (uses_kill || key->alpha_test_func) {
+ bool alpha_test_func =
+ (stage == MESA_SHADER_FRAGMENT) &&
+ ((brw_wm_prog_key*) this->key)->alpha_test_func;
+ if (uses_kill || alpha_test_func) {
fs_inst *discard_init = emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS);
discard_init->flag_subreg = 1;
}
@@ -3248,7 +3261,7 @@ fs_visitor::run()
emit(FS_OPCODE_PLACEHOLDER_HALT);
- if (key->alpha_test_func)
+ if (alpha_test_func)
emit_alpha_test();
emit_fb_writes();
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h b/src/mesa/drivers/dri/i965/brw_fs.h
index 7f43594407d..d76ea2d4871 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -469,7 +469,7 @@ public:
void visit_atomic_counter_intrinsic(ir_call *ir);
- const struct brw_wm_prog_key *const key;
+ const void *const key;
struct brw_stage_prog_data *prog_data;
unsigned int sanity_param_count;
diff --git a/src/mesa/drivers/dri/i965/brw_fs_fp.cpp b/src/mesa/drivers/dri/i965/brw_fs_fp.cpp
index 526c8171ff0..63bd55ec8e7 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_fp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_fp.cpp
@@ -633,6 +633,9 @@ fs_visitor::setup_fp_regs()
fs_reg
fs_visitor::get_fp_dst_reg(const prog_dst_register *dst)
{
+ assert(stage == MESA_SHADER_FRAGMENT);
+ brw_wm_prog_key *key = (brw_wm_prog_key*) this->key;
+
switch (dst->File) {
case PROGRAM_TEMPORARY:
return fp_temp_regs[dst->Index];
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index bd579f11d78..6dcf67b8480 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
@@ -77,6 +77,8 @@ fs_visitor::visit(ir_variable *ir)
this->do_dual_src = true;
} else if (ir->data.location == FRAG_RESULT_COLOR) {
/* Writing gl_FragColor outputs to all color regions. */
+ assert(stage == MESA_SHADER_FRAGMENT);
+ brw_wm_prog_key *key = (brw_wm_prog_key*) this->key;
for (unsigned int i = 0; i < MAX2(key->nr_color_regions, 1); i++) {
this->outputs[i] = *reg;
this->output_components[i] = 4;
@@ -355,6 +357,9 @@ fs_visitor::emit_interpolate_expression(ir_expression *ir)
*/
no16("interpolate_at_* not yet supported in SIMD16 mode.");
+ assert(stage == MESA_SHADER_FRAGMENT);
+ brw_wm_prog_key *key = (brw_wm_prog_key*) this->key;
+
ir_dereference * deref = ir->operands[0]->as_dereference();
ir_swizzle * swiz = NULL;
if (!deref) {
@@ -1666,7 +1671,7 @@ fs_visitor::rescale_texcoord(ir_texture *ir, fs_reg coordinate,
fs_reg scale_x, scale_y;
const struct brw_sampler_prog_key_data *tex =
(stage == MESA_SHADER_FRAGMENT) ?
- &this->key->tex : NULL;
+ &((brw_wm_prog_key*) this->key)->tex : NULL;
assert(tex);
/* The 965 requires the EU to do the normalization of GL rectangle
@@ -1811,7 +1816,7 @@ fs_visitor::visit(ir_texture *ir)
{
const struct brw_sampler_prog_key_data *tex =
(stage == MESA_SHADER_FRAGMENT) ?
- &this->key->tex : NULL;
+ &((brw_wm_prog_key*) this->key)->tex : NULL;
assert(tex);
fs_inst *inst = NULL;
@@ -2035,7 +2040,7 @@ fs_visitor::gather_channel(ir_texture *ir, uint32_t sampler)
{
const struct brw_sampler_prog_key_data *tex =
(stage == MESA_SHADER_FRAGMENT) ?
- &this->key->tex : NULL;
+ &((brw_wm_prog_key*) this->key)->tex : NULL;
assert(tex);
ir_constant *chan = ir->lod_info.component->as_constant();
int swiz = GET_SWZ(tex->swizzles[sampler], chan->value.i[0]);
@@ -2079,7 +2084,7 @@ fs_visitor::swizzle_result(ir_texture *ir, fs_reg orig_val, uint32_t sampler)
const struct brw_sampler_prog_key_data *tex =
(stage == MESA_SHADER_FRAGMENT) ?
- &this->key->tex : NULL;
+ &((brw_wm_prog_key*) this->key)->tex : NULL;
assert(tex);
if (ir->type == glsl_type::float_type) {
@@ -2955,6 +2960,8 @@ fs_visitor::emit_interpolation_setup_gen6()
void
fs_visitor::emit_color_write(int target, int index, int first_color_mrf)
{
+ assert(stage == MESA_SHADER_FRAGMENT);
+ brw_wm_prog_key *key = (brw_wm_prog_key*) this->key;
int reg_width = dispatch_width / 8;
fs_inst *inst;
fs_reg color = outputs[target];
@@ -3051,6 +3058,8 @@ cond_for_alpha_func(GLenum func)
void
fs_visitor::emit_alpha_test()
{
+ assert(stage == MESA_SHADER_FRAGMENT);
+ brw_wm_prog_key *key = (brw_wm_prog_key*) this->key;
this->current_annotation = "Alpha test";
fs_inst *cmp;
@@ -3081,6 +3090,7 @@ fs_visitor::emit_fb_writes()
{
assert(stage == MESA_SHADER_FRAGMENT);
brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
+ brw_wm_prog_key *key = (brw_wm_prog_key*) this->key;
this->current_annotation = "FB write header";
bool header_present = true;
diff --git a/src/mesa/drivers/dri/i965/brw_wm_iz.cpp b/src/mesa/drivers/dri/i965/brw_wm_iz.cpp
index 47823a764de..14930eb0184 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_iz.cpp
+++ b/src/mesa/drivers/dri/i965/brw_wm_iz.cpp
@@ -122,11 +122,12 @@ static const struct {
*/
void fs_visitor::setup_payload_gen4()
{
+ assert(stage == MESA_SHADER_FRAGMENT);
+ brw_wm_prog_key *key = (brw_wm_prog_key*) this->key;
+ gl_fragment_program *fp = (gl_fragment_program*) prog;
GLuint reg = 2;
bool kill_stats_promoted_workaround = false;
int lookup = key->iz_lookup;
- assert(stage == MESA_SHADER_FRAGMENT);
- gl_fragment_program *fp = (gl_fragment_program*) prog;
bool uses_depth =
(fp->Base.InputsRead & (1 << VARYING_SLOT_POS)) != 0;
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-11 15:55:05 +0000