diff options
| -rw-r--r-- | src/amd/vulkan/radv_cmd_buffer.c | 117 |
1 files changed, 77 insertions, 40 deletions
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 4e133d1f255..b0e6f139e73 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -920,6 +920,73 @@ radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer) } static void +radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer) +{ + unsigned width = cmd_buffer->state.dynamic.line_width * 8; + + radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL, + S_028A08_WIDTH(CLAMP(width, 0, 0xFFF))); +} + +static void +radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer) +{ + struct radv_dynamic_state *d = &cmd_buffer->state.dynamic; + + radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4); + radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4); +} + +static void +radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer) +{ + struct radv_dynamic_state *d = &cmd_buffer->state.dynamic; + + radeon_set_context_reg_seq(cmd_buffer->cs, + R_028430_DB_STENCILREFMASK, 2); + radeon_emit(cmd_buffer->cs, + S_028430_STENCILTESTVAL(d->stencil_reference.front) | + S_028430_STENCILMASK(d->stencil_compare_mask.front) | + S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) | + S_028430_STENCILOPVAL(1)); + radeon_emit(cmd_buffer->cs, + S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) | + S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) | + S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) | + S_028434_STENCILOPVAL_BF(1)); +} + +static void +radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer) +{ + struct radv_dynamic_state *d = &cmd_buffer->state.dynamic; + + radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN, + fui(d->depth_bounds.min)); + radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX, + fui(d->depth_bounds.max)); +} + +static void +radv_emit_depth_biais(struct radv_cmd_buffer *cmd_buffer) +{ + struct radv_raster_state *raster = &cmd_buffer->state.pipeline->graphics.raster; + struct radv_dynamic_state *d = &cmd_buffer->state.dynamic; + unsigned slope = fui(d->depth_bias.slope * 16.0f); + unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale); + + if (G_028814_POLY_OFFSET_FRONT_ENABLE(raster->pa_su_sc_mode_cntl)) { + radeon_set_context_reg_seq(cmd_buffer->cs, + R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5); + radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */ + radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */ + radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */ + radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */ + radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */ + } +} + +static void radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer, int index, struct radv_color_buffer_info *cb) @@ -1276,8 +1343,6 @@ void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer) static void radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer) { - struct radv_dynamic_state *d = &cmd_buffer->state.dynamic; - if (G_028810_DX_RASTERIZATION_KILL(cmd_buffer->state.pipeline->graphics.raster.pa_cl_clip_cntl)) return; @@ -1287,52 +1352,24 @@ radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer) if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT)) radv_emit_scissor(cmd_buffer); - if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH) { - unsigned width = cmd_buffer->state.dynamic.line_width * 8; - radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL, - S_028A08_WIDTH(CLAMP(width, 0, 0xFFF))); - } + if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH) + radv_emit_line_width(cmd_buffer); - if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS) { - radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4); - radeon_emit_array(cmd_buffer->cs, (uint32_t*)d->blend_constants, 4); - } + if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS) + radv_emit_blend_constants(cmd_buffer); if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE | RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK | - RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK)) { - radeon_set_context_reg_seq(cmd_buffer->cs, R_028430_DB_STENCILREFMASK, 2); - radeon_emit(cmd_buffer->cs, S_028430_STENCILTESTVAL(d->stencil_reference.front) | - S_028430_STENCILMASK(d->stencil_compare_mask.front) | - S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) | - S_028430_STENCILOPVAL(1)); - radeon_emit(cmd_buffer->cs, S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) | - S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) | - S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) | - S_028434_STENCILOPVAL_BF(1)); - } + RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK)) + radv_emit_stencil(cmd_buffer); if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE | - RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)) { - radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN, fui(d->depth_bounds.min)); - radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX, fui(d->depth_bounds.max)); - } + RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)) + radv_emit_depth_bounds(cmd_buffer); if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE | - RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)) { - struct radv_raster_state *raster = &cmd_buffer->state.pipeline->graphics.raster; - unsigned slope = fui(d->depth_bias.slope * 16.0f); - unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale); - - if (G_028814_POLY_OFFSET_FRONT_ENABLE(raster->pa_su_sc_mode_cntl)) { - radeon_set_context_reg_seq(cmd_buffer->cs, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5); - radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */ - radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */ - radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */ - radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */ - radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */ - } - } + RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)) + radv_emit_depth_biais(cmd_buffer); cmd_buffer->state.dirty = 0; } |