diff options
| -rw-r--r-- | src/intel/blorp/blorp_clear.c | 4 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_clear.c | 3 |
2 files changed, 5 insertions, 2 deletions
diff --git a/src/intel/blorp/blorp_clear.c b/src/intel/blorp/blorp_clear.c index fea5eb7b442..3d5c41cc714 100644 --- a/src/intel/blorp/blorp_clear.c +++ b/src/intel/blorp/blorp_clear.c @@ -399,6 +399,10 @@ blorp_clear(struct blorp_batch *batch, if (surf->surf->tiling == ISL_TILING_LINEAR) use_simd16_replicated_data = false; + /* Replicated clears don't work yet before gen6 */ + if (batch->blorp->isl_dev->info->gen < 6) + use_simd16_replicated_data = false; + /* Constant color writes ignore everyting in blend and color calculator * state. This is not documented. */ diff --git a/src/mesa/drivers/dri/i965/brw_clear.c b/src/mesa/drivers/dri/i965/brw_clear.c index ba9aa4b654b..664342d452f 100644 --- a/src/mesa/drivers/dri/i965/brw_clear.c +++ b/src/mesa/drivers/dri/i965/brw_clear.c @@ -285,8 +285,7 @@ brw_clear(struct gl_context *ctx, GLbitfield mask) mt->stencil_mt->r8stencil_needs_update = true; } - /* BLORP is currently only supported on Gen6+. */ - if (brw->gen >= 6 && (mask & BUFFER_BITS_COLOR)) { + if (mask & BUFFER_BITS_COLOR) { const bool encode_srgb = ctx->Color.sRGBEnabled; if (brw_blorp_clear_color(brw, fb, mask, partial_clear, encode_srgb)) { debug_mask("blorp color", mask & BUFFER_BITS_COLOR); |