diff options
| -rw-r--r-- | src/intel/compiler/brw_fs.cpp | 6 | ||||
| -rw-r--r-- | src/intel/compiler/brw_ir_fs.h | 33 | ||||
| -rw-r--r-- | src/intel/compiler/brw_reg.h | 30 |
3 files changed, 64 insertions, 5 deletions
diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index 9dc21ac5e38..3fc7ae48943 100644 --- a/src/intel/compiler/brw_fs.cpp +++ b/src/intel/compiler/brw_fs.cpp @@ -4585,11 +4585,7 @@ get_fpu_lowered_simd_width(const struct gen_device_info *devinfo, !inst->force_writemask_all) { const unsigned channels_per_grf = inst->exec_size / DIV_ROUND_UP(inst->size_written, REG_SIZE); - unsigned exec_type_size = 0; - for (int i = 0; i < inst->sources; i++) { - if (inst->src[i].file != BAD_FILE) - exec_type_size = MAX2(exec_type_size, type_sz(inst->src[i].type)); - } + const unsigned exec_type_size = get_exec_type_size(inst); assert(exec_type_size); /* The hardware shifts exactly 8 channels per compressed half of the diff --git a/src/intel/compiler/brw_ir_fs.h b/src/intel/compiler/brw_ir_fs.h index cad371248c4..58beae0d1f0 100644 --- a/src/intel/compiler/brw_ir_fs.h +++ b/src/intel/compiler/brw_ir_fs.h @@ -448,4 +448,37 @@ regs_read(const fs_inst *inst, unsigned i) reg_size); } +static inline enum brw_reg_type +get_exec_type(const fs_inst *inst) +{ + brw_reg_type exec_type = BRW_REGISTER_TYPE_B; + + for (int i = 0; i < inst->sources; i++) { + if (inst->src[i].file != BAD_FILE) { + const brw_reg_type t = get_exec_type(inst->src[i].type); + if (type_sz(t) > type_sz(exec_type)) + exec_type = t; + else if (type_sz(t) == type_sz(exec_type) && + brw_reg_type_is_floating_point(t)) + exec_type = t; + } + } + + if (exec_type == BRW_REGISTER_TYPE_B) + exec_type = inst->dst.type; + + /* TODO: We need to handle half-float conversions. */ + assert(exec_type != BRW_REGISTER_TYPE_HF || + inst->dst.type == BRW_REGISTER_TYPE_HF); + assert(exec_type != BRW_REGISTER_TYPE_B); + + return exec_type; +} + +static inline unsigned +get_exec_type_size(const fs_inst *inst) +{ + return type_sz(get_exec_type(inst)); +} + #endif diff --git a/src/intel/compiler/brw_reg.h b/src/intel/compiler/brw_reg.h index f8c3340e452..17a51fbd655 100644 --- a/src/intel/compiler/brw_reg.h +++ b/src/intel/compiler/brw_reg.h @@ -325,6 +325,36 @@ type_sz(unsigned type) } } +static inline bool +brw_reg_type_is_floating_point(enum brw_reg_type type) +{ + switch (type) { + case BRW_REGISTER_TYPE_F: + case BRW_REGISTER_TYPE_HF: + case BRW_REGISTER_TYPE_DF: + return true; + default: + return false; + } +} + +static inline enum brw_reg_type +get_exec_type(const enum brw_reg_type type) +{ + switch (type) { + case BRW_REGISTER_TYPE_B: + case BRW_REGISTER_TYPE_V: + return BRW_REGISTER_TYPE_W; + case BRW_REGISTER_TYPE_UB: + case BRW_REGISTER_TYPE_UV: + return BRW_REGISTER_TYPE_UW; + case BRW_REGISTER_TYPE_VF: + return BRW_REGISTER_TYPE_F; + default: + return type; + } +} + /** * Return an integer type of the requested size and signedness. */ |