diff options
| -rw-r--r-- | src/intel/blorp/blorp.c | 6 | ||||
| -rw-r--r-- | src/intel/compiler/brw_compiler.h | 1 | ||||
| -rw-r--r-- | src/intel/compiler/brw_fs_generator.cpp | 6 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_wm.c | 10 |
4 files changed, 10 insertions, 13 deletions
diff --git a/src/intel/blorp/blorp.c b/src/intel/blorp/blorp.c index e8a2c6135f5..52675ec4ac5 100644 --- a/src/intel/blorp/blorp.c +++ b/src/intel/blorp/blorp.c @@ -176,8 +176,10 @@ blorp_compile_fs(struct blorp_context *blorp, void *mem_ctx, wm_prog_data->base.nr_params = 0; wm_prog_data->base.param = NULL; - /* BLORP always just uses the first two binding table entries */ - wm_prog_data->binding_table.render_target_start = BLORP_RENDERBUFFER_BT_INDEX; + /* BLORP always uses the first two binding table entries: + * - Surface 0 is the render target (which always start from 0) + * - Surface 1 is the source texture + */ wm_prog_data->base.binding_table.texture_start = BLORP_TEXTURE_BT_INDEX; nir = brw_preprocess_nir(compiler, nir); diff --git a/src/intel/compiler/brw_compiler.h b/src/intel/compiler/brw_compiler.h index 0060c381c0d..b1086bbcee5 100644 --- a/src/intel/compiler/brw_compiler.h +++ b/src/intel/compiler/brw_compiler.h @@ -681,7 +681,6 @@ struct brw_wm_prog_data { /** @{ * surface indices the WM-specific surfaces */ - uint32_t render_target_start; uint32_t render_target_read_start; /** @} */ } binding_table; diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp index 91bf0643084..cd5be054f69 100644 --- a/src/intel/compiler/brw_fs_generator.cpp +++ b/src/intel/compiler/brw_fs_generator.cpp @@ -287,8 +287,6 @@ fs_generator::fire_fb_write(fs_inst *inst, * messages set "Render Target Index" to 0. Using a different binding * table index would make it impossible to use headerless messages. */ - assert(prog_data->binding_table.render_target_start == 0); - const uint32_t surf_index = inst->target; bool last_render_target = inst->eot || @@ -427,8 +425,8 @@ fs_generator::generate_fb_read(fs_inst *inst, struct brw_reg dst, { assert(inst->size_written % REG_SIZE == 0); struct brw_wm_prog_data *prog_data = brw_wm_prog_data(this->prog_data); - const unsigned surf_index = - prog_data->binding_table.render_target_start + inst->target; + /* We assume that render targets start at binding table index 0. */ + const unsigned surf_index = inst->target; gen9_fb_READ(p, dst, payload, surf_index, inst->header_size, inst->size_written / REG_SIZE, diff --git a/src/mesa/drivers/dri/i965/brw_wm.c b/src/mesa/drivers/dri/i965/brw_wm.c index 942fb04a804..0072bdd0fb4 100644 --- a/src/mesa/drivers/dri/i965/brw_wm.c +++ b/src/mesa/drivers/dri/i965/brw_wm.c @@ -46,13 +46,11 @@ assign_fs_binding_table_offsets(const struct gen_device_info *devinfo, const struct brw_wm_prog_key *key, struct brw_wm_prog_data *prog_data) { - uint32_t next_binding_table_offset = 0; - - /* If there are no color regions, we still perform an FB write to a null - * renderbuffer, which we place at surface index 0. + /* Render targets implicitly start at surface index 0. Even if there are + * no color regions, we still perform an FB write to a null render target, + * which will be surface 0. */ - prog_data->binding_table.render_target_start = next_binding_table_offset; - next_binding_table_offset += MAX2(key->nr_color_regions, 1); + uint32_t next_binding_table_offset = MAX2(key->nr_color_regions, 1); next_binding_table_offset = brw_assign_common_binding_table_offsets(devinfo, prog, &prog_data->base, |