diff options
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_descriptors.c | 6 | ||||
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_shader.c | 13 | ||||
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_shader.h | 13 | ||||
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_state_draw.c | 9 | ||||
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_state_shaders.c | 4 |
5 files changed, 18 insertions, 27 deletions
diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c index 47e455f9bc7..2f6f8eb57e8 100644 --- a/src/gallium/drivers/radeonsi/si_descriptors.c +++ b/src/gallium/drivers/radeonsi/si_descriptors.c @@ -1835,8 +1835,12 @@ static void si_set_user_data_base(struct si_context *sctx, if (*base != new_base) { *base = new_base; - if (new_base) + if (new_base) { si_mark_shader_pointers_dirty(sctx, shader); + + if (shader == PIPE_SHADER_VERTEX) + sctx->last_vs_state = ~0; + } } } diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c index 5c17c640a3c..7adf76a0b03 100644 --- a/src/gallium/drivers/radeonsi/si_shader.c +++ b/src/gallium/drivers/radeonsi/si_shader.c @@ -227,7 +227,7 @@ static LLVMValueRef get_tcs_in_patch_stride(struct si_shader_context *ctx) { if (ctx->type == PIPE_SHADER_VERTEX) - return unpack_param(ctx, SI_PARAM_LS_OUT_LAYOUT, 8, 13); + return unpack_param(ctx, SI_PARAM_VS_STATE_BITS, 8, 13); else if (ctx->type == PIPE_SHADER_TESS_CTRL) return unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 8, 13); else { @@ -2663,7 +2663,7 @@ static void si_llvm_emit_ls_epilogue(struct lp_build_tgsi_context *bld_base) LLVMValueRef vertex_id = LLVMGetParam(ctx->main_fn, ctx->param_rel_auto_id); LLVMValueRef vertex_dw_stride = - unpack_param(ctx, SI_PARAM_LS_OUT_LAYOUT, 24, 8); + unpack_param(ctx, SI_PARAM_VS_STATE_BITS, 24, 8); LLVMValueRef base_dw_addr = LLVMBuildMul(gallivm->builder, vertex_id, vertex_dw_stride, ""); @@ -5609,19 +5609,16 @@ static void create_function(struct si_shader_context *ctx) params[SI_PARAM_BASE_VERTEX] = ctx->i32; params[SI_PARAM_START_INSTANCE] = ctx->i32; params[SI_PARAM_DRAWID] = ctx->i32; - num_params = SI_PARAM_DRAWID+1; + params[SI_PARAM_VS_STATE_BITS] = ctx->i32; + num_params = SI_PARAM_VS_STATE_BITS+1; if (shader->key.as_es) { params[ctx->param_es2gs_offset = num_params++] = ctx->i32; } else if (shader->key.as_ls) { - params[SI_PARAM_LS_OUT_LAYOUT] = ctx->i32; - num_params = SI_PARAM_LS_OUT_LAYOUT+1; + /* no extra parameters */ } else { if (shader->is_gs_copy_shader) { num_params = SI_PARAM_RW_BUFFERS+1; - } else { - params[SI_PARAM_VS_STATE_BITS] = ctx->i32; - num_params = SI_PARAM_VS_STATE_BITS+1; } /* The locations of the other parameters are assigned dynamically. */ diff --git a/src/gallium/drivers/radeonsi/si_shader.h b/src/gallium/drivers/radeonsi/si_shader.h index 6ce2b26c974..fdb0dd482bc 100644 --- a/src/gallium/drivers/radeonsi/si_shader.h +++ b/src/gallium/drivers/radeonsi/si_shader.h @@ -98,16 +98,9 @@ enum { SI_SGPR_BASE_VERTEX, SI_SGPR_START_INSTANCE, SI_SGPR_DRAWID, - SI_ES_NUM_USER_SGPR, - - /* hw VS only */ - SI_SGPR_VS_STATE_BITS = SI_ES_NUM_USER_SGPR, + SI_SGPR_VS_STATE_BITS, SI_VS_NUM_USER_SGPR, - /* hw LS only */ - SI_SGPR_LS_OUT_LAYOUT = SI_ES_NUM_USER_SGPR, - SI_LS_NUM_USER_SGPR, - /* both TCS and TES */ SI_SGPR_TCS_OFFCHIP_LAYOUT = SI_NUM_RESOURCE_SGPRS, SI_TES_NUM_USER_SGPR, @@ -146,11 +139,7 @@ enum { SI_PARAM_BASE_VERTEX, SI_PARAM_START_INSTANCE, SI_PARAM_DRAWID, - /* [0] = clamp vertex color, VS as VS only */ SI_PARAM_VS_STATE_BITS, - /* same value as TCS_IN_LAYOUT, VS as LS only */ - SI_PARAM_LS_OUT_LAYOUT = SI_PARAM_DRAWID + 1, - /* the other VS parameters are assigned dynamically */ /* Layout of TCS outputs in the offchip buffer * [0:8] = the number of patches per threadgroup. diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c index 7bf4f4ddb87..0d70ea9d6d7 100644 --- a/src/gallium/drivers/radeonsi/si_state_draw.c +++ b/src/gallium/drivers/radeonsi/si_state_draw.c @@ -222,9 +222,9 @@ static void si_emit_derived_tess_state(struct si_context *sctx, (num_tcs_output_cp << 9) | *num_patches; /* Set them for LS. */ - radeon_set_sh_reg(cs, - R_00B530_SPI_SHADER_USER_DATA_LS_0 + SI_SGPR_LS_OUT_LAYOUT * 4, - tcs_in_layout); + sctx->current_vs_state &= C_VS_STATE_LS_OUT_PATCH_SIZE & + C_VS_STATE_LS_OUT_VERTEX_SIZE; + sctx->current_vs_state |= tcs_in_layout; /* Set them for TCS. */ radeon_set_sh_reg_seq(cs, @@ -500,7 +500,8 @@ static void si_emit_vs_state(struct si_context *sctx) struct radeon_winsys_cs *cs = sctx->b.gfx.cs; radeon_set_sh_reg(cs, - R_00B130_SPI_SHADER_USER_DATA_VS_0 + SI_SGPR_VS_STATE_BITS * 4, + sctx->shader_userdata.sh_base[PIPE_SHADER_VERTEX] + + SI_SGPR_VS_STATE_BITS * 4, sctx->current_vs_state); sctx->last_vs_state = sctx->current_vs_state; diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c index d175b9c75e5..78c7495ce8f 100644 --- a/src/gallium/drivers/radeonsi/si_state_shaders.c +++ b/src/gallium/drivers/radeonsi/si_state_shaders.c @@ -464,7 +464,7 @@ static void si_shader_ls(struct si_screen *sscreen, struct si_shader *shader) S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt) | S_00B528_DX10_CLAMP(1) | S_00B528_FLOAT_MODE(shader->config.float_mode); - shader->config.rsrc2 = S_00B52C_USER_SGPR(SI_LS_NUM_USER_SGPR) | + shader->config.rsrc2 = S_00B52C_USER_SGPR(SI_VS_NUM_USER_SGPR) | S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0); } @@ -512,7 +512,7 @@ static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader) if (shader->selector->type == PIPE_SHADER_VERTEX) { vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : 0; - num_user_sgprs = SI_ES_NUM_USER_SGPR; + num_user_sgprs = SI_VS_NUM_USER_SGPR; } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) { vgpr_comp_cnt = 3; /* all components are needed for TES */ num_user_sgprs = SI_TES_NUM_USER_SGPR; |