diff options
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_meta_fast_clear.c | 8 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 9 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 3 |
3 files changed, 9 insertions, 11 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c b/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c index f5ecbb54989..eb201736c6e 100644 --- a/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c +++ b/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c @@ -204,7 +204,7 @@ brw_draw_rectlist(struct gl_context *ctx, struct rect *rect, int num_instances) } static void -get_fast_clear_rect(struct brw_context *brw, struct gl_framebuffer *fb, +get_fast_clear_rect(struct gl_framebuffer *fb, struct intel_renderbuffer *irb, struct rect *rect) { unsigned int x_align, y_align; @@ -226,7 +226,7 @@ get_fast_clear_rect(struct brw_context *brw, struct gl_framebuffer *fb, * alignment size returned by intel_get_non_msrt_mcs_alignment(), but * with X alignment multiplied by 16 and Y alignment multiplied by 32. */ - intel_get_non_msrt_mcs_alignment(brw, irb->mt, &x_align, &y_align); + intel_get_non_msrt_mcs_alignment(irb->mt, &x_align, &y_align); x_align *= 16; y_align *= 32; @@ -516,7 +516,7 @@ brw_meta_fast_clear(struct brw_context *brw, struct gl_framebuffer *fb, irb->mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_RESOLVED; irb->need_downsample = true; fast_clear_buffers |= 1 << index; - get_fast_clear_rect(brw, fb, irb, &fast_clear_rect); + get_fast_clear_rect(fb, irb, &fast_clear_rect); break; case REP_CLEAR: @@ -653,7 +653,7 @@ get_resolve_rect(struct brw_context *brw, * by 8 and 16 and 8 and 8 for SKL. */ - intel_get_non_msrt_mcs_alignment(brw, mt, &x_align, &y_align); + intel_get_non_msrt_mcs_alignment(mt, &x_align, &y_align); if (brw->gen >= 9) { x_scaledown = x_align * 8; y_scaledown = y_align * 8; diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index eafd2a6be9a..97e7e73ace9 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c @@ -57,7 +57,7 @@ intel_miptree_alloc_mcs(struct brw_context *brw, * created, based on the chip generation and the surface type. */ static enum intel_msaa_layout -compute_msaa_layout(struct brw_context *brw, mesa_format format, GLenum target, +compute_msaa_layout(struct brw_context *brw, mesa_format format, bool disable_aux_buffers) { /* Prior to Gen7, all MSAA surfaces used IMS layout. */ @@ -138,8 +138,7 @@ compute_msaa_layout(struct brw_context *brw, mesa_format format, GLenum target, * by half the block width, and Y coordinates by half the block height. */ void -intel_get_non_msrt_mcs_alignment(struct brw_context *brw, - struct intel_mipmap_tree *mt, +intel_get_non_msrt_mcs_alignment(struct intel_mipmap_tree *mt, unsigned *width_px, unsigned *height) { switch (mt->tiling) { @@ -320,7 +319,7 @@ intel_miptree_create_layout(struct brw_context *brw, if (num_samples > 1) { /* Adjust width/height/depth for MSAA */ mt->msaa_layout = compute_msaa_layout(brw, format, - mt->target, mt->disable_aux_buffers); + mt->disable_aux_buffers); if (mt->msaa_layout == INTEL_MSAA_LAYOUT_IMS) { /* From the Ivybridge PRM, Volume 1, Part 1, page 108: * "If the surface is multisampled and it is a depth or stencil @@ -1425,7 +1424,7 @@ intel_miptree_alloc_non_msrt_mcs(struct brw_context *brw, const mesa_format format = MESA_FORMAT_R_UINT32; unsigned block_width_px; unsigned block_height; - intel_get_non_msrt_mcs_alignment(brw, mt, &block_width_px, &block_height); + intel_get_non_msrt_mcs_alignment(mt, &block_width_px, &block_height); unsigned width_divisor = block_width_px * 4; unsigned height_divisor = block_height * 8; unsigned mcs_width = diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h index 7b5f97b3368..0e92b95de5d 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h @@ -515,8 +515,7 @@ struct intel_mipmap_tree }; void -intel_get_non_msrt_mcs_alignment(struct brw_context *brw, - struct intel_mipmap_tree *mt, +intel_get_non_msrt_mcs_alignment(struct intel_mipmap_tree *mt, unsigned *width_px, unsigned *height); bool intel_tiling_supports_non_msrt_mcs(struct brw_context *brw, unsigned tiling); |