diff options
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_vec4.h | 1 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 39 |
2 files changed, 23 insertions, 17 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h b/src/mesa/drivers/dri/i965/brw_vec4.h index 9b932960589..8c613bd9572 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4.h +++ b/src/mesa/drivers/dri/i965/brw_vec4.h @@ -464,6 +464,7 @@ public: void emit_math(enum opcode opcode, dst_reg dst, src_reg src0, src_reg src1); void emit_ndc_computation(); + void emit_psiz_and_flags(struct brw_reg reg); int emit_vue_header_gen6(int header_mrf); int emit_vue_header_gen4(int header_mrf); void emit_urb_writes(void); diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp index 3335ea246fb..bd8878a1ebe 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp @@ -1721,13 +1721,12 @@ vec4_visitor::emit_ndc_computation() emit(MUL(ndc_xyz, pos, src_reg(ndc_w))); } -int -vec4_visitor::emit_vue_header_gen4(int header_mrf) +void +vec4_visitor::emit_psiz_and_flags(struct brw_reg reg) { - emit_ndc_computation(); - - if ((c->prog_data.outputs_written & BITFIELD64_BIT(VERT_RESULT_PSIZ)) || - c->key.nr_userclip || brw->has_negative_rhw_bug) { + if (intel->gen < 6 && + ((c->prog_data.outputs_written & BITFIELD64_BIT(VERT_RESULT_PSIZ)) || + c->key.nr_userclip || brw->has_negative_rhw_bug)) { dst_reg header1 = dst_reg(this, glsl_type::uvec4_type); GLuint i; @@ -1778,11 +1777,24 @@ vec4_visitor::emit_vue_header_gen4(int header_mrf) } header1.writemask = WRITEMASK_XYZW; - emit(MOV(brw_message_reg(header_mrf++), src_reg(header1))); + emit(MOV(reg, src_reg(header1))); + } else if (intel->gen < 6) { + emit(MOV(retype(reg, BRW_REGISTER_TYPE_UD), 0u)); } else { - emit(MOV(retype(brw_message_reg(header_mrf++), - BRW_REGISTER_TYPE_UD), 0u)); + emit(MOV(retype(reg, BRW_REGISTER_TYPE_D), src_reg(0))); + if (c->prog_data.outputs_written & BITFIELD64_BIT(VERT_RESULT_PSIZ)) { + emit(MOV(brw_writemask(reg, WRITEMASK_W), + src_reg(output_reg[VERT_RESULT_PSIZ]))); + } } +} + +int +vec4_visitor::emit_vue_header_gen4(int header_mrf) +{ + emit_ndc_computation(); + + emit_psiz_and_flags(brw_message_reg(header_mrf++)); if (intel->gen == 5) { /* There are 20 DWs (D0-D19) in VUE header on Ironlake: @@ -1828,8 +1840,6 @@ vec4_visitor::emit_vue_header_gen4(int header_mrf) int vec4_visitor::emit_vue_header_gen6(int header_mrf) { - struct brw_reg reg; - /* There are 8 or 16 DWs (D0-D15) in VUE header on Sandybridge: * dword 0-3 (m2) of the header is indices, point width, clip flags. * dword 4-7 (m3) is the 4D space position @@ -1840,12 +1850,7 @@ vec4_visitor::emit_vue_header_gen6(int header_mrf) */ current_annotation = "indices, point width, clip flags"; - reg = brw_message_reg(header_mrf++); - emit(MOV(retype(reg, BRW_REGISTER_TYPE_D), src_reg(0))); - if (c->prog_data.outputs_written & BITFIELD64_BIT(VERT_RESULT_PSIZ)) { - emit(MOV(brw_writemask(reg, WRITEMASK_W), - src_reg(output_reg[VERT_RESULT_PSIZ]))); - } + emit_psiz_and_flags(brw_message_reg(header_mrf++)); current_annotation = "gl_Position"; emit(MOV(brw_message_reg(header_mrf++), |