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-rw-r--r--src/mesa/drivers/dri/i965/brw_device_info.c2
-rw-r--r--src/mesa/drivers/dri/i965/gen8_ps_state.c5
2 files changed, 5 insertions, 2 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_device_info.c b/src/mesa/drivers/dri/i965/brw_device_info.c
index d931091ee6e..e4c110da036 100644
--- a/src/mesa/drivers/dri/i965/brw_device_info.c
+++ b/src/mesa/drivers/dri/i965/brw_device_info.c
@@ -201,7 +201,7 @@ static const struct brw_device_info brw_device_info_hsw_gt3 = {
.has_pln = true, \
.max_vs_threads = 280, \
.max_gs_threads = 256, \
- .max_wm_threads = 64, /* threads per PSD */ \
+ .max_wm_threads = 408, \
.urb = { \
.size = 128, \
.min_vs_entries = 64, \
diff --git a/src/mesa/drivers/dri/i965/gen8_ps_state.c b/src/mesa/drivers/dri/i965/gen8_ps_state.c
index c2810bb21b9..561fc96e7d3 100644
--- a/src/mesa/drivers/dri/i965/gen8_ps_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_ps_state.c
@@ -174,7 +174,10 @@ upload_ps_state(struct brw_context *brw)
if (ctx->Shader.CurrentProgram[MESA_SHADER_FRAGMENT] == NULL)
dw3 |= GEN7_PS_FLOATING_POINT_MODE_ALT;
- dw6 |= (brw->max_wm_threads - 2) << HSW_PS_MAX_THREADS_SHIFT;
+ /* 3DSTATE_PS expects the number of threads per PSD, which is always 64;
+ * it implicitly scales for different GT levels (which have some # of PSDs).
+ */
+ dw6 |= (64 - 2) << HSW_PS_MAX_THREADS_SHIFT;
/* CACHE_NEW_WM_PROG */
if (brw->wm.prog_data->base.nr_params > 0)