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-rw-r--r--configure.ac2
-rw-r--r--meson.build2
-rw-r--r--src/gallium/drivers/freedreno/a6xx/fd6_emit.c16
-rw-r--r--src/gallium/drivers/freedreno/a6xx/fd6_emit.h30
4 files changed, 48 insertions, 2 deletions
diff --git a/configure.ac b/configure.ac
index 520948b0518..ab9bdce885f 100644
--- a/configure.ac
+++ b/configure.ac
@@ -78,7 +78,7 @@ LIBDRM_AMDGPU_REQUIRED=2.4.93
LIBDRM_INTEL_REQUIRED=2.4.75
LIBDRM_NVVIEUX_REQUIRED=2.4.66
LIBDRM_NOUVEAU_REQUIRED=2.4.66
-LIBDRM_FREEDRENO_REQUIRED=2.4.93
+LIBDRM_FREEDRENO_REQUIRED=2.4.96
LIBDRM_ETNAVIV_REQUIRED=2.4.89
LIBDRM_VC4_REQUIRED=2.4.89
diff --git a/meson.build b/meson.build
index 002ce35a608..505cc6c79bd 100644
--- a/meson.build
+++ b/meson.build
@@ -1112,7 +1112,7 @@ _drm_amdgpu_ver = '2.4.93'
_drm_radeon_ver = '2.4.71'
_drm_nouveau_ver = '2.4.66'
_drm_etnaviv_ver = '2.4.89'
-_drm_freedreno_ver = '2.4.93'
+_drm_freedreno_ver = '2.4.96'
_drm_intel_ver = '2.4.75'
_drm_ver = '2.4.75'
diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_emit.c b/src/gallium/drivers/freedreno/a6xx/fd6_emit.c
index 45bb5250ec8..fc4a53f8651 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_emit.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_emit.c
@@ -940,6 +940,22 @@ fd6_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
if (ctx->dirty_shader[PIPE_SHADER_FRAGMENT] & FD_DIRTY_SHADER_IMAGE)
fd6_emit_images(ctx, ring, PIPE_SHADER_FRAGMENT);
+
+ if (emit->num_groups > 0) {
+ OUT_PKT7(ring, CP_SET_DRAW_STATE, 3 * emit->num_groups);
+ for (unsigned i = 0; i < emit->num_groups; i++) {
+ struct fd6_state_group *g = &emit->groups[i];
+ unsigned n = fd_ringbuffer_size(g->stateobj) / 4;
+
+ OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(n) |
+ CP_SET_DRAW_STATE__0_ENABLE_MASK(g->enable_mask) |
+ CP_SET_DRAW_STATE__0_GROUP_ID(g->group_id));
+ OUT_RB(ring, g->stateobj);
+
+ fd_ringbuffer_del(g->stateobj);
+ }
+ emit->num_groups = 0;
+ }
}
void
diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_emit.h b/src/gallium/drivers/freedreno/a6xx/fd6_emit.h
index 4ebb5987423..a2117a1b244 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_emit.h
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_emit.h
@@ -38,6 +38,20 @@
struct fd_ringbuffer;
+/* To collect all the state objects to emit in a single CP_SET_DRAW_STATE
+ * packet, the emit tracks a collection of however many state_group's that
+ * need to be emit'd.
+ */
+enum fd6_state_id {
+ FD6_GROUP_CONST,
+};
+
+struct fd6_state_group {
+ struct fd_ringbuffer *stateobj;
+ enum fd6_state_id group_id;
+ uint8_t enable_mask;
+};
+
/* grouped together emit-state for prog/vertex/state emit: */
struct fd6_emit {
struct pipe_debug_callback *debug;
@@ -63,6 +77,9 @@ struct fd6_emit {
/* TODO: other shader stages.. */
unsigned streamout_mask;
+
+ struct fd6_state_group groups[32];
+ unsigned num_groups;
};
static inline const struct ir3_shader_variant *
@@ -92,6 +109,19 @@ fd6_emit_get_fp(struct fd6_emit *emit)
}
static inline void
+fd6_emit_add_group(struct fd6_emit *emit, struct fd_ringbuffer *stateobj,
+ enum fd6_state_id group_id, unsigned enable_mask)
+{
+ debug_assert(emit->num_groups < ARRAY_SIZE(emit->groups));
+ if (fd_ringbuffer_size(stateobj) == 0)
+ return;
+ struct fd6_state_group *g = &emit->groups[emit->num_groups++];
+ g->stateobj = stateobj;
+ g->group_id = group_id;
+ g->enable_mask = enable_mask;
+}
+
+static inline void
fd6_event_write(struct fd_batch *batch, struct fd_ringbuffer *ring,
enum vgt_event_type evt, bool timestamp)
{