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-rw-r--r--src/mesa/drivers/dri/i965/brw_link.cpp20
-rw-r--r--src/mesa/drivers/dri/i965/intel_extensions.c1
2 files changed, 15 insertions, 6 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_link.cpp b/src/mesa/drivers/dri/i965/brw_link.cpp
index b2664b8b6ea..a77df50c7c4 100644
--- a/src/mesa/drivers/dri/i965/brw_link.cpp
+++ b/src/mesa/drivers/dri/i965/brw_link.cpp
@@ -106,12 +106,20 @@ process_glsl_ir(gl_shader_stage stage,
*/
brw_lower_packing_builtins(brw, shader->Stage, shader->ir);
do_mat_op_to_vec(shader->ir);
- lower_instructions(shader->ir,
- DIV_TO_MUL_RCP |
- SUB_TO_ADD_NEG |
- EXP_TO_EXP2 |
- LOG_TO_LOG2 |
- DFREXP_DLDEXP_TO_ARITH);
+
+ unsigned instructions_to_lower = (DIV_TO_MUL_RCP |
+ SUB_TO_ADD_NEG |
+ EXP_TO_EXP2 |
+ LOG_TO_LOG2 |
+ DFREXP_DLDEXP_TO_ARITH);
+ if (brw->gen < 7) {
+ instructions_to_lower |= BIT_COUNT_TO_MATH |
+ EXTRACT_TO_SHIFTS |
+ INSERT_TO_SHIFTS |
+ REVERSE_TO_SHIFTS;
+ }
+
+ lower_instructions(shader->ir, instructions_to_lower);
/* Pre-gen6 HW can only nest if-statements 16 deep. Beyond this,
* if-statements need to be flattened.
diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c b/src/mesa/drivers/dri/i965/intel_extensions.c
index cf383bcaae4..5ebcba20e29 100644
--- a/src/mesa/drivers/dri/i965/intel_extensions.c
+++ b/src/mesa/drivers/dri/i965/intel_extensions.c
@@ -278,6 +278,7 @@ intelInitExtensions(struct gl_context *ctx)
_mesa_override_glsl_version(&ctx->Const);
ctx->Extensions.EXT_shader_integer_mix = ctx->Const.GLSLVersion >= 130;
+ ctx->Extensions.MESA_shader_integer_functions = ctx->Const.GLSLVersion >= 130;
if (brw->gen >= 5) {
ctx->Extensions.ARB_texture_query_levels = ctx->Const.GLSLVersion >= 130;