4 files changed, 0 insertions, 81 deletions
diff --git a/src/gallium/drivers/radeon/AMDGPU.h b/src/gallium/drivers/radeon/AMDGPU.h
index 9ab8e82ce69..0f42cb744d3 100644
--- a/src/gallium/drivers/radeon/AMDGPU.h
+++ b/src/gallium/drivers/radeon/AMDGPU.h
@@ -26,7 +26,6 @@ FunctionPass *createR600LowerInstructionsPass(TargetMachine &tm);
 
 // SI Passes
 FunctionPass *createSIAssignInterpRegsPass(TargetMachine &tm);
-FunctionPass *createSILowerShaderInstructionsPass(TargetMachine &tm);
 FunctionPass *createSIPropagateImmReadsPass(TargetMachine &tm);
 FunctionPass *createSICodeEmitterPass(formatted_raw_ostream &OS);
 
diff --git a/src/gallium/drivers/radeon/AMDGPUTargetMachine.cpp b/src/gallium/drivers/radeon/AMDGPUTargetMachine.cpp
index 6d292be9ec6..c1c21abc9c1 100644
--- a/src/gallium/drivers/radeon/AMDGPUTargetMachine.cpp
+++ b/src/gallium/drivers/radeon/AMDGPUTargetMachine.cpp
@@ -130,7 +130,6 @@ bool AMDGPUPassConfig::addPreRegAlloc() {
   if (ST.device()->getGeneration() <= AMDILDeviceInfo::HD6XXX) {
     PM->add(createR600LowerInstructionsPass(*TM));
   } else {
-    PM->add(createSILowerShaderInstructionsPass(*TM));
     PM->add(createSIAssignInterpRegsPass(*TM));
   }
   PM->add(createAMDGPULowerInstructionsPass(*TM));
diff --git a/src/gallium/drivers/radeon/Makefile.sources b/src/gallium/drivers/radeon/Makefile.sources
index 8c302e160d4..b7f70c2dad5 100644
--- a/src/gallium/drivers/radeon/Makefile.sources
+++ b/src/gallium/drivers/radeon/Makefile.sources
@@ -54,7 +54,6 @@ CPP_SOURCES := \
 	SICodeEmitter.cpp		\
 	SIInstrInfo.cpp			\
 	SIISelLowering.cpp		\
-	SILowerShaderInstructions.cpp	\
 	SIMachineFunctionInfo.cpp	\
 	SIPropagateImmReads.cpp		\
 	SIRegisterInfo.cpp		\
diff --git a/src/gallium/drivers/radeon/SILowerShaderInstructions.cpp b/src/gallium/drivers/radeon/SILowerShaderInstructions.cpp
deleted file mode 100644
index 0c5a831440b..00000000000
--- a/src/gallium/drivers/radeon/SILowerShaderInstructions.cpp
+++ /dev/null
@@ -1,78 +0,0 @@
-//===-- SILowerShaderInstructions.cpp - Pass for lowering shader instructions  -------===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// TODO: Add full description
-//
-//===----------------------------------------------------------------------===//
-
-
-#include "AMDGPU.h"
-#include "llvm/CodeGen/MachineFunctionPass.h"
-#include "llvm/CodeGen/MachineInstrBuilder.h"
-#include "llvm/CodeGen/MachineRegisterInfo.h"
-
-using namespace llvm;
-
-namespace {
-  class SILowerShaderInstructionsPass : public MachineFunctionPass {
-
-  private:
-    static char ID;
-    TargetMachine &TM;
-    MachineRegisterInfo * MRI;
-
-  public:
-    SILowerShaderInstructionsPass(TargetMachine &tm) :
-      MachineFunctionPass(ID), TM(tm) { }
-
-    bool runOnMachineFunction(MachineFunction &MF);
-
-    const char *getPassName() const { return "SI Lower Shader Instructions"; }
-
-    void lowerSET_M0(MachineInstr &MI, MachineBasicBlock &MBB,
-                     MachineBasicBlock::iterator I);
-  };
-} /* End anonymous namespace */
-
-char SILowerShaderInstructionsPass::ID = 0;
-
-FunctionPass *llvm::createSILowerShaderInstructionsPass(TargetMachine &tm) {
-    return new SILowerShaderInstructionsPass(tm);
-}
-
-bool SILowerShaderInstructionsPass::runOnMachineFunction(MachineFunction &MF)
-{
-  MRI = &MF.getRegInfo();
-  for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
-                                                  BB != BB_E; ++BB) {
-    MachineBasicBlock &MBB = *BB;
-    for (MachineBasicBlock::iterator I = MBB.begin(), Next = llvm::next(I);
-         I != MBB.end(); I = Next, Next = llvm::next(I) ) {
-      MachineInstr &MI = *I;
-      switch (MI.getOpcode()) {
-      case AMDIL::SET_M0:
-        lowerSET_M0(MI, MBB, I);
-        break;
-      default: continue;
-      }
-      MI.removeFromParent();
-    }
-  }
-
-  return false;
-}
-
-void SILowerShaderInstructionsPass::lowerSET_M0(MachineInstr &MI,
-    MachineBasicBlock &MBB, MachineBasicBlock::iterator I)
-{
-  const struct TargetInstrInfo * TII = TM.getInstrInfo();
-  BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(AMDIL::S_MOV_IMM_I32))
-          .addReg(AMDIL::M0)
-          .addOperand(MI.getOperand(1));
-}