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-rw-r--r--src/amd/common/ac_nir_to_llvm.c31
-rw-r--r--src/amd/vulkan/radv_pipeline.c1
2 files changed, 32 insertions, 0 deletions
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index f513ea1efef..10081454a8e 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -1774,6 +1774,37 @@ static void visit_alu(struct nir_to_llvm_context *ctx, nir_alu_instr *instr)
case nir_op_fddy_coarse:
result = emit_ddxy(ctx, instr->op, src[0]);
break;
+
+ case nir_op_unpack_64_2x32_split_x: {
+ assert(instr->src[0].src.ssa->num_components == 1);
+ LLVMValueRef tmp = LLVMBuildBitCast(ctx->builder, src[0],
+ LLVMVectorType(ctx->i32, 2),
+ "");
+ result = LLVMBuildExtractElement(ctx->builder, tmp,
+ ctx->i32zero, "");
+ break;
+ }
+
+ case nir_op_unpack_64_2x32_split_y: {
+ assert(instr->src[0].src.ssa->num_components == 1);
+ LLVMValueRef tmp = LLVMBuildBitCast(ctx->builder, src[0],
+ LLVMVectorType(ctx->i32, 2),
+ "");
+ result = LLVMBuildExtractElement(ctx->builder, tmp,
+ ctx->i32one, "");
+ break;
+ }
+
+ case nir_op_pack_64_2x32_split: {
+ LLVMValueRef tmp = LLVMGetUndef(LLVMVectorType(ctx->i32, 2));
+ tmp = LLVMBuildInsertElement(ctx->builder, tmp,
+ src[0], ctx->i32zero, "");
+ tmp = LLVMBuildInsertElement(ctx->builder, tmp,
+ src[1], ctx->i32one, "");
+ result = LLVMBuildBitCast(ctx->builder, tmp, ctx->i64, "");
+ break;
+ }
+
default:
fprintf(stderr, "Unknown NIR alu instr: ");
nir_print_instr(&instr->instr, stderr);
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index cf11362eade..e0c67ce5ea1 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -145,6 +145,7 @@ radv_optimize_nir(struct nir_shader *shader)
progress = false;
NIR_PASS_V(shader, nir_lower_vars_to_ssa);
+ NIR_PASS_V(shader, nir_lower_64bit_pack);
NIR_PASS_V(shader, nir_lower_alu_to_scalar);
NIR_PASS_V(shader, nir_lower_phis_to_scalar);