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-rw-r--r--src/intel/common/gen_device_info.c48
-rw-r--r--src/intel/common/gen_device_info.h4
-rw-r--r--src/intel/vulkan/anv_allocator.c2
-rw-r--r--src/mesa/drivers/dri/i965/brw_tes.c2
-rw-r--r--src/mesa/drivers/dri/i965/gen7_ds_state.c2
-rw-r--r--src/mesa/drivers/dri/i965/gen7_urb.c4
-rw-r--r--src/mesa/drivers/dri/i965/gen8_ds_state.c2
7 files changed, 32 insertions, 32 deletions
diff --git a/src/intel/common/gen_device_info.c b/src/intel/common/gen_device_info.c
index b12bfad6ea3..98669b35a0f 100644
--- a/src/intel/common/gen_device_info.c
+++ b/src/intel/common/gen_device_info.c
@@ -119,7 +119,7 @@ static const struct gen_device_info gen_device_info_ivb_gt1 = {
.num_slices = 1,
.max_vs_threads = 36,
.max_tcs_threads = 36,
- .max_ds_threads = 36,
+ .max_tes_threads = 36,
.max_gs_threads = 36,
.max_wm_threads = 48,
.max_cs_threads = 36,
@@ -129,7 +129,7 @@ static const struct gen_device_info gen_device_info_ivb_gt1 = {
.max_vs_entries = 512,
.max_tcs_entries = 32,
.min_ds_entries = 10,
- .max_ds_entries = 288,
+ .max_tes_entries = 288,
.max_gs_entries = 192,
},
};
@@ -139,7 +139,7 @@ static const struct gen_device_info gen_device_info_ivb_gt2 = {
.num_slices = 1,
.max_vs_threads = 128,
.max_tcs_threads = 128,
- .max_ds_threads = 128,
+ .max_tes_threads = 128,
.max_gs_threads = 128,
.max_wm_threads = 172,
.max_cs_threads = 64,
@@ -149,7 +149,7 @@ static const struct gen_device_info gen_device_info_ivb_gt2 = {
.max_vs_entries = 704,
.max_tcs_entries = 64,
.min_ds_entries = 10,
- .max_ds_entries = 448,
+ .max_tes_entries = 448,
.max_gs_entries = 320,
},
};
@@ -160,7 +160,7 @@ static const struct gen_device_info gen_device_info_byt = {
.has_llc = false,
.max_vs_threads = 36,
.max_tcs_threads = 36,
- .max_ds_threads = 36,
+ .max_tes_threads = 36,
.max_gs_threads = 36,
.max_wm_threads = 48,
.max_cs_threads = 32,
@@ -170,7 +170,7 @@ static const struct gen_device_info gen_device_info_byt = {
.max_vs_entries = 512,
.max_tcs_entries = 32,
.min_ds_entries = 10,
- .max_ds_entries = 288,
+ .max_tes_entries = 288,
.max_gs_entries = 192,
},
};
@@ -186,7 +186,7 @@ static const struct gen_device_info gen_device_info_hsw_gt1 = {
.num_slices = 1,
.max_vs_threads = 70,
.max_tcs_threads = 70,
- .max_ds_threads = 70,
+ .max_tes_threads = 70,
.max_gs_threads = 70,
.max_wm_threads = 102,
.max_cs_threads = 70,
@@ -196,7 +196,7 @@ static const struct gen_device_info gen_device_info_hsw_gt1 = {
.max_vs_entries = 640,
.max_tcs_entries = 64,
.min_ds_entries = 10,
- .max_ds_entries = 384,
+ .max_tes_entries = 384,
.max_gs_entries = 256,
},
};
@@ -206,7 +206,7 @@ static const struct gen_device_info gen_device_info_hsw_gt2 = {
.num_slices = 1,
.max_vs_threads = 280,
.max_tcs_threads = 256,
- .max_ds_threads = 280,
+ .max_tes_threads = 280,
.max_gs_threads = 256,
.max_wm_threads = 204,
.max_cs_threads = 70,
@@ -216,7 +216,7 @@ static const struct gen_device_info gen_device_info_hsw_gt2 = {
.max_vs_entries = 1664,
.max_tcs_entries = 128,
.min_ds_entries = 10,
- .max_ds_entries = 960,
+ .max_tes_entries = 960,
.max_gs_entries = 640,
},
};
@@ -226,7 +226,7 @@ static const struct gen_device_info gen_device_info_hsw_gt3 = {
.num_slices = 2,
.max_vs_threads = 280,
.max_tcs_threads = 256,
- .max_ds_threads = 280,
+ .max_tes_threads = 280,
.max_gs_threads = 256,
.max_wm_threads = 408,
.max_cs_threads = 70,
@@ -236,7 +236,7 @@ static const struct gen_device_info gen_device_info_hsw_gt3 = {
.max_vs_entries = 1664,
.max_tcs_entries = 128,
.min_ds_entries = 10,
- .max_ds_entries = 960,
+ .max_tes_entries = 960,
.max_gs_entries = 640,
},
};
@@ -252,7 +252,7 @@ static const struct gen_device_info gen_device_info_hsw_gt3 = {
.has_surface_tile_offset = true, \
.max_vs_threads = 504, \
.max_tcs_threads = 504, \
- .max_ds_threads = 504, \
+ .max_tes_threads = 504, \
.max_gs_threads = 504, \
.max_wm_threads = 384
@@ -266,7 +266,7 @@ static const struct gen_device_info gen_device_info_bdw_gt1 = {
.max_vs_entries = 2560,
.max_tcs_entries = 504,
.min_ds_entries = 34,
- .max_ds_entries = 1536,
+ .max_tes_entries = 1536,
.max_gs_entries = 960,
}
};
@@ -281,7 +281,7 @@ static const struct gen_device_info gen_device_info_bdw_gt2 = {
.max_vs_entries = 2560,
.max_tcs_entries = 504,
.min_ds_entries = 34,
- .max_ds_entries = 1536,
+ .max_tes_entries = 1536,
.max_gs_entries = 960,
}
};
@@ -296,7 +296,7 @@ static const struct gen_device_info gen_device_info_bdw_gt3 = {
.max_vs_entries = 2560,
.max_tcs_entries = 504,
.min_ds_entries = 34,
- .max_ds_entries = 1536,
+ .max_tes_entries = 1536,
.max_gs_entries = 960,
}
};
@@ -307,7 +307,7 @@ static const struct gen_device_info gen_device_info_chv = {
.num_slices = 1,
.max_vs_threads = 80,
.max_tcs_threads = 80,
- .max_ds_threads = 80,
+ .max_tes_threads = 80,
.max_gs_threads = 80,
.max_wm_threads = 128,
.max_cs_threads = 6 * 7,
@@ -317,7 +317,7 @@ static const struct gen_device_info gen_device_info_chv = {
.max_vs_entries = 640,
.max_tcs_entries = 80,
.min_ds_entries = 34,
- .max_ds_entries = 384,
+ .max_tes_entries = 384,
.max_gs_entries = 256,
}
};
@@ -334,7 +334,7 @@ static const struct gen_device_info gen_device_info_chv = {
.max_vs_threads = 336, \
.max_gs_threads = 336, \
.max_tcs_threads = 336, \
- .max_ds_threads = 336, \
+ .max_tes_threads = 336, \
.max_wm_threads = 64 * 9, \
.max_cs_threads = 56, \
.urb = { \
@@ -343,7 +343,7 @@ static const struct gen_device_info gen_device_info_chv = {
.max_vs_entries = 1856, \
.max_tcs_entries = 672, \
.min_ds_entries = 34, \
- .max_ds_entries = 1120, \
+ .max_tes_entries = 1120, \
.max_gs_entries = 640, \
}
@@ -386,7 +386,7 @@ static const struct gen_device_info gen_device_info_bxt = {
.num_slices = 1,
.max_vs_threads = 112,
.max_tcs_threads = 112,
- .max_ds_threads = 112,
+ .max_tes_threads = 112,
.max_gs_threads = 112,
.max_wm_threads = 64 * 3,
.max_cs_threads = 6 * 6,
@@ -395,7 +395,7 @@ static const struct gen_device_info gen_device_info_bxt = {
.min_vs_entries = 34,
.max_vs_entries = 704,
.max_tcs_entries = 256,
- .max_ds_entries = 416,
+ .max_tes_entries = 416,
.max_gs_entries = 256,
}
};
@@ -409,7 +409,7 @@ static const struct gen_device_info gen_device_info_bxt_2x6 = {
.num_slices = 1,
.max_vs_threads = 56, /* XXX: guess */
.max_tcs_threads = 56, /* XXX: guess */
- .max_ds_threads = 56,
+ .max_tes_threads = 56,
.max_gs_threads = 56,
.max_wm_threads = 64 * 2,
.max_cs_threads = 6 * 6,
@@ -418,7 +418,7 @@ static const struct gen_device_info gen_device_info_bxt_2x6 = {
.min_vs_entries = 34,
.max_vs_entries = 352,
.max_tcs_entries = 128,
- .max_ds_entries = 208,
+ .max_tes_entries = 208,
.max_gs_entries = 128,
}
};
diff --git a/src/intel/common/gen_device_info.h b/src/intel/common/gen_device_info.h
index 40258d4239f..964e429cedd 100644
--- a/src/intel/common/gen_device_info.h
+++ b/src/intel/common/gen_device_info.h
@@ -95,7 +95,7 @@ struct gen_device_info
unsigned num_slices;
unsigned max_vs_threads; /**< Maximum Vertex Shader threads */
unsigned max_tcs_threads; /**< Maximum Hull Shader threads */
- unsigned max_ds_threads; /**< Maximum Domain Shader threads */
+ unsigned max_tes_threads; /**< Maximum Domain Shader threads */
unsigned max_gs_threads; /**< Maximum Geometry Shader threads. */
/**
* Theoretical maximum number of Pixel Shader threads.
@@ -137,7 +137,7 @@ struct gen_device_info
unsigned max_vs_entries;
unsigned max_tcs_entries;
unsigned min_ds_entries;
- unsigned max_ds_entries;
+ unsigned max_tes_entries;
unsigned max_gs_entries;
} urb;
/** @} */
diff --git a/src/intel/vulkan/anv_allocator.c b/src/intel/vulkan/anv_allocator.c
index 65fd38b1a04..d5c033c97e1 100644
--- a/src/intel/vulkan/anv_allocator.c
+++ b/src/intel/vulkan/anv_allocator.c
@@ -950,7 +950,7 @@ anv_scratch_pool_alloc(struct anv_device *device, struct anv_scratch_pool *pool,
uint32_t max_threads[] = {
[MESA_SHADER_VERTEX] = devinfo->max_vs_threads,
[MESA_SHADER_TESS_CTRL] = devinfo->max_tcs_threads,
- [MESA_SHADER_TESS_EVAL] = devinfo->max_ds_threads,
+ [MESA_SHADER_TESS_EVAL] = devinfo->max_tes_threads,
[MESA_SHADER_GEOMETRY] = devinfo->max_gs_threads,
[MESA_SHADER_FRAGMENT] = devinfo->max_wm_threads,
[MESA_SHADER_COMPUTE] = scratch_ids_per_subslice * subslices,
diff --git a/src/mesa/drivers/dri/i965/brw_tes.c b/src/mesa/drivers/dri/i965/brw_tes.c
index ffd5702af54..ad0eb2e070f 100644
--- a/src/mesa/drivers/dri/i965/brw_tes.c
+++ b/src/mesa/drivers/dri/i965/brw_tes.c
@@ -217,7 +217,7 @@ brw_codegen_tes_prog(struct brw_context *brw,
/* Scratch space is used for register spilling */
brw_alloc_stage_scratch(brw, stage_state,
prog_data.base.base.total_scratch,
- devinfo->max_ds_threads);
+ devinfo->max_tes_threads);
brw_upload_cache(&brw->cache, BRW_CACHE_TES_PROG,
key, sizeof(*key),
diff --git a/src/mesa/drivers/dri/i965/gen7_ds_state.c b/src/mesa/drivers/dri/i965/gen7_ds_state.c
index 57b187c5339..a255c53df9b 100644
--- a/src/mesa/drivers/dri/i965/gen7_ds_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_ds_state.c
@@ -71,7 +71,7 @@ gen7_upload_ds_state(struct brw_context *brw)
const struct brw_vue_prog_data *vue_prog_data = &tes_prog_data->base;
const struct brw_stage_prog_data *prog_data = &vue_prog_data->base;
- const unsigned thread_count = (devinfo->max_ds_threads - 1) <<
+ const unsigned thread_count = (devinfo->max_tes_threads - 1) <<
(brw->is_haswell ? HSW_DS_MAX_THREADS_SHIFT : GEN7_DS_MAX_THREADS_SHIFT);
if (active) {
diff --git a/src/mesa/drivers/dri/i965/gen7_urb.c b/src/mesa/drivers/dri/i965/gen7_urb.c
index fb87a94caa3..d38fc268229 100644
--- a/src/mesa/drivers/dri/i965/gen7_urb.c
+++ b/src/mesa/drivers/dri/i965/gen7_urb.c
@@ -320,7 +320,7 @@ gen7_upload_urb(struct brw_context *brw, unsigned vs_size,
DIV_ROUND_UP(devinfo->urb.min_ds_entries * ds_entry_size_bytes,
chunk_size_bytes);
ds_wants =
- DIV_ROUND_UP(devinfo->urb.max_ds_entries * ds_entry_size_bytes,
+ DIV_ROUND_UP(devinfo->urb.max_tes_entries * ds_entry_size_bytes,
chunk_size_bytes) - ds_chunks;
}
@@ -379,7 +379,7 @@ gen7_upload_urb(struct brw_context *brw, unsigned vs_size,
*/
nr_vs_entries = MIN2(nr_vs_entries, devinfo->urb.max_vs_entries);
nr_hs_entries = MIN2(nr_hs_entries, devinfo->urb.max_tcs_entries);
- nr_ds_entries = MIN2(nr_ds_entries, devinfo->urb.max_ds_entries);
+ nr_ds_entries = MIN2(nr_ds_entries, devinfo->urb.max_tes_entries);
nr_gs_entries = MIN2(nr_gs_entries, devinfo->urb.max_gs_entries);
/* Ensure that we program a multiple of the granularity. */
diff --git a/src/mesa/drivers/dri/i965/gen8_ds_state.c b/src/mesa/drivers/dri/i965/gen8_ds_state.c
index f7dbcec0480..c316d01dbb9 100644
--- a/src/mesa/drivers/dri/i965/gen8_ds_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_ds_state.c
@@ -65,7 +65,7 @@ gen8_upload_ds_state(struct brw_context *brw)
OUT_BATCH(GEN7_DS_ENABLE |
GEN7_DS_STATISTICS_ENABLE |
- (devinfo->max_ds_threads - 1) << HSW_DS_MAX_THREADS_SHIFT |
+ (devinfo->max_tes_threads - 1) << HSW_DS_MAX_THREADS_SHIFT |
(vue_prog_data->dispatch_mode == DISPATCH_MODE_SIMD8 ?
GEN7_DS_SIMD8_DISPATCH_ENABLE : 0) |
(tes_prog_data->domain == BRW_TESS_DOMAIN_TRI ?
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-20 01:42:38 +0000