diff options
-rw-r--r-- | src/intel/compiler/brw_eu.c | 8 | ||||
-rw-r--r-- | src/intel/compiler/brw_eu.h | 2 | ||||
-rw-r--r-- | src/intel/compiler/brw_eu_defines.h | 4 | ||||
-rw-r--r-- | src/intel/compiler/brw_eu_emit.c | 2 | ||||
-rw-r--r-- | src/intel/compiler/brw_fs_builder.h | 2 | ||||
-rw-r--r-- | src/intel/compiler/brw_fs_generator.cpp | 10 |
6 files changed, 26 insertions, 2 deletions
diff --git a/src/intel/compiler/brw_eu.c b/src/intel/compiler/brw_eu.c index 87a6145ac29..ec30579446b 100644 --- a/src/intel/compiler/brw_eu.c +++ b/src/intel/compiler/brw_eu.c @@ -488,7 +488,13 @@ static const struct opcode_desc opcode_descs[128] = { [BRW_OPCODE_ASR] = { .name = "asr", .nsrc = 2, .ndst = 1, .gens = GEN_ALL, }, - /* Reserved - 13-15 */ + /* Reserved - 13 */ + [BRW_OPCODE_ROR] = { + .name = "ror", .nsrc = 2, .ndst = 1, .gens = GEN_GE(GEN11), + }, + [BRW_OPCODE_ROL] = { + .name = "rol", .nsrc = 2, .ndst = 1, .gens = GEN_GE(GEN11), + }, [BRW_OPCODE_CMP] = { .name = "cmp", .nsrc = 2, .ndst = 1, .gens = GEN_ALL, }, diff --git a/src/intel/compiler/brw_eu.h b/src/intel/compiler/brw_eu.h index 29965e60a7f..dd504cc25fb 100644 --- a/src/intel/compiler/brw_eu.h +++ b/src/intel/compiler/brw_eu.h @@ -204,6 +204,8 @@ ALU2(SHR) ALU2(SHL) ALU1(DIM) ALU2(ASR) +ALU2(ROL) +ALU2(ROR) ALU3(CSEL) ALU1(F32TO16) ALU1(F16TO32) diff --git a/src/intel/compiler/brw_eu_defines.h b/src/intel/compiler/brw_eu_defines.h index 933037c4df3..e8ca7ff8b98 100644 --- a/src/intel/compiler/brw_eu_defines.h +++ b/src/intel/compiler/brw_eu_defines.h @@ -210,7 +210,9 @@ enum opcode { BRW_OPCODE_SMOV = 10, /**< Gen8+ */ /* Reused */ /* Reserved - 11 */ BRW_OPCODE_ASR = 12, - /* Reserved - 13-15 */ + /* Reserved - 13 */ + BRW_OPCODE_ROR = 14, /**< Gen11+ */ + BRW_OPCODE_ROL = 15, /**< Gen11+ */ BRW_OPCODE_CMP = 16, BRW_OPCODE_CMPN = 17, BRW_OPCODE_CSEL = 18, /**< Gen8+ */ diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c index 6cb4f7bdbf1..8e7263ce447 100644 --- a/src/intel/compiler/brw_eu_emit.c +++ b/src/intel/compiler/brw_eu_emit.c @@ -981,6 +981,8 @@ ALU2(SHR) ALU2(SHL) ALU1(DIM) ALU2(ASR) +ALU2(ROL) +ALU2(ROR) ALU3(CSEL) ALU1(FRC) ALU1(RNDD) diff --git a/src/intel/compiler/brw_fs_builder.h b/src/intel/compiler/brw_fs_builder.h index b781f1257ba..0c1b6f5d6c7 100644 --- a/src/intel/compiler/brw_fs_builder.h +++ b/src/intel/compiler/brw_fs_builder.h @@ -594,6 +594,8 @@ namespace brw { ALU1(RNDE) ALU1(RNDU) ALU1(RNDZ) + ALU2(ROL) + ALU2(ROR) ALU2(SAD2) ALU2_ACC(SADA2) ALU2(SEL) diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp index 14868baa009..d068d1a51c1 100644 --- a/src/intel/compiler/brw_fs_generator.cpp +++ b/src/intel/compiler/brw_fs_generator.cpp @@ -1796,6 +1796,16 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width) case BRW_OPCODE_SHL: brw_SHL(p, dst, src[0], src[1]); break; + case BRW_OPCODE_ROL: + assert(devinfo->gen >= 11); + assert(src[0].type == dst.type); + brw_ROL(p, dst, src[0], src[1]); + break; + case BRW_OPCODE_ROR: + assert(devinfo->gen >= 11); + assert(src[0].type == dst.type); + brw_ROR(p, dst, src[0], src[1]); + break; case BRW_OPCODE_F32TO16: assert(devinfo->gen >= 7); brw_F32TO16(p, dst, src[0]); |