diff options
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_hw_context.c | 36 | ||||
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_pipe.c | 3 | ||||
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_state_draw.c | 21 |
3 files changed, 25 insertions, 35 deletions
diff --git a/src/gallium/drivers/radeonsi/si_hw_context.c b/src/gallium/drivers/radeonsi/si_hw_context.c index eaefa6a40e9..e030c753d6c 100644 --- a/src/gallium/drivers/radeonsi/si_hw_context.c +++ b/src/gallium/drivers/radeonsi/si_hw_context.c @@ -102,20 +102,8 @@ void si_context_gfx_flush(void *context, unsigned flags, /* force to keep tiling flags */ flags |= RADEON_FLUSH_KEEP_TILING_FLAGS; -#if SI_TRACE_CS - if (ctx->screen->b.trace_bo) { - struct si_screen *sscreen = ctx->screen; - unsigned i; - - for (i = 0; i < cs->cdw; i++) { - fprintf(stderr, "[%4d] [%5d] 0x%08x\n", sscreen->b.cs_count, i, cs->buf[i]); - } - sscreen->b.cs_count++; - } -#endif - /* Flush the CS. */ - ctx->b.ws->cs_flush(cs, flags, fence, 0); + ctx->b.ws->cs_flush(cs, flags, fence, ctx->screen->b.cs_count++); ctx->b.rings.gfx.flushing = false; #if SI_TRACE_CS @@ -125,7 +113,7 @@ void si_context_gfx_flush(void *context, unsigned flags, for (i = 0; i < 10; i++) { usleep(5); - if (!ctx->ws->buffer_is_busy(sscreen->b.trace_bo->buf, RADEON_USAGE_READWRITE)) { + if (!ctx->b.ws->buffer_is_busy(sscreen->b.trace_bo->buf, RADEON_USAGE_READWRITE)) { break; } } @@ -169,23 +157,3 @@ void si_begin_new_cs(struct si_context *ctx) ctx->b.initial_gfx_cs_size = ctx->b.rings.gfx.cs->cdw; } - -#if SI_TRACE_CS -void si_trace_emit(struct si_context *sctx) -{ - struct si_screen *sscreen = sctx->screen; - struct radeon_winsys_cs *cs = sctx->cs; - uint64_t va; - - va = sscreen->b.trace_bo->gpu_address; - r600_context_bo_reloc(sctx, sscreen->b.trace_bo, RADEON_USAGE_READWRITE); - cs->buf[cs->cdw++] = PKT3(PKT3_WRITE_DATA, 4, 0); - cs->buf[cs->cdw++] = PKT3_WRITE_DATA_DST_SEL(PKT3_WRITE_DATA_DST_SEL_MEM_SYNC) | - PKT3_WRITE_DATA_WR_CONFIRM | - PKT3_WRITE_DATA_ENGINE_SEL(PKT3_WRITE_DATA_ENGINE_SEL_ME); - cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; - cs->buf[cs->cdw++] = (va >> 32UL) & 0xFFFFFFFFUL; - cs->buf[cs->cdw++] = cs->cdw; - cs->buf[cs->cdw++] = sscreen->b.cs_count; -} -#endif diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c index 2cce5cc28e4..cba6d98f29c 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.c +++ b/src/gallium/drivers/radeonsi/si_pipe.c @@ -94,7 +94,8 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen, void * } sctx->b.rings.gfx.cs = ws->cs_create(ws, RING_GFX, si_context_gfx_flush, - sctx, NULL); + sctx, sscreen->b.trace_bo ? + sscreen->b.trace_bo->cs_buf : NULL); sctx->b.rings.gfx.flush = si_context_gfx_flush; si_init_all_descriptors(sctx); diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c index 0888841f4a8..a47534429b8 100644 --- a/src/gallium/drivers/radeonsi/si_state_draw.c +++ b/src/gallium/drivers/radeonsi/si_state_draw.c @@ -1025,3 +1025,24 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info) pipe_resource_reference(&ib.buffer, NULL); sctx->b.num_draw_calls++; } + +#if SI_TRACE_CS +void si_trace_emit(struct si_context *sctx) +{ + struct si_screen *sscreen = sctx->screen; + struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs; + uint64_t va; + + va = sscreen->b.trace_bo->gpu_address; + r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, sscreen->b.trace_bo, + RADEON_USAGE_READWRITE, RADEON_PRIO_MIN); + radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 4, 0)); + radeon_emit(cs, PKT3_WRITE_DATA_DST_SEL(PKT3_WRITE_DATA_DST_SEL_MEM_SYNC) | + PKT3_WRITE_DATA_WR_CONFIRM | + PKT3_WRITE_DATA_ENGINE_SEL(PKT3_WRITE_DATA_ENGINE_SEL_ME)); + radeon_emit(cs, va & 0xFFFFFFFFUL); + radeon_emit(cs, (va >> 32UL) & 0xFFFFFFFFUL); + radeon_emit(cs, cs->cdw); + radeon_emit(cs, sscreen->b.cs_count); +} +#endif |