diff options
52 files changed, 14464 insertions, 0 deletions
diff --git a/src/gallium/drivers/r600/Makefile b/src/gallium/drivers/r600/Makefile new file mode 100644 index 00000000000..bc58575c789 --- /dev/null +++ b/src/gallium/drivers/r600/Makefile @@ -0,0 +1,26 @@ +TOP = ../../../.. +include $(TOP)/configs/current + +LIBNAME = r600 + +LIBRARY_INCLUDES = \ + $(shell pkg-config libdrm --cflags-only-I) + +C_SOURCES = \ + r600_buffer.c \ + r600_context.c \ + r600_draw.c \ + r600_blit.c \ + r600_helper.c \ + r600_query.c \ + r600_screen.c \ + r600_state.c \ + r600_texture.c \ + r600_shader.c \ + r600_compiler.c \ + r600_compiler_tgsi.c \ + r600_compiler_dump.c \ + r600_compiler_r600.c \ + r600_compiler_r700.c + +include ../../Makefile.template diff --git a/src/gallium/drivers/r600/SConscript b/src/gallium/drivers/r600/SConscript new file mode 100644 index 00000000000..a88c5452529 --- /dev/null +++ b/src/gallium/drivers/r600/SConscript @@ -0,0 +1,21 @@ +Import('*') + +env = env.Clone() +env.Append(CPPPATH = [ + '#/include', + '#/src/mesa', +]) + +r600 = env.ConvenienceLibrary( + target = 'r600', + source = [ + 'r600_buffer.c', + 'r600_context.c', + 'r600_draw.c', + 'r600_query.c', + 'r600_screen.c', + 'r600_state.c', + 'r600_texture.c', + ]) + +Export('r600') diff --git a/src/gallium/drivers/r600/r600_blit.c b/src/gallium/drivers/r600/r600_blit.c new file mode 100644 index 00000000000..88b865ef9a6 --- /dev/null +++ b/src/gallium/drivers/r600/r600_blit.c @@ -0,0 +1,81 @@ +/* + * Copyright 2009 Marek Olšák <[email protected]> + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Jerome Glisse + * Marek Olšák + */ +#include <pipe/p_screen.h> +#include <util/u_blitter.h> +#include <util/u_inlines.h> +#include <util/u_memory.h> +#include "r600_screen.h" +#include "r600_texture.h" +#include "r600_context.h" + +static void r600_blitter_save_states(struct pipe_context *ctx) +{ + struct r600_context *rctx = (struct r600_context*)ctx; + + util_blitter_save_blend(rctx->blitter, + rctx->draw->state[R600_BLEND]); + util_blitter_save_depth_stencil_alpha(rctx->blitter, + rctx->draw->state[R600_DSA]); + util_blitter_save_stencil_ref(rctx->blitter, &rctx->stencil_ref); + util_blitter_save_rasterizer(rctx->blitter, + rctx->draw->state[R600_RASTERIZER]); + util_blitter_save_fragment_shader(rctx->blitter, + rctx->ps_shader); + util_blitter_save_vertex_shader(rctx->blitter, + rctx->vs_shader); +} + +void r600_clear(struct pipe_context *ctx, unsigned buffers, + const float *rgba, double depth, unsigned stencil) +{ + struct r600_context *rctx = (struct r600_context*)ctx; + struct pipe_framebuffer_state *fb = &rctx->fb_state; + +#if 0 + r600_blitter_save_states(ctx); + util_blitter_clear(rctx->blitter, fb->width, fb->height, + fb->nr_cbufs, buffers, rgba, depth, + stencil); +#endif +} + +void r600_surface_copy(struct pipe_context *ctx, + struct pipe_surface *dst, + unsigned dstx, unsigned dsty, + struct pipe_surface *src, + unsigned srcx, unsigned srcy, + unsigned width, unsigned height) +{ +} + +void r600_surface_fill(struct pipe_context *ctx, + struct pipe_surface *dst, + unsigned dstx, unsigned dsty, + unsigned width, unsigned height, + unsigned value) +{ +} diff --git a/src/gallium/drivers/r600/r600_buffer.c b/src/gallium/drivers/r600/r600_buffer.c new file mode 100644 index 00000000000..f3a0208b003 --- /dev/null +++ b/src/gallium/drivers/r600/r600_buffer.c @@ -0,0 +1,177 @@ +/* + * Copyright 2010 Jerome Glisse <[email protected]> + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Jerome Glisse + * Corbin Simpson <[email protected]> + */ +#include <pipe/p_screen.h> +#include <util/u_format.h> +#include <util/u_math.h> +#include <util/u_inlines.h> +#include <util/u_memory.h> +#include "r600_screen.h" +#include "r600_texture.h" +#include "r600_context.h" + +static u32 r600_domain_from_usage(unsigned usage) +{ + u32 domain = RADEON_GEM_DOMAIN_GTT; + + if (usage & PIPE_BUFFER_USAGE_GPU_WRITE) { + domain |= RADEON_GEM_DOMAIN_VRAM; + } + if (usage & PIPE_BUFFER_USAGE_PIXEL) { + domain |= RADEON_GEM_DOMAIN_VRAM; + } + if (usage & PIPE_BUFFER_USAGE_VERTEX) { + domain |= RADEON_GEM_DOMAIN_GTT; + } + if (usage & PIPE_BUFFER_USAGE_INDEX) { + domain |= RADEON_GEM_DOMAIN_GTT; + } + return domain; +} + +static struct pipe_buffer *r600_buffer_create(struct pipe_screen *screen, + unsigned alignment, + unsigned usage, + unsigned size) +{ + struct r600_screen *rscreen = r600_screen(screen); + struct r600_pipe_buffer *rbuffer; + struct radeon_bo *bo; + struct pb_desc desc; + + rbuffer = CALLOC_STRUCT(r600_pipe_buffer); + if (rbuffer == NULL) + return NULL; + + pipe_reference_init(&rbuffer->base.reference, 1); + rbuffer->base.screen = screen; + rbuffer->base.alignment = alignment; + rbuffer->base.usage = usage; + rbuffer->base.size = size; + + if (usage & PIPE_BUFFER_USAGE_CONSTANT) { + desc.alignment = alignment; + desc.usage = usage; + rbuffer->pb = pb_malloc_buffer_create(size, &desc); + if (rbuffer->pb == NULL) { + free(rbuffer); + return NULL; + } + return &rbuffer->base; + } + rbuffer->domain = r600_domain_from_usage(usage); + bo = radeon_bo(rscreen->rw, 0, size, alignment, NULL); + if (bo == NULL) { + FREE(rbuffer); + return NULL; + } + rbuffer->bo = bo; + return &rbuffer->base; +} + +static struct pipe_buffer *r600_user_buffer_create(struct pipe_screen *screen, + void *ptr, unsigned bytes) +{ + struct r600_pipe_buffer *rbuffer; + struct r600_screen *rscreen = r600_screen(screen); + + rbuffer = (struct r600_pipe_buffer*)r600_buffer_create(screen, 0, 0, bytes); + if (rbuffer == NULL) { + return NULL; + } + radeon_bo_map(rscreen->rw, rbuffer->bo); + memcpy(rbuffer->bo->data, ptr, bytes); + radeon_bo_unmap(rscreen->rw, rbuffer->bo); + return &rbuffer->base; +} + +static void r600_buffer_destroy(struct pipe_buffer *buffer) +{ + struct r600_pipe_buffer *rbuffer = (struct r600_pipe_buffer*)buffer; + struct r600_screen *rscreen = r600_screen(buffer->screen); + + if (rbuffer->pb) { + pipe_reference_init(&rbuffer->pb->base.reference, 0); + pb_destroy(rbuffer->pb); + rbuffer->pb = NULL; + } + if (rbuffer->bo) { + radeon_bo_decref(rscreen->rw, rbuffer->bo); + } + FREE(rbuffer); +} + +static void *r600_buffer_map_range(struct pipe_screen *screen, + struct pipe_buffer *buffer, + unsigned offset, unsigned length, + unsigned usage) +{ + struct r600_pipe_buffer *rbuffer = (struct r600_pipe_buffer*)buffer; + struct r600_screen *rscreen = r600_screen(buffer->screen); + int write = 0; + + if (rbuffer->pb) { + return pb_map(rbuffer->pb, usage); + } + if (usage & PIPE_BUFFER_USAGE_DONTBLOCK) { + /* FIXME */ + } + if (usage & PIPE_BUFFER_USAGE_CPU_WRITE) { + write = 1; + } + if (radeon_bo_map(rscreen->rw, rbuffer->bo)) { + return NULL; + } + return rbuffer->bo->data; +} + +static void r600_buffer_unmap( struct pipe_screen *screen, struct pipe_buffer *buffer) +{ + struct r600_pipe_buffer *rbuffer = (struct r600_pipe_buffer*)buffer; + struct r600_screen *rscreen = r600_screen(buffer->screen); + + if (rbuffer->pb) { + pb_unmap(rbuffer->pb); + } else { + radeon_bo_unmap(rscreen->rw, rbuffer->bo); + } +} + +static void r600_buffer_flush_mapped_range(struct pipe_screen *screen, + struct pipe_buffer *buf, + unsigned offset, unsigned length) +{ +} + +void r600_screen_init_buffer_functions(struct pipe_screen *screen) +{ + screen->buffer_create = r600_buffer_create; + screen->user_buffer_create = r600_user_buffer_create; + screen->buffer_map_range = r600_buffer_map_range; + screen->buffer_flush_mapped_range = r600_buffer_flush_mapped_range; + screen->buffer_unmap = r600_buffer_unmap; + screen->buffer_destroy = r600_buffer_destroy; +} diff --git a/src/gallium/drivers/r600/r600_compiler.c b/src/gallium/drivers/r600/r600_compiler.c new file mode 100644 index 00000000000..f1be2bbdf4f --- /dev/null +++ b/src/gallium/drivers/r600/r600_compiler.c @@ -0,0 +1,446 @@ +/* + * Copyright 2010 Jerome Glisse <[email protected]> + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#include <stdlib.h> +#include <string.h> +#include <stdint.h> +#include <stdio.h> +#include <errno.h> +#include "r600_compiler.h" + +struct c_vector *c_vector_new(void) +{ + struct c_vector *v = calloc(1, sizeof(struct c_vector)); + + if (v == NULL) { + return NULL; + } + c_list_init(v); + return v; +} + +static unsigned c_opcode_is_alu(unsigned opcode) +{ + switch (opcode) { + case C_OPCODE_MOV: + case C_OPCODE_MUL: + case C_OPCODE_MAD: + case C_OPCODE_ARL: + case C_OPCODE_LIT: + case C_OPCODE_RCP: + case C_OPCODE_RSQ: + case C_OPCODE_EXP: + case C_OPCODE_LOG: + case C_OPCODE_ADD: + case C_OPCODE_DP3: + case C_OPCODE_DP4: + case C_OPCODE_DST: + case C_OPCODE_MIN: + case C_OPCODE_MAX: + case C_OPCODE_SLT: + case C_OPCODE_SGE: + case C_OPCODE_SUB: + case C_OPCODE_LRP: + case C_OPCODE_CND: + case C_OPCODE_DP2A: + case C_OPCODE_FRC: + case C_OPCODE_CLAMP: + case C_OPCODE_FLR: + case C_OPCODE_ROUND: + case C_OPCODE_EX2: + case C_OPCODE_LG2: + case C_OPCODE_POW: + case C_OPCODE_XPD: + case C_OPCODE_ABS: + case C_OPCODE_RCC: + case C_OPCODE_DPH: + case C_OPCODE_COS: + case C_OPCODE_DDX: + case C_OPCODE_DDY: + case C_OPCODE_PK2H: + case C_OPCODE_PK2US: + case C_OPCODE_PK4B: + case C_OPCODE_PK4UB: + case C_OPCODE_RFL: + case C_OPCODE_SEQ: + case C_OPCODE_SFL: + case C_OPCODE_SGT: + case C_OPCODE_SIN: + case C_OPCODE_SLE: + case C_OPCODE_SNE: + case C_OPCODE_STR: + case C_OPCODE_UP2H: + case C_OPCODE_UP2US: + case C_OPCODE_UP4B: + case C_OPCODE_UP4UB: + case C_OPCODE_X2D: + case C_OPCODE_ARA: + case C_OPCODE_ARR: + case C_OPCODE_BRA: + case C_OPCODE_SSG: + case C_OPCODE_CMP: + case C_OPCODE_SCS: + case C_OPCODE_NRM: + case C_OPCODE_DIV: + case C_OPCODE_DP2: + case C_OPCODE_CEIL: + case C_OPCODE_I2F: + case C_OPCODE_NOT: + case C_OPCODE_TRUNC: + case C_OPCODE_SHL: + case C_OPCODE_AND: + case C_OPCODE_OR: + case C_OPCODE_MOD: + case C_OPCODE_XOR: + case C_OPCODE_SAD: + case C_OPCODE_NRM4: + case C_OPCODE_F2I: + case C_OPCODE_IDIV: + case C_OPCODE_IMAX: + case C_OPCODE_IMIN: + case C_OPCODE_INEG: + case C_OPCODE_ISGE: + case C_OPCODE_ISHR: + case C_OPCODE_ISLT: + case C_OPCODE_F2U: + case C_OPCODE_U2F: + case C_OPCODE_UADD: + case C_OPCODE_UDIV: + case C_OPCODE_UMAD: + case C_OPCODE_UMAX: + case C_OPCODE_UMIN: + case C_OPCODE_UMOD: + case C_OPCODE_UMUL: + case C_OPCODE_USEQ: + case C_OPCODE_USGE: + case C_OPCODE_USHR: + case C_OPCODE_USLT: + case C_OPCODE_USNE: + return 1; + case C_OPCODE_END: + case C_OPCODE_VFETCH: + case C_OPCODE_KILP: + case C_OPCODE_CAL: + case C_OPCODE_RET: + case C_OPCODE_TXB: + case C_OPCODE_TXL: + case C_OPCODE_BRK: + case C_OPCODE_IF: + case C_OPCODE_BGNFOR: + case C_OPCODE_REP: + case C_OPCODE_ELSE: + case C_OPCODE_ENDIF: + case C_OPCODE_ENDFOR: + case C_OPCODE_ENDREP: + case C_OPCODE_PUSHA: + case C_OPCODE_POPA: + case C_OPCODE_TXF: + case C_OPCODE_TXQ: + case C_OPCODE_CONT: + case C_OPCODE_EMIT: + case C_OPCODE_ENDPRIM: + case C_OPCODE_BGNLOOP: + case C_OPCODE_BGNSUB: + case C_OPCODE_ENDLOOP: + case C_OPCODE_ENDSUB: + case C_OPCODE_NOP: + case C_OPCODE_CALLNZ: + case C_OPCODE_IFC: + case C_OPCODE_BREAKC: + case C_OPCODE_KIL: + case C_OPCODE_TEX: + case C_OPCODE_TXD: + case C_OPCODE_TXP: + case C_OPCODE_SWITCH: + case C_OPCODE_CASE: + case C_OPCODE_DEFAULT: + case C_OPCODE_ENDSWITCH: + default: + return 0; + } +} + + +/* NEW */ +void c_node_init(struct c_node *node) +{ + memset(node, 0, sizeof(struct c_node)); + c_list_init(&node->predecessors); + c_list_init(&node->successors); + c_list_init(&node->childs); + c_list_init(&node->insts); + node->parent = NULL; +} + +static struct c_node_link *c_node_link_new(struct c_node *node) +{ + struct c_node_link *link; + + link = calloc(1, sizeof(struct c_node_link)); + if (link == NULL) + return NULL; + c_list_init(link); + link->node = node; + return link; +} + +int c_node_cfg_link(struct c_node *predecessor, struct c_node *successor) +{ + struct c_node_link *pedge, *sedge; + + pedge = c_node_link_new(successor); + sedge = c_node_link_new(predecessor); + if (sedge == NULL || pedge == NULL) { + free(sedge); + free(pedge); + return -ENOMEM; + } + c_list_add_tail(pedge, &predecessor->successors); + c_list_add_tail(sedge, &successor->predecessors); + return 0; +} + +int c_node_add_new_instruction_head(struct c_node *node, struct c_instruction *instruction) +{ + struct c_instruction *inst = calloc(1, sizeof(struct c_instruction)); + + if (inst == NULL) + return -ENOMEM; + memcpy(inst, instruction, sizeof(struct c_instruction)); + c_list_add(inst, &node->insts); + return 0; +} + +int c_node_add_new_instruction(struct c_node *node, struct c_instruction *instruction) +{ + struct c_instruction *inst = calloc(1, sizeof(struct c_instruction)); + + if (inst == NULL) + return -ENOMEM; + memcpy(inst, instruction, sizeof(struct c_instruction)); + c_list_add_tail(inst, &node->insts); + return 0; +} + +struct c_node *c_shader_cfg_new_node_after(struct c_shader *shader, struct c_node *predecessor) +{ + struct c_node *node = calloc(1, sizeof(struct c_node)); + + if (node == NULL) + return NULL; + c_node_init(node); + if (c_node_cfg_link(predecessor, node)) { + free(node); + return NULL; + } + c_list_add_tail(node, &shader->nodes); + return node; +} + +int c_shader_init(struct c_shader *shader, unsigned type) +{ + unsigned i; + int r; + + shader->type = type; + for (i = 0; i < C_FILE_COUNT; i++) { + shader->files[i].nvectors = 0; + c_list_init(&shader->files[i].vectors); + } + c_list_init(&shader->nodes); + c_node_init(&shader->entry); + c_node_init(&shader->end); + shader->entry.opcode = C_OPCODE_ENTRY; + shader->end.opcode = C_OPCODE_END; + r = c_node_cfg_link(&shader->entry, &shader->end); + if (r) + return r; + return 0; +} + +struct c_vector *c_shader_vector_new(struct c_shader *shader, unsigned file, unsigned name, int sid) +{ + struct c_vector *v = calloc(1, sizeof(struct c_vector)); + int i; + + if (v == NULL) { + return NULL; + } + for (i = 0; i < 4; i++) { + v->channel[i] = calloc(1, sizeof(struct c_channel)); + if (v->channel[i] == NULL) + goto out_err; + v->channel[i]->vindex = i; + v->channel[i]->vector = v; + } + v->file = file; + v->name = name; + v->sid = sid; + shader->files[v->file].nvectors++; + v->id = shader->nvectors++; + c_list_add_tail(v, &shader->files[v->file].vectors); + return v; +out_err: + for (i = 0; i < 4; i++) { + free(v->channel[i]); + } + free(v); + return NULL; +} + +static void c_node_remove_link(struct c_node_link *head, struct c_node *node) +{ + struct c_node_link *link, *tmp; + + c_list_for_each_safe(link, tmp, head) { + if (link->node == node) { + c_list_del(link); + free(link); + } + } +} + +static void c_node_destroy(struct c_node *node) +{ + struct c_instruction *i, *ni; + struct c_node_link *link, *tmp; + + c_list_for_each_safe(i, ni, &node->insts) { + c_list_del(i); + free(i); + } + if (node->parent) + c_node_remove_link(&node->parent->childs, node); + node->parent = NULL; + c_list_for_each_safe(link, tmp, &node->predecessors) { + c_node_remove_link(&link->node->successors, node); + c_list_del(link); + free(link); + } + c_list_for_each_safe(link, tmp, &node->successors) { + c_node_remove_link(&link->node->predecessors, node); + c_list_del(link); + free(link); + } + c_list_for_each_safe(link, tmp, &node->childs) { + link->node->parent = NULL; + c_list_del(link); + free(link); + } +} + +void c_shader_destroy(struct c_shader *shader) +{ + struct c_node *n, *nn; + struct c_vector *v, *nv; + unsigned i; + + for (i = 0; i < C_FILE_COUNT; i++) { + shader->files[i].nvectors = 0; + c_list_for_each_safe(v, nv, &shader->files[i].vectors) { + c_list_del(v); + free(v->channel[0]); + free(v->channel[1]); + free(v->channel[2]); + free(v->channel[3]); + free(v); + } + } + c_list_for_each_safe(n, nn, &shader->nodes) { + c_list_del(n); + c_node_destroy(n); + } + memset(shader, 0, sizeof(struct c_shader)); +} + +static void c_shader_dfs_without_rec(struct c_node *entry, struct c_node *node) +{ + struct c_node_link *link; + + if (entry == node || entry->visited) + return; + entry->visited = 1; + c_list_for_each(link, &entry->successors) { + c_shader_dfs_without_rec(link->node, node); + } +} + +static void c_shader_dfs_without(struct c_shader *shader, struct c_node *node) +{ + struct c_node *n; + + shader->entry.visited = 0; + shader->end.visited = 0; + c_list_for_each(n, &shader->nodes) { + n->visited = 0; + } + c_shader_dfs_without_rec(&shader->entry, node); +} + +static int c_shader_build_dominator_tree_rec(struct c_shader *shader, struct c_node *node) +{ + struct c_node_link *link, *nlink; + unsigned found = 0; + int r; + + if (node->done) + return 0; + node->done = 1; + c_list_for_each(link, &node->predecessors) { + /* if we remove this predecessor can we reach the current node ? */ + c_shader_dfs_without(shader, link->node); + if (node->visited == 0) { + /* we were unable to visit current node thus current + * predecessor is the immediate dominator of node, as + * their can be only one immediate dominator we break + */ + node->parent = link->node; + nlink = c_node_link_new(node); + if (nlink == NULL) + return -ENOMEM; + c_list_add_tail(nlink, &link->node->childs); + found = 1; + break; + } + } + /* this shouldn't happen there should at least be 1 denominator for each node */ + if (!found && node->opcode != C_OPCODE_ENTRY) { + fprintf(stderr, "invalid flow control graph node %p (%d) has no immediate dominator\n", + node, node->opcode); + return -EINVAL; + } + c_list_for_each(link, &node->predecessors) { + r = c_shader_build_dominator_tree_rec(shader, link->node); + if (r) + return r; + } + return 0; +} + +int c_shader_build_dominator_tree(struct c_shader *shader) +{ + struct c_node *node; + c_list_for_each(node, &shader->nodes) { + node->done = 0; + } + return c_shader_build_dominator_tree_rec(shader, &shader->end); +} diff --git a/src/gallium/drivers/r600/r600_compiler.h b/src/gallium/drivers/r600/r600_compiler.h new file mode 100644 index 00000000000..d3c13b519be --- /dev/null +++ b/src/gallium/drivers/r600/r600_compiler.h @@ -0,0 +1,329 @@ +/* + * Copyright 2010 Jerome Glisse <[email protected]> + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef R600_COMPILER_H +#define R600_COMPILER_H + +struct c_vector; + +/* operand are the basic source/destination of each operation */ +struct c_channel { + struct c_channel *next; + struct c_channel *prev; + unsigned vindex; /**< index in vector X,Y,Z,W (0,1,2,3) */ + unsigned value; /**< immediate value 32bits */ + struct c_vector *vector; /**< vector to which it belongs */ +}; + +/* in GPU world most of the time operand are grouped into vector + * of 4 component this structure is mostly and handler to group + * operand into a same vector + */ +struct c_vector { + struct c_vector *next; + struct c_vector *prev; + unsigned id; /**< vector uniq id */ + unsigned name; /**< semantic name */ + unsigned file; /**< operand file C_FILE_* */ + int sid; /**< semantic id */ + struct c_channel *channel[4]; /**< operands */ +}; + +#define c_list_init(e) do { (e)->next = e; (e)->prev = e; } while(0) +#define c_list_add(e, h) do { (e)->next = (h)->next; (e)->prev = h; (h)->next = e; (e)->next->prev = e; } while(0) +#define c_list_add_tail(e, h) do { (e)->next = h; (e)->prev = (h)->prev; (h)->prev = e; (e)->prev->next = e; } while(0) +#define c_list_del(e) do { (e)->next->prev = (e)->prev; (e)->prev->next = (e)->next; c_list_init(e); } while(0) +#define c_list_for_each(p, h) for (p = (h)->next; p != (h); p = p->next) +#define c_list_for_each_from(p, s, h) for (p = s; p != (h); p = p->next) +#define c_list_for_each_safe(p, n, h) for (p = (h)->next, n = p->next; p != (h); p = n, n = p->next) +#define c_list_empty(h) ((h)->next == h) + + +#define C_PROGRAM_TYPE_VS 0 +#define C_PROGRAM_TYPE_FS 1 +#define C_PROGRAM_TYPE_COUNT 2 + +#define C_NODE_FLAG_ALU 1 +#define C_NODE_FLAG_FETCH 2 + +#define C_SWIZZLE_X 0 +#define C_SWIZZLE_Y 1 +#define C_SWIZZLE_Z 2 +#define C_SWIZZLE_W 3 +#define C_SWIZZLE_0 4 +#define C_SWIZZLE_1 5 +#define C_SWIZZLE_D 6 /**< discard */ + +#define C_FILE_NULL 0 +#define C_FILE_CONSTANT 1 +#define C_FILE_INPUT 2 +#define C_FILE_OUTPUT 3 +#define C_FILE_TEMPORARY 4 +#define C_FILE_SAMPLER 5 +#define C_FILE_ADDRESS 6 +#define C_FILE_IMMEDIATE 7 +#define C_FILE_LOOP 8 +#define C_FILE_PREDICATE 9 +#define C_FILE_SYSTEM_VALUE 10 +#define C_FILE_RESOURCE 11 +#define C_FILE_COUNT 12 + +#define C_SEMANTIC_POSITION 0 +#define C_SEMANTIC_COLOR 1 +#define C_SEMANTIC_BCOLOR 2 /**< back-face color */ +#define C_SEMANTIC_FOG 3 +#define C_SEMANTIC_PSIZE 4 +#define C_SEMANTIC_GENERIC 5 +#define C_SEMANTIC_NORMAL 6 +#define C_SEMANTIC_FACE 7 +#define C_SEMANTIC_EDGEFLAG 8 +#define C_SEMANTIC_PRIMID 9 +#define C_SEMANTIC_INSTANCEID 10 +#define C_SEMANTIC_VERTEXID 11 +#define C_SEMANTIC_COUNT 12 /**< number of semantic values */ + +#define C_OPCODE_ARL 0 +#define C_OPCODE_MOV 1 +#define C_OPCODE_LIT 2 +#define C_OPCODE_RCP 3 +#define C_OPCODE_RSQ 4 +#define C_OPCODE_EXP 5 +#define C_OPCODE_LOG 6 +#define C_OPCODE_MUL 7 +#define C_OPCODE_ADD 8 +#define C_OPCODE_DP3 9 +#define C_OPCODE_DP4 10 +#define C_OPCODE_DST 11 +#define C_OPCODE_MIN 12 +#define C_OPCODE_MAX 13 +#define C_OPCODE_SLT 14 +#define C_OPCODE_SGE 15 +#define C_OPCODE_MAD 16 +#define C_OPCODE_SUB 17 +#define C_OPCODE_LRP 18 +#define C_OPCODE_CND 19 +/* gap */ +#define C_OPCODE_DP2A 21 +/* gap */ +#define C_OPCODE_FRC 24 +#define C_OPCODE_CLAMP 25 +#define C_OPCODE_FLR 26 +#define C_OPCODE_ROUND 27 +#define C_OPCODE_EX2 28 +#define C_OPCODE_LG2 29 +#define C_OPCODE_POW 30 +#define C_OPCODE_XPD 31 +/* gap */ +#define C_OPCODE_ABS 33 +#define C_OPCODE_RCC 34 +#define C_OPCODE_DPH 35 +#define C_OPCODE_COS 36 +#define C_OPCODE_DDX 37 +#define C_OPCODE_DDY 38 +#define C_OPCODE_KILP 39 /* predicated kill */ +#define C_OPCODE_PK2H 40 +#define C_OPCODE_PK2US 41 +#define C_OPCODE_PK4B 42 +#define C_OPCODE_PK4UB 43 +#define C_OPCODE_RFL 44 +#define C_OPCODE_SEQ 45 +#define C_OPCODE_SFL 46 +#define C_OPCODE_SGT 47 +#define C_OPCODE_SIN 48 +#define C_OPCODE_SLE 49 +#define C_OPCODE_SNE 50 +#define C_OPCODE_STR 51 +#define C_OPCODE_TEX 52 +#define C_OPCODE_TXD 53 +#define C_OPCODE_TXP 54 +#define C_OPCODE_UP2H 55 +#define C_OPCODE_UP2US 56 +#define C_OPCODE_UP4B 57 +#define C_OPCODE_UP4UB 58 +#define C_OPCODE_X2D 59 +#define C_OPCODE_ARA 60 +#define C_OPCODE_ARR 61 +#define C_OPCODE_BRA 62 +#define C_OPCODE_CAL 63 +#define C_OPCODE_RET 64 +#define C_OPCODE_SSG 65 /* SGN */ +#define C_OPCODE_CMP 66 +#define C_OPCODE_SCS 67 +#define C_OPCODE_TXB 68 +#define C_OPCODE_NRM 69 +#define C_OPCODE_DIV 70 +#define C_OPCODE_DP2 71 +#define C_OPCODE_TXL 72 +#define C_OPCODE_BRK 73 +#define C_OPCODE_IF 74 +#define C_OPCODE_BGNFOR 75 +#define C_OPCODE_REP 76 +#define C_OPCODE_ELSE 77 +#define C_OPCODE_ENDIF 78 +#define C_OPCODE_ENDFOR 79 +#define C_OPCODE_ENDREP 80 +#define C_OPCODE_PUSHA 81 +#define C_OPCODE_POPA 82 +#define C_OPCODE_CEIL 83 +#define C_OPCODE_I2F 84 +#define C_OPCODE_NOT 85 +#define C_OPCODE_TRUNC 86 +#define C_OPCODE_SHL 87 +/* gap */ +#define C_OPCODE_AND 89 +#define C_OPCODE_OR 90 +#define C_OPCODE_MOD 91 +#define C_OPCODE_XOR 92 +#define C_OPCODE_SAD 93 +#define C_OPCODE_TXF 94 +#define C_OPCODE_TXQ 95 +#define C_OPCODE_CONT 96 +#define C_OPCODE_EMIT 97 +#define C_OPCODE_ENDPRIM 98 +#define C_OPCODE_BGNLOOP 99 +#define C_OPCODE_BGNSUB 100 +#define C_OPCODE_ENDLOOP 101 +#define C_OPCODE_ENDSUB 102 +/* gap */ +#define C_OPCODE_NOP 107 +/* gap */ +#define C_OPCODE_NRM4 112 +#define C_OPCODE_CALLNZ 113 +#define C_OPCODE_IFC 114 +#define C_OPCODE_BREAKC 115 +#define C_OPCODE_KIL 116 /* conditional kill */ +#define C_OPCODE_END 117 /* aka HALT */ +/* gap */ +#define C_OPCODE_F2I 119 +#define C_OPCODE_IDIV 120 +#define C_OPCODE_IMAX 121 +#define C_OPCODE_IMIN 122 +#define C_OPCODE_INEG 123 +#define C_OPCODE_ISGE 124 +#define C_OPCODE_ISHR 125 +#define C_OPCODE_ISLT 126 +#define C_OPCODE_F2U 127 +#define C_OPCODE_U2F 128 +#define C_OPCODE_UADD 129 +#define C_OPCODE_UDIV 130 +#define C_OPCODE_UMAD 131 +#define C_OPCODE_UMAX 132 +#define C_OPCODE_UMIN 133 +#define C_OPCODE_UMOD 134 +#define C_OPCODE_UMUL 135 +#define C_OPCODE_USEQ 136 +#define C_OPCODE_USGE 137 +#define C_OPCODE_USHR 138 +#define C_OPCODE_USLT 139 +#define C_OPCODE_USNE 140 +#define C_OPCODE_SWITCH 141 +#define C_OPCODE_CASE 142 +#define C_OPCODE_DEFAULT 143 +#define C_OPCODE_ENDSWITCH 144 +#define C_OPCODE_VFETCH 145 +#define C_OPCODE_ENTRY 146 +#define C_OPCODE_LAST 147 + +#define C_OPERAND_FLAG_ABS (1 << 0) +#define C_OPERAND_FLAG_NEG (1 << 1) + +struct c_operand { + struct c_vector *vector; + unsigned swizzle[4]; + unsigned flag[4]; +}; + +struct c_instruction { + struct c_instruction *next, *prev; + unsigned opcode; + unsigned ninput; + struct c_operand input[3]; + struct c_operand output; + unsigned write_mask; + void *backend; +}; + +struct c_node; + +struct c_node_link { + struct c_node_link *next; + struct c_node_link *prev; + struct c_node *node; +}; + +/** + * struct c_node + * + * @next: all node are in a double linked list, this point to + * next node + * @next: all node are in a double linked list, this point to + * previous node + * @predecessors: list of all predecessor nodes in the flow graph + * @successors: list of all sucessor nodes in the flow graph + * @parent: parent node in the depth first walk tree + * @childs: child nodes in the depth first walk tree + */ +struct c_node { + struct c_node *next, *prev; + struct c_node_link predecessors; + struct c_node_link successors; + struct c_node *parent; + struct c_node_link childs; + struct c_instruction insts; + unsigned opcode; + unsigned visited; + unsigned done; + void *backend; +}; + +struct c_file { + unsigned nvectors; + struct c_vector vectors; +}; + +struct c_shader { + unsigned nvectors; + struct c_file files[C_FILE_COUNT]; + struct c_node nodes; + struct c_node entry; + struct c_node end; + unsigned type; +}; + +int c_shader_init(struct c_shader *shader, unsigned type); +void c_shader_destroy(struct c_shader *shader); +struct c_vector *c_shader_vector_new(struct c_shader *shader, unsigned file, unsigned name, int sid); +int c_shader_build_dominator_tree(struct c_shader *shader); +void c_shader_dump(struct c_shader *shader); + +void c_node_init(struct c_node *node); +int c_node_add_new_instruction(struct c_node *node, struct c_instruction *instruction); +int c_node_add_new_instruction_head(struct c_node *node, struct c_instruction *instruction); + +/* control flow graph functions */ +int c_node_cfg_link(struct c_node *predecessor, struct c_node *successor); +struct c_node *c_node_cfg_new_after(struct c_node *predecessor); +struct c_node *c_shader_cfg_new_node_after(struct c_shader *shader, struct c_node *predecessor); + +struct c_vector *c_vector_new(void); + +#endif diff --git a/src/gallium/drivers/r600/r600_compiler_dump.c b/src/gallium/drivers/r600/r600_compiler_dump.c new file mode 100644 index 00000000000..9df6a38598e --- /dev/null +++ b/src/gallium/drivers/r600/r600_compiler_dump.c @@ -0,0 +1,270 @@ +/* + * Copyright 2010 Jerome Glisse <[email protected]> + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#include <stdlib.h> +#include <string.h> +#include <stdint.h> +#include <stdio.h> +#include "r600_compiler.h" + +static const char *c_file_swz[] = { + "x", + "y", + "z", + "w", + "0", + "1", + ".", +}; + +static const char *c_file_str[] = { + "NULL", + "CONSTANT", + "INPUT", + "OUTPUT", + "TEMPORARY", + "SAMPLER", + "ADDRESS", + "IMMEDIATE", + "LOOP", + "PREDICATE", + "SYSTEM_VALUE", +}; + +static const char *c_semantic_str[] = { + "POSITION", + "COLOR", + "BCOLOR", + "FOG", + "PSIZE", + "GENERIC", + "NORMAL", + "FACE", + "EDGEFLAG", + "PRIMID", + "INSTANCEID", +}; + +static const char *c_opcode_str[] = { + "ARL", + "MOV", + "LIT", + "RCP", + "RSQ", + "EXP", + "LOG", + "MUL", + "ADD", + "DP3", + "DP4", + "DST", + "MIN", + "MAX", + "SLT", + "SGE", + "MAD", + "SUB", + "LRP", + "CND", + "(INVALID)", + "DP2A", + "(INVALID)", + "(INVALID)", + "FRC", + "CLAMP", + "FLR", + "ROUND", + "EX2", + "LG2", + "POW", + "XPD", + "(INVALID)", + "ABS", + "RCC", + "DPH", + "COS", + "DDX", + "DDY", + "KILP", + "PK2H", + "PK2US", + "PK4B", + "PK4UB", + "RFL", + "SEQ", + "SFL", + "SGT", + "SIN", + "SLE", + "SNE", + "STR", + "TEX", + "TXD", + "TXP", + "UP2H", + "UP2US", + "UP4B", + "UP4UB", + "X2D", + "ARA", + "ARR", + "BRA", + "CAL", + "RET", + "SSG", + "CMP", + "SCS", + "TXB", + "NRM", + "DIV", + "DP2", + "TXL", + "BRK", + "IF", + "BGNFOR", + "REP", + "ELSE", + "ENDIF", + "ENDFOR", + "ENDREP", + "PUSHA", + "POPA", + "CEIL", + "I2F", + "NOT", + "TRUNC", + "SHL", + "(INVALID)", + "AND", + "OR", + "MOD", + "XOR", + "SAD", + "TXF", + "TXQ", + "CONT", + "EMIT", + "ENDPRIM", + "BGNLOOP", + "BGNSUB", + "ENDLOOP", + "ENDSUB", + "(INVALID)", + "(INVALID)", + "(INVALID)", + "(INVALID)", + "NOP", + "(INVALID)", + "(INVALID)", + "(INVALID)", + "(INVALID)", + "NRM4", + "CALLNZ", + "IFC", + "BREAKC", + "KIL", + "END", + "(INVALID)", + "F2I", + "IDIV", + "IMAX", + "IMIN", + "INEG", + "ISGE", + "ISHR", + "ISLT", + "F2U", + "U2F", + "UADD", + "UDIV", + "UMAD", + "UMAX", + "UMIN", + "UMOD", + "UMUL", + "USEQ", + "USGE", + "USHR", + "USLT", + "USNE", + "SWITCH", + "CASE", + "DEFAULT", + "ENDSWITCH", + "VFETCH", + "ENTRY", +}; + +static inline const char *c_get_name(const char *name[], unsigned i) +{ + return name[i]; +} + +static void pindent(unsigned indent) +{ + unsigned i; + for (i = 0; i < indent; i++) + fprintf(stderr, " "); +} + +static void c_node_dump(struct c_node *node, unsigned indent) +{ + struct c_instruction *i; + unsigned j; + + pindent(indent); fprintf(stderr, "# node %s\n", c_get_name(c_opcode_str, node->opcode)); + c_list_for_each(i, &node->insts) { + pindent(indent); fprintf(stderr, "%s", c_get_name(c_opcode_str, i->opcode)); + fprintf(stderr, " %s[%d][%s%s%s%s]", + c_get_name(c_file_str, i->output.vector->file), + i->output.vector->id, + c_get_name(c_file_swz, i->output.swizzle[0]), + c_get_name(c_file_swz, i->output.swizzle[1]), + c_get_name(c_file_swz, i->output.swizzle[2]), + c_get_name(c_file_swz, i->output.swizzle[3])); + for (j = 0; j < i->ninput; j++) { + fprintf(stderr, " %s[%d][%s%s%s%s]", + c_get_name(c_file_str, i->input[j].vector->file), + i->input[j].vector->id, + c_get_name(c_file_swz, i->input[j].swizzle[0]), + c_get_name(c_file_swz, i->input[j].swizzle[1]), + c_get_name(c_file_swz, i->input[j].swizzle[2]), + c_get_name(c_file_swz, i->input[j].swizzle[3])); + } + fprintf(stderr, ";\n"); + } +} + +static void c_shader_dump_rec(struct c_shader *shader, struct c_node *node, unsigned indent) +{ + struct c_node_link *link; + + c_node_dump(node, indent); + c_list_for_each(link, &node->childs) { + c_shader_dump_rec(shader, link->node, indent + 1); + } +} + +void c_shader_dump(struct c_shader *shader) +{ + c_shader_dump_rec(shader, &shader->entry, 0); +} diff --git a/src/gallium/drivers/r600/r600_compiler_r600.c b/src/gallium/drivers/r600/r600_compiler_r600.c new file mode 100644 index 00000000000..bed2b72f247 --- /dev/null +++ b/src/gallium/drivers/r600/r600_compiler_r600.c @@ -0,0 +1,763 @@ +/* + * Copyright 2010 Jerome Glisse <[email protected]> + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#include <stdlib.h> +#include <string.h> +#include <stdint.h> +#include <stdio.h> +#include <errno.h> +#include <util/u_format.h> +#include "r600_context.h" +#include "r600_sq.h" + + +struct r600_shader_alu_translate { + unsigned copcode; + unsigned opcode; + unsigned is_op3; +}; + +static int r600_shader_alu_translate(struct r600_shader *rshader, + struct c_instruction *instruction); +struct r600_shader_alu_translate r600_alu_translate_list[C_OPCODE_LAST]; + +int r600_shader_insert_fetch(struct c_shader *shader) +{ + struct c_vector *vi, *vr, *v, *nv; + struct c_instruction instruction; + int r; + + if (shader->type != C_PROGRAM_TYPE_VS) + return 0; + vi = c_shader_vector_new(shader, C_FILE_INPUT, C_SEMANTIC_VERTEXID, -1); + if (vi == NULL) + return -ENOMEM; + c_list_for_each_safe(v, nv, &shader->files[C_FILE_INPUT].vectors) { + if (v == vi) + continue; + vr = c_shader_vector_new(shader, C_FILE_RESOURCE, C_SEMANTIC_GENERIC, -1); + if (vr == NULL) + return -ENOMEM; + memset(&instruction, 0, sizeof(struct c_instruction)); + instruction.opcode = C_OPCODE_VFETCH; + instruction.write_mask = 0xF; + instruction.ninput = 2; + instruction.output.vector = v; + instruction.input[0].vector = vi; + instruction.input[1].vector = vr; + instruction.output.swizzle[0] = C_SWIZZLE_X; + instruction.output.swizzle[1] = C_SWIZZLE_Y; + instruction.output.swizzle[2] = C_SWIZZLE_Z; + instruction.output.swizzle[3] = C_SWIZZLE_W; + r = c_node_add_new_instruction_head(&shader->entry, &instruction); + if (r) + return r; + c_list_del(v); + shader->files[C_FILE_INPUT].nvectors--; + c_list_add_tail(v, &shader->files[C_FILE_TEMPORARY].vectors); + shader->files[C_FILE_TEMPORARY].nvectors++; + v->file = C_FILE_TEMPORARY; + } + return 0; +} + +void r600_shader_cleanup(struct r600_shader *rshader) +{ + struct r600_shader_node *n, *nn; + struct r600_shader_vfetch *vf, *nvf; + struct r600_shader_alu *alu, *nalu; + int i; + + if (rshader == NULL) + return; + if (rshader->gpr) { + for (i = 0; i < rshader->nvector; i++) { + free(rshader->gpr[i]); + } + free(rshader->gpr); + rshader->gpr = NULL; + } + c_list_for_each_safe(n, nn, &rshader->nodes) { + c_list_del(n); + c_list_for_each_safe(vf, nvf, &n->vfetch) { + c_list_del(vf); + free(vf); + } + c_list_for_each_safe(alu, nalu, &n->alu) { + c_list_del(alu); + free(alu); + } + free(n); + } + free(rshader->bcode); + return; +} + +int r600_shader_vfetch_bytecode(struct r600_shader *rshader, + struct r600_shader_node *rnode, + struct r600_shader_vfetch *vfetch, + unsigned *cid) +{ + unsigned id = *cid; + + vfetch->cf_addr = id; + rshader->bcode[id++] = S_SQ_VTX_WORD0_BUFFER_ID(vfetch->sel[2]) | + S_SQ_VTX_WORD0_SRC_GPR(vfetch->sel[1]) | + S_SQ_VTX_WORD0_SRC_SEL_X(vfetch->chan[1]) | + S_SQ_VTX_WORD0_MEGA_FETCH_COUNT(0x1F); + rshader->bcode[id++] = S_SQ_VTX_WORD1_DST_SEL_X(vfetch->dsel[0]) | + S_SQ_VTX_WORD1_DST_SEL_Y(vfetch->dsel[1]) | + S_SQ_VTX_WORD1_DST_SEL_Z(vfetch->dsel[2]) | + S_SQ_VTX_WORD1_DST_SEL_W(vfetch->dsel[3]) | + S_SQ_VTX_WORD1_USE_CONST_FIELDS(1) | + S_SQ_VTX_WORD1_GPR_DST_GPR(vfetch->sel[0]); + rshader->bcode[id++] = S_SQ_VTX_WORD2_MEGA_FETCH(1); + rshader->bcode[id++] = 0; + *cid = id; + return 0; +} + +int r600_shader_update(struct r600_shader *rshader, enum pipe_format *resource_format) +{ + struct r600_shader_node *rnode; + struct r600_shader_vfetch *vfetch; + unsigned i; + + memcpy(rshader->resource_format, resource_format, + rshader->nresource * sizeof(enum pipe_format)); + c_list_for_each(rnode, &rshader->nodes) { + c_list_for_each(vfetch, &rnode->vfetch) { + const struct util_format_description *desc; + i = vfetch->cf_addr + 1; + rshader->bcode[i] &= C_SQ_VTX_WORD1_DST_SEL_X; + rshader->bcode[i] &= C_SQ_VTX_WORD1_DST_SEL_Y; + rshader->bcode[i] &= C_SQ_VTX_WORD1_DST_SEL_Z; + rshader->bcode[i] &= C_SQ_VTX_WORD1_DST_SEL_W; + desc = util_format_description(resource_format[vfetch->sel[2]]); + if (desc == NULL) { + fprintf(stderr, "%s unknown format %d\n", __func__, resource_format[vfetch->sel[2]]); + continue; + } + /* WARNING so far TGSI swizzle match R600 ones */ + rshader->bcode[i] |= S_SQ_VTX_WORD1_DST_SEL_X(desc->swizzle[0]); + rshader->bcode[i] |= S_SQ_VTX_WORD1_DST_SEL_Y(desc->swizzle[1]); + rshader->bcode[i] |= S_SQ_VTX_WORD1_DST_SEL_Z(desc->swizzle[2]); + rshader->bcode[i] |= S_SQ_VTX_WORD1_DST_SEL_W(desc->swizzle[3]); + } + } + return 0; +} + +int r600_shader_register(struct r600_shader *rshader) +{ + struct c_vector *v, *nv; + unsigned tid, cid, rid, i; + + rshader->nvector = rshader->cshader.nvectors; + rshader->gpr = calloc(rshader->nvector, sizeof(void*)); + if (rshader->gpr == NULL) + return -ENOMEM; + tid = 0; + cid = 0; + rid = 0; + /* alloc input first */ + c_list_for_each(v, &rshader->cshader.files[C_FILE_INPUT].vectors) { + nv = c_vector_new(); + if (nv == NULL) { + return -ENOMEM; + } + memcpy(nv, v, sizeof(struct c_vector)); + nv->id = tid++; + rshader->gpr[v->id] = nv; + } + for (i = 0; i < C_FILE_COUNT; i++) { + if (i == C_FILE_INPUT || i == C_FILE_IMMEDIATE) + continue; + c_list_for_each(v, &rshader->cshader.files[i].vectors) { + switch (v->file) { + case C_FILE_OUTPUT: + case C_FILE_TEMPORARY: + nv = c_vector_new(); + if (nv == NULL) { + return -ENOMEM; + } + memcpy(nv, v, sizeof(struct c_vector)); + nv->id = tid++; + rshader->gpr[v->id] = nv; + break; + case C_FILE_CONSTANT: + nv = c_vector_new(); + if (nv == NULL) { + return -ENOMEM; + } + memcpy(nv, v, sizeof(struct c_vector)); + nv->id = (cid++) + 256; + rshader->gpr[v->id] = nv; + break; + case C_FILE_RESOURCE: + nv = c_vector_new(); + if (nv == NULL) { + return -ENOMEM; + } + memcpy(nv, v, sizeof(struct c_vector)); + nv->id = (rid++); + rshader->gpr[v->id] = nv; + break; + default: + fprintf(stderr, "%s:%d unsupported file %d\n", __func__, __LINE__, v->file); + return -EINVAL; + } + } + } + rshader->ngpr = tid; + rshader->nconstant = cid; + rshader->nresource = rid; + return 0; +} + +int r600_shader_find_gpr(struct r600_shader *rshader, struct c_vector *v, + unsigned swizzle, unsigned *sel, unsigned *chan) +{ + struct c_vector *tmp; + + /* Values [0,127] correspond to GPR[0..127]. + * Values [256,511] correspond to cfile constants c[0..255]. + * Other special values are shown in the list below. + * 248 SQ_ALU_SRC_0: special constant 0.0. + * 249 SQ_ALU_SRC_1: special constant 1.0 float. + * 250 SQ_ALU_SRC_1_INT: special constant 1 integer. + * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer. + * 252 SQ_ALU_SRC_0_5: special constant 0.5 float. + * 253 SQ_ALU_SRC_LITERAL: literal constant. + * 254 SQ_ALU_SRC_PV: previous vector result. + * 255 SQ_ALU_SRC_PS: previous scalar result. + */ + *sel = 248; + *chan = 0; + if (v == NULL) + return 0; + if (v->file == C_FILE_IMMEDIATE) { + *sel = 253; + } else { + tmp = rshader->gpr[v->id]; + if (tmp == NULL) { + fprintf(stderr, "%s %d unknown register\n", __FILE__, __LINE__); + return -EINVAL; + } + *sel = tmp->id; + } + *chan = swizzle; + switch (swizzle) { + case C_SWIZZLE_X: + case C_SWIZZLE_Y: + case C_SWIZZLE_Z: + case C_SWIZZLE_W: + break; + case C_SWIZZLE_0: + *sel = 248; + *chan = 0; + break; + case C_SWIZZLE_1: + *sel = 249; + *chan = 0; + break; + default: + fprintf(stderr, "%s %d invalid swizzle %d\n", __FILE__, __LINE__, swizzle); + return -EINVAL; + } + return 0; +} + +static int r600_shader_new_node(struct r600_shader *rshader, struct c_node *node) +{ + struct r600_shader_node *rnode; + rnode = CALLOC_STRUCT(r600_shader_node); + if (rnode == NULL) + return -ENOMEM; + rnode->node = node; + c_list_init(&rnode->vfetch); + c_list_init(&rnode->alu); + c_list_add_tail(rnode, &rshader->nodes); + rshader->cur_node = rnode; + return 0; +} + +static int r600_shader_new_alu(struct r600_shader *rshader, struct r600_shader_alu *alu) +{ + struct r600_shader_alu *nalu; + + nalu = CALLOC_STRUCT(r600_shader_alu); + if (nalu == NULL) + return -ENOMEM; + memcpy(nalu, alu, sizeof(struct r600_shader_alu)); + c_list_add_tail(nalu, &rshader->cur_node->alu); + return 0; +} + +static int r600_shader_add_vfetch(struct r600_shader *rshader, + struct c_instruction *instruction) +{ + struct r600_shader_vfetch *vfetch; + int r; + + if (instruction == NULL) + return 0; + if (instruction->opcode != C_OPCODE_VFETCH) + return 0; + if (!c_list_empty(&rshader->cur_node->alu)) { + r = r600_shader_new_node(rshader, rshader->cur_node->node); + if (r) + return r; + } + vfetch = calloc(1, sizeof(struct r600_shader_vfetch)); + if (vfetch == NULL) + return -ENOMEM; + r = r600_shader_find_gpr(rshader, instruction->output.vector, 0, &vfetch->sel[0], &vfetch->chan[0]); + if (r) + return r; + r = r600_shader_find_gpr(rshader, instruction->input[0].vector, 0, &vfetch->sel[1], &vfetch->chan[1]); + if (r) + return r; + r = r600_shader_find_gpr(rshader, instruction->input[1].vector, 0, &vfetch->sel[2], &vfetch->chan[2]); + if (r) + return r; + vfetch->dsel[0] = C_SWIZZLE_X; + vfetch->dsel[1] = C_SWIZZLE_Y; + vfetch->dsel[2] = C_SWIZZLE_Z; + vfetch->dsel[3] = C_SWIZZLE_W; + c_list_add_tail(vfetch, &rshader->cur_node->vfetch); + rshader->cur_node->nslot += 2; + return 0; +} + +static int r600_node_translate(struct r600_shader *rshader, struct c_node *node) +{ + struct c_instruction *instruction; + int r; + + r = r600_shader_new_node(rshader, node); + if (r) + return r; + c_list_for_each(instruction, &node->insts) { + switch (instruction->opcode) { + case C_OPCODE_VFETCH: + r = r600_shader_add_vfetch(rshader, instruction); + if (r) + return r; + break; + default: + r = r600_shader_alu_translate(rshader, instruction); + if (r) + return r; + break; + } + } + return 0; +} + +int r600_shader_translate_rec(struct r600_shader *rshader, struct c_node *node) +{ + struct c_node_link *link; + int r; + + if (node->opcode == C_OPCODE_END) + return 0; + r = r600_node_translate(rshader, node); + if (r) + return r; + c_list_for_each(link, &node->childs) { + r = r600_shader_translate_rec(rshader, link->node); + if (r) + return r; + } + return 0; +} + +static int r600_shader_alu_translate(struct r600_shader *rshader, + struct c_instruction *instruction) +{ + struct r600_shader_alu_translate *info = &r600_alu_translate_list[instruction->opcode]; + struct r600_shader_alu alu; + unsigned rmask; + int r, i, j, c; + + if (!c_list_empty(&rshader->cur_node->vfetch)) { + r = r600_shader_new_node(rshader, rshader->cur_node->node); + if (r) + return r; + } + memset(&alu, 0, sizeof(struct r600_shader_alu)); + for (i = 0, c = 0; i < 4; i++) { + if (!(instruction->write_mask) || instruction->output.swizzle[i] == C_SWIZZLE_D) + continue; + alu.alu[c].opcode = instruction->opcode; + alu.alu[c].inst = info->opcode; + alu.alu[c].is_op3 = info->is_op3; + rmask = ~((1 << (i + 1)) - 1); + r = r600_shader_find_gpr(rshader, instruction->output.vector, + instruction->output.swizzle[i], + &alu.alu[c].dst.sel, &alu.alu[c].dst.chan); + if (r) { + fprintf(stderr, "%s %d register failed\n", __FILE__, __LINE__); + return r; + } + for (j = 0; j < instruction->ninput; j++) { + r = r600_shader_find_gpr(rshader, instruction->input[j].vector, + instruction->input[j].swizzle[i], + &alu.alu[c].src[j].sel, &alu.alu[c].src[j].chan); + if (r) { + fprintf(stderr, "%s %d register failed\n", __FILE__, __LINE__); + return r; + } + if (instruction->input[j].vector->file == C_FILE_IMMEDIATE) { + alu.literal[0] = instruction->input[j].vector->channel[0]->value; + alu.literal[1] = instruction->input[j].vector->channel[1]->value; + alu.literal[2] = instruction->input[j].vector->channel[2]->value; + alu.literal[3] = instruction->input[j].vector->channel[3]->value; + if (alu.alu[c].src[j].chan > 1) { + alu.nliteral = 4; + } else { + alu.nliteral = 2; + } + } + } + c++; + } + alu.nalu = c; + alu.alu[c - 1].last = 1; + r = r600_shader_new_alu(rshader, &alu); + return r; +} + +void r600_shader_node_place(struct r600_shader *rshader) +{ + struct r600_shader_node *node, *nnode; + struct r600_shader_alu *alu, *nalu; + struct r600_shader_vfetch *vfetch, *nvfetch; + unsigned cf_id = 0, cf_addr = 0; + + rshader->ncf = 0; + rshader->nslot = 0; + c_list_for_each_safe(node, nnode, &rshader->nodes) { + c_list_for_each_safe(alu, nalu, &node->alu) { + node->nslot += alu->nalu; + node->nslot += alu->nliteral >> 1; + } + node->nfetch = 0; + c_list_for_each_safe(vfetch, nvfetch, &node->vfetch) { + node->nslot += 2; + node->nfetch += 1; + } + if (!c_list_empty(&node->vfetch)) { + /* fetch node need to be 16 bytes aligned*/ + cf_addr += 1; + cf_addr &= 0xFFFFFFFEUL; + } + node->cf_id = cf_id; + node->cf_addr = cf_addr; + cf_id += 2; + cf_addr += node->nslot * 2; + rshader->ncf++; + } + rshader->nslot = cf_addr; + c_list_for_each_safe(node, nnode, &rshader->nodes) { + node->cf_addr += cf_id * 2; + } + rshader->ncf += rshader->cshader.files[C_FILE_OUTPUT].nvectors; + rshader->ndw = rshader->ncf * 2 + rshader->nslot * 2; +} + +int r600_shader_legalize(struct r600_shader *rshader) +{ + struct r600_shader_node *node, *nnode; + struct r600_shader_alu *alu, *nalu; + unsigned i; + + c_list_for_each_safe(node, nnode, &rshader->nodes) { + c_list_for_each_safe(alu, nalu, &node->alu) { + for (i = 0; i < alu->nalu; i++) { + switch (alu->alu[i].opcode) { + case C_OPCODE_DP3: + if (alu->alu[i].last) { + /* force W component to be 0 */ + alu->alu[i].src[0].chan = alu->alu[i].src[1].chan = 0; + alu->alu[i].src[0].sel = alu->alu[i].src[1].sel = 248; + } + break; + case C_OPCODE_SUB: + alu->alu[i].src[1].neg ^= 1; + break; + case C_OPCODE_ABS: + alu->alu[i].src[0].abs |= 1; + break; + default: + break; + } + } + } + } + return 0; +} + +#if 0 +static int r600_shader_alu_translate_lit(struct r600_shader *rshader, + struct c_instruction *instruction, + struct r600_shader_alu_translate *info) +{ + struct r600_shader_alu alu; + int r; + + if (rshader->cur_node->nvfetch) { + r = r600_shader_new_node(rshader, rshader->cur_node->node); + if (r) + return r; + } + /* dst.z = log(src0.y) */ + memset(&alu, 0, sizeof(struct r600_shader_alu)); + alu.opcode = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED; + alu.is_op3 = 0; + alu.last = 1; + alu.vector[0] = instruction->vectors[0]; + alu.vector[1] = instruction->vectors[1]; + alu.component[0] = C_SWIZZLE_Z; + alu.component[1] = C_SWIZZLE_Y; + r = r600_shader_new_alu(rshader, &alu); + if (r) + return r; + /* dst.z = MUL_LIT(src0.w, dst.z, src0.x) */ + memset(&alu, 0, sizeof(struct r600_shader_alu)); + alu.opcode = V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT; + alu.is_op3 = 0; + alu.last = 1; + alu.vector[0] = instruction->vectors[0]; + alu.vector[1] = instruction->vectors[1]; + alu.vector[2] = instruction->vectors[0]; + alu.vector[3] = instruction->vectors[1]; + alu.component[0] = C_SWIZZLE_Z; + alu.component[1] = C_SWIZZLE_W; + alu.component[2] = C_SWIZZLE_Z; + alu.component[3] = C_SWIZZLE_X; + r = r600_shader_new_alu(rshader, &alu); + if (r) + return r; + /* dst.z = exp(dst.z) */ + memset(&alu, 0, sizeof(struct r600_shader_alu)); + alu.opcode = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE; + alu.is_op3 = 0; + alu.last = 1; + alu.vector[0] = instruction->vectors[0]; + alu.vector[1] = instruction->vectors[0]; + alu.component[0] = C_SWIZZLE_Z; + alu.component[1] = C_SWIZZLE_Z; + r = r600_shader_new_alu(rshader, &alu); + if (r) + return r; + /* dst.x = 1 */ + memset(&alu, 0, sizeof(struct r600_shader_alu)); + alu.opcode = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV; + alu.is_op3 = 0; + alu.last = 0; + alu.vector[0] = instruction->vectors[0]; + alu.vector[1] = instruction->vectors[1]; + alu.component[0] = C_SWIZZLE_X; + alu.component[1] = C_SWIZZLE_1; + r = r600_shader_new_alu(rshader, &alu); + if (r) + return r; + /* dst.w = 1 */ + memset(&alu, 0, sizeof(struct r600_shader_alu)); + alu.opcode = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV; + alu.is_op3 = 0; + alu.last = 0; + alu.vector[0] = instruction->vectors[0]; + alu.vector[1] = instruction->vectors[1]; + alu.component[0] = C_SWIZZLE_W; + alu.component[1] = C_SWIZZLE_1; + r = r600_shader_new_alu(rshader, &alu); + if (r) + return r; + /* dst.y = max(src0.x, 0.0) */ + memset(&alu, 0, sizeof(struct r600_shader_alu)); + alu.opcode = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX; + alu.is_op3 = 0; + alu.last = 1; + alu.vector[0] = instruction->vectors[0]; + alu.vector[1] = instruction->vectors[1]; + alu.vector[2] = instruction->vectors[1]; + alu.component[0] = C_SWIZZLE_Y; + alu.component[1] = C_SWIZZLE_X; + alu.component[2] = C_SWIZZLE_0; + r = r600_shader_new_alu(rshader, &alu); + if (r) + return r; + return 0; +} +#endif +struct r600_shader_alu_translate r600_alu_translate_list[C_OPCODE_LAST] = { + {C_OPCODE_ARL, 0, 0}, + {C_OPCODE_MOV, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, 0}, + {C_OPCODE_LIT, 0, 0}, + {C_OPCODE_RCP, 0, 0}, + {C_OPCODE_RSQ, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_FF, 0}, + {C_OPCODE_EXP, 0, 0}, + {C_OPCODE_LOG, 0, 0}, + {C_OPCODE_MUL, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL, 0}, + {C_OPCODE_ADD, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, 0}, + {C_OPCODE_DP3, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, 0}, + {C_OPCODE_DP4, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, 0}, + {C_OPCODE_DST, 0, 0}, + {C_OPCODE_MIN, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN, 0}, + {C_OPCODE_MAX, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX, 0}, + {C_OPCODE_SLT, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, 0}, + {C_OPCODE_SGE, 0, 0}, + {C_OPCODE_MAD, V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD, 1}, + {C_OPCODE_SUB, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, 0}, + {C_OPCODE_LRP, 0, 0}, + {C_OPCODE_CND, 0, 0}, + {20, 0, 0}, + {C_OPCODE_DP2A, 0, 0}, + {22, 0, 0}, + {23, 0, 0}, + {C_OPCODE_FRC, 0, 0}, + {C_OPCODE_CLAMP, 0, 0}, + {C_OPCODE_FLR, 0, 0}, + {C_OPCODE_ROUND, 0, 0}, + {C_OPCODE_EX2, 0, 0}, + {C_OPCODE_LG2, 0, 0}, + {C_OPCODE_POW, 0, 0}, + {C_OPCODE_XPD, 0, 0}, + {32, 0, 0}, + {C_OPCODE_ABS, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, 0}, + {C_OPCODE_RCC, 0, 0}, + {C_OPCODE_DPH, 0, 0}, + {C_OPCODE_COS, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS, 0}, + {C_OPCODE_DDX, 0, 0}, + {C_OPCODE_DDY, 0, 0}, + {C_OPCODE_KILP, 0, 0}, + {C_OPCODE_PK2H, 0, 0}, + {C_OPCODE_PK2US, 0, 0}, + {C_OPCODE_PK4B, 0, 0}, + {C_OPCODE_PK4UB, 0, 0}, + {C_OPCODE_RFL, 0, 0}, + {C_OPCODE_SEQ, 0, 0}, + {C_OPCODE_SFL, 0, 0}, + {C_OPCODE_SGT, 0, 0}, + {C_OPCODE_SIN, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN, 0}, + {C_OPCODE_SLE, 0, 0}, + {C_OPCODE_SNE, 0, 0}, + {C_OPCODE_STR, 0, 0}, + {C_OPCODE_TEX, 0, 0}, + {C_OPCODE_TXD, 0, 0}, + {C_OPCODE_TXP, 0, 0}, + {C_OPCODE_UP2H, 0, 0}, + {C_OPCODE_UP2US, 0, 0}, + {C_OPCODE_UP4B, 0, 0}, + {C_OPCODE_UP4UB, 0, 0}, + {C_OPCODE_X2D, 0, 0}, + {C_OPCODE_ARA, 0, 0}, + {C_OPCODE_ARR, 0, 0}, + {C_OPCODE_BRA, 0, 0}, + {C_OPCODE_CAL, 0, 0}, + {C_OPCODE_RET, 0, 0}, + {C_OPCODE_SSG, 0, 0}, + {C_OPCODE_CMP, 0, 0}, + {C_OPCODE_SCS, 0, 0}, + {C_OPCODE_TXB, 0, 0}, + {C_OPCODE_NRM, 0, 0}, + {C_OPCODE_DIV, 0, 0}, + {C_OPCODE_DP2, 0, 0}, + {C_OPCODE_TXL, 0, 0}, + {C_OPCODE_BRK, 0, 0}, + {C_OPCODE_IF, 0, 0}, + {C_OPCODE_BGNFOR, 0, 0}, + {C_OPCODE_REP, 0, 0}, + {C_OPCODE_ELSE, 0, 0}, + {C_OPCODE_ENDIF, 0, 0}, + {C_OPCODE_ENDFOR, 0, 0}, + {C_OPCODE_ENDREP, 0, 0}, + {C_OPCODE_PUSHA, 0, 0}, + {C_OPCODE_POPA, 0, 0}, + {C_OPCODE_CEIL, 0, 0}, + {C_OPCODE_I2F, 0, 0}, + {C_OPCODE_NOT, 0, 0}, + {C_OPCODE_TRUNC, 0, 0}, + {C_OPCODE_SHL, 0, 0}, + {88, 0, 0}, + {C_OPCODE_AND, 0, 0}, + {C_OPCODE_OR, 0, 0}, + {C_OPCODE_MOD, 0, 0}, + {C_OPCODE_XOR, 0, 0}, + {C_OPCODE_SAD, 0, 0}, + {C_OPCODE_TXF, 0, 0}, + {C_OPCODE_TXQ, 0, 0}, + {C_OPCODE_CONT, 0, 0}, + {C_OPCODE_EMIT, 0, 0}, + {C_OPCODE_ENDPRIM, 0, 0}, + {C_OPCODE_BGNLOOP, 0, 0}, + {C_OPCODE_BGNSUB, 0, 0}, + {C_OPCODE_ENDLOOP, 0, 0}, + {C_OPCODE_ENDSUB, 0, 0}, + {103, 0, 0}, + {104, 0, 0}, + {105, 0, 0}, + {106, 0, 0}, + {C_OPCODE_NOP, 0, 0}, + {108, 0, 0}, + {109, 0, 0}, + {110, 0, 0}, + {111, 0, 0}, + {C_OPCODE_NRM4, 0, 0}, + {C_OPCODE_CALLNZ, 0, 0}, + {C_OPCODE_IFC, 0, 0}, + {C_OPCODE_BREAKC, 0, 0}, + {C_OPCODE_KIL, 0, 0}, + {C_OPCODE_END, 0, 0}, + {118, 0, 0}, + {C_OPCODE_F2I, 0, 0}, + {C_OPCODE_IDIV, 0, 0}, + {C_OPCODE_IMAX, 0, 0}, + {C_OPCODE_IMIN, 0, 0}, + {C_OPCODE_INEG, 0, 0}, + {C_OPCODE_ISGE, 0, 0}, + {C_OPCODE_ISHR, 0, 0}, + {C_OPCODE_ISLT, 0, 0}, + {C_OPCODE_F2U, 0, 0}, + {C_OPCODE_U2F, 0, 0}, + {C_OPCODE_UADD, 0, 0}, + {C_OPCODE_UDIV, 0, 0}, + {C_OPCODE_UMAD, 0, 0}, + {C_OPCODE_UMAX, 0, 0}, + {C_OPCODE_UMIN, 0, 0}, + {C_OPCODE_UMOD, 0, 0}, + {C_OPCODE_UMUL, 0, 0}, + {C_OPCODE_USEQ, 0, 0}, + {C_OPCODE_USGE, 0, 0}, + {C_OPCODE_USHR, 0, 0}, + {C_OPCODE_USLT, 0, 0}, + {C_OPCODE_USNE, 0, 0}, + {C_OPCODE_SWITCH, 0, 0}, + {C_OPCODE_CASE, 0, 0}, + {C_OPCODE_DEFAULT, 0, 0}, + {C_OPCODE_ENDSWITCH, 0, 0}, + {C_OPCODE_VFETCH, 0, 0}, + {C_OPCODE_ENTRY, 0, 0}, +}; diff --git a/src/gallium/drivers/r600/r600_compiler_r700.c b/src/gallium/drivers/r600/r600_compiler_r700.c new file mode 100644 index 00000000000..2cc2951f944 --- /dev/null +++ b/src/gallium/drivers/r600/r600_compiler_r700.c @@ -0,0 +1,213 @@ +/* + * Copyright 2010 Jerome Glisse <[email protected]> + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#include <stdlib.h> +#include <string.h> +#include <stdint.h> +#include <stdio.h> +#include <errno.h> +#include "r600_context.h" +#include "r700_sq.h" + +static int r700_shader_cf_node_bytecode(struct r600_shader *rshader, + struct r600_shader_node *rnode, + unsigned *cid) +{ + unsigned id = *cid; + + if (rnode->nfetch) { + rshader->bcode[id++] = S_SQ_CF_WORD0_ADDR(rnode->cf_addr >> 1); + rshader->bcode[id++] = S_SQ_CF_WORD1_CF_INST(V_SQ_CF_WORD1_SQ_CF_INST_VTX) | + S_SQ_CF_WORD1_COUNT(rnode->nfetch - 1); + } else { + rshader->bcode[id++] = S_SQ_CF_ALU_WORD0_ADDR(rnode->cf_addr >> 1); + rshader->bcode[id++] = S_SQ_CF_ALU_WORD1_CF_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU) | + S_SQ_CF_ALU_WORD1_BARRIER(1) | + S_SQ_CF_ALU_WORD1_COUNT(rnode->nslot - 1); + } + *cid = id; + return 0; +} + +static int r700_shader_cf_output_bytecode(struct r600_shader *rshader, + struct c_vector *v, + unsigned *cid, + unsigned end) +{ + unsigned gpr, chan; + unsigned id = *cid; + int r; + + r = r600_shader_find_gpr(rshader, v, 0, &gpr, &chan); + if (r) + return r; + rshader->bcode[id + 0] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(gpr) | + S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(3); + rshader->bcode[id + 1] = S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(0) | + S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(1) | + S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(2) | + S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(3) | + S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(1) | + S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE) | + S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(end); + switch (v->name) { + case C_SEMANTIC_POSITION: + rshader->bcode[id + 0] |= S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(60) | + S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS); + break; + case C_SEMANTIC_COLOR: + if (rshader->cshader.type == C_PROGRAM_TYPE_VS) { + rshader->output[rshader->noutput].gpr = gpr; + rshader->output[rshader->noutput].sid = v->sid; + rshader->output[rshader->noutput].name = v->name; + rshader->bcode[id + 0] |= S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(rshader->noutput++) | + S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM); + } else { + rshader->bcode[id + 0] |= S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(0) | + S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL); + } + break; + case C_SEMANTIC_GENERIC: + rshader->output[rshader->noutput].gpr = gpr; + rshader->output[rshader->noutput].sid = v->sid; + rshader->output[rshader->noutput].name = v->name; + rshader->bcode[id + 0] |= S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(rshader->noutput++) | + S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM); + break; + default: + fprintf(stderr, "%s:%d unsupported\n", __func__, __LINE__); + return -EINVAL; + } + *cid = id + 2; + return 0; +} + +static int r700_shader_alu_bytecode(struct r600_shader *rshader, + struct r600_shader_node *rnode, + struct r600_shader_inst *alu, + unsigned *cid) +{ + unsigned id = *cid; + + /* don't replace gpr by pv or ps for destination register */ + if (alu->is_op3) { + rshader->bcode[id++] = S_SQ_ALU_WORD0_SRC0_SEL(alu->src[0].sel) | + S_SQ_ALU_WORD0_SRC0_CHAN(alu->src[0].chan) | + S_SQ_ALU_WORD0_SRC1_SEL(alu->src[1].sel) | + S_SQ_ALU_WORD0_SRC1_CHAN(alu->src[1].chan) | + S_SQ_ALU_WORD0_LAST(alu->last); + rshader->bcode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) | + S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) | + S_SQ_ALU_WORD1_OP3_SRC2_SEL(alu->src[2].sel) | + S_SQ_ALU_WORD1_OP3_SRC2_CHAN(alu->src[2].chan) | + S_SQ_ALU_WORD1_OP3_SRC2_NEG(alu->src[2].neg) | + S_SQ_ALU_WORD1_OP3_ALU_INST(alu->inst) | + S_SQ_ALU_WORD1_BANK_SWIZZLE(0); + } else { + rshader->bcode[id++] = S_SQ_ALU_WORD0_SRC0_SEL(alu->src[0].sel) | + S_SQ_ALU_WORD0_SRC0_CHAN(alu->src[0].chan) | + S_SQ_ALU_WORD0_SRC0_NEG(alu->src[0].neg) | + S_SQ_ALU_WORD0_SRC1_SEL(alu->src[1].sel) | + S_SQ_ALU_WORD0_SRC1_CHAN(alu->src[1].chan) | + S_SQ_ALU_WORD0_SRC1_NEG(alu->src[1].neg) | + S_SQ_ALU_WORD0_LAST(alu->last); + rshader->bcode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) | + S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) | + S_SQ_ALU_WORD1_OP2_SRC0_ABS(alu->src[0].abs) | + S_SQ_ALU_WORD1_OP2_SRC1_ABS(alu->src[1].abs) | + S_SQ_ALU_WORD1_OP2_WRITE_MASK(1) | + S_SQ_ALU_WORD1_OP2_ALU_INST(alu->inst) | + S_SQ_ALU_WORD1_BANK_SWIZZLE(0); + } + *cid = id; + return 0; +} + +int r700_shader_translate(struct r600_shader *rshader) +{ + struct c_shader *shader = &rshader->cshader; + struct r600_shader_node *rnode; + struct r600_shader_vfetch *vfetch; + struct r600_shader_alu *alu; + struct c_vector *v; + unsigned id, i, end; + int r; + + r = r600_shader_register(rshader); + if (r) { + fprintf(stderr, "%s %d register allocation failed\n", __FILE__, __LINE__); + return r; + } + r = r600_shader_translate_rec(rshader, &shader->entry); + if (r) { + fprintf(stderr, "%s %d translation failed\n", __FILE__, __LINE__); + return r; + } + r = r600_shader_legalize(rshader); + if (r) { + fprintf(stderr, "%s %d legalize failed\n", __FILE__, __LINE__); + return r; + } + r600_shader_node_place(rshader); + rshader->bcode = malloc(rshader->ndw * 4); + if (rshader->bcode == NULL) + return -ENOMEM; + c_list_for_each(rnode, &rshader->nodes) { + id = rnode->cf_addr; + c_list_for_each(vfetch, &rnode->vfetch) { + r = r600_shader_vfetch_bytecode(rshader, rnode, vfetch, &id); + if (r) + return r; + } + c_list_for_each(alu, &rnode->alu) { + for (i = 0; i < alu->nalu; i++) { + r = r700_shader_alu_bytecode(rshader, rnode, &alu->alu[i], &id); + if (r) + return r; + } + for (i = 0; i < alu->nliteral; i++) { + rshader->bcode[id++] = alu->literal[i]; + } + } + } + id = 0; + c_list_for_each(rnode, &rshader->nodes) { + r = r700_shader_cf_node_bytecode(rshader, rnode, &id); + if (r) + return r; + } + c_list_for_each(v, &rshader->cshader.files[C_FILE_OUTPUT].vectors) { + end = 0; + if (v->next == &rshader->cshader.files[C_FILE_OUTPUT].vectors) + end = 1; + r = r700_shader_cf_output_bytecode(rshader, v, &id, end); + if (r) + return r; + } + c_list_for_each(v, &rshader->cshader.files[C_FILE_INPUT].vectors) { + rshader->input[rshader->ninput].gpr = rshader->ninput; + rshader->input[rshader->ninput].sid = v->sid; + rshader->input[rshader->ninput].name = v->name; + rshader->ninput++; + } + return 0; +} diff --git a/src/gallium/drivers/r600/r600_compiler_tgsi.c b/src/gallium/drivers/r600/r600_compiler_tgsi.c new file mode 100644 index 00000000000..745f92272f8 --- /dev/null +++ b/src/gallium/drivers/r600/r600_compiler_tgsi.c @@ -0,0 +1,717 @@ +/* + * Copyright 2010 Jerome Glisse <[email protected]> + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#include <stdlib.h> +#include <string.h> +#include <stdint.h> +#include <stdio.h> +#include <errno.h> +#include <tgsi/tgsi_parse.h> +#include <tgsi/tgsi_scan.h> +#include "r600_shader.h" +#include "r600_context.h" + +struct tgsi_shader { + struct c_vector **v[TGSI_FILE_COUNT]; + struct tgsi_shader_info info; + struct tgsi_parse_context parser; + const struct tgsi_token *tokens; + struct c_shader *shader; + struct c_node *node; +}; + +static unsigned tgsi_file_to_c_file(unsigned file); +static unsigned tgsi_sname_to_c_sname(unsigned sname); +static int tgsi_opcode_to_c_opcode(unsigned opcode, unsigned *copcode); + +static int tgsi_shader_init(struct tgsi_shader *ts, + const struct tgsi_token *tokens, + struct c_shader *shader) +{ + int i; + + ts->shader = shader; + ts->tokens = tokens; + tgsi_scan_shader(ts->tokens, &ts->info); + tgsi_parse_init(&ts->parser, ts->tokens); + /* initialize to NULL in case of error */ + for (i = 0; i < C_FILE_COUNT; i++) { + ts->v[i] = NULL; + } + for (i = 0; i < TGSI_FILE_COUNT; i++) { + if (ts->info.file_count[i] > 0) { + ts->v[i] = calloc(ts->info.file_count[i], sizeof(void*)); + if (ts->v[i] == NULL) { + fprintf(stderr, "%s:%d unsupported %d %d\n", __func__, __LINE__, i, ts->info.file_count[i]); + return -ENOMEM; + } + } + } + return 0; +} + +static void tgsi_shader_destroy(struct tgsi_shader *ts) +{ + int i; + + for (i = 0; i < TGSI_FILE_COUNT; i++) { + free(ts->v[i]); + } + tgsi_parse_free(&ts->parser); +} + +static int ntransform_declaration(struct tgsi_shader *ts) +{ + struct tgsi_full_declaration *fd = &ts->parser.FullToken.FullDeclaration; + struct c_vector *v; + unsigned file; + unsigned name; + int sid; + int i; + + if (fd->Declaration.Dimension) { + fprintf(stderr, "%s:%d unsupported\n", __func__, __LINE__); + return -EINVAL; + } + for (i = fd->Range.First ; i <= fd->Range.Last; i++) { + sid = i; + name = C_SEMANTIC_GENERIC; + file = tgsi_file_to_c_file(fd->Declaration.File); + if (file == TGSI_FILE_NULL) { + fprintf(stderr, "%s:%d unsupported\n", __func__, __LINE__); + return -EINVAL; + } + if (fd->Declaration.Semantic) { + name = tgsi_sname_to_c_sname(fd->Semantic.Name); + sid = fd->Semantic.Index; + } + v = c_shader_vector_new(ts->shader, file, name, sid); + if (v == NULL) { + fprintf(stderr, "%s:%d unsupported\n", __func__, __LINE__); + return -ENOMEM; + } + ts->v[fd->Declaration.File][i] = v; + } + return 0; +} + +static int ntransform_immediate(struct tgsi_shader *ts) +{ + struct tgsi_full_immediate *fd = &ts->parser.FullToken.FullImmediate; + struct c_vector *v; + unsigned file; + unsigned name; + + if (fd->Immediate.DataType != TGSI_IMM_FLOAT32) { + fprintf(stderr, "%s:%d unsupported\n", __func__, __LINE__); + return -EINVAL; + } + name = C_SEMANTIC_GENERIC; + file = C_FILE_IMMEDIATE; + v = c_shader_vector_new(ts->shader, file, name, 0); + if (v == NULL) { + fprintf(stderr, "%s:%d unsupported\n", __func__, __LINE__); + return -ENOMEM; + } + v->channel[0]->value = fd->u[0].Uint; + v->channel[1]->value = fd->u[1].Uint; + v->channel[2]->value = fd->u[2].Uint; + v->channel[3]->value = fd->u[3].Uint; + ts->v[TGSI_FILE_IMMEDIATE][0] = v; + return 0; +} + +static int ntransform_instruction(struct tgsi_shader *ts) +{ + struct tgsi_full_instruction *fi = &ts->parser.FullToken.FullInstruction; + struct c_shader *shader = ts->shader; + struct c_instruction instruction; + unsigned opcode; + int i, r; + + if (fi->Instruction.NumDstRegs > 1) { + fprintf(stderr, "%s %d unsupported\n", __func__, __LINE__); + return -EINVAL; + } + if (fi->Instruction.Saturate) { + fprintf(stderr, "%s %d unsupported\n", __func__, __LINE__); + return -EINVAL; + } + if (fi->Instruction.Predicate) { + fprintf(stderr, "%s %d unsupported\n", __func__, __LINE__); + return -EINVAL; + } + if (fi->Instruction.Label) { + fprintf(stderr, "%s %d unsupported\n", __func__, __LINE__); + return -EINVAL; + } + if (fi->Instruction.Texture) { + fprintf(stderr, "%s %d unsupported\n", __func__, __LINE__); + return -EINVAL; + } + for (i = 0; i < fi->Instruction.NumSrcRegs; i++) { + if (fi->Src[i].Register.Indirect || + fi->Src[i].Register.Dimension || + fi->Src[i].Register.Absolute) { + fprintf(stderr, "%s %d unsupported\n", __func__, __LINE__); + return -EINVAL; + } + } + for (i = 0; i < fi->Instruction.NumDstRegs; i++) { + if (fi->Dst[i].Register.Indirect || fi->Dst[i].Register.Dimension) { + fprintf(stderr, "%s %d unsupported\n", __func__, __LINE__); + return -EINVAL; + } + } + r = tgsi_opcode_to_c_opcode(fi->Instruction.Opcode, &opcode); + if (r) { + fprintf(stderr, "%s:%d unsupported\n", __func__, __LINE__); + return r; + } + if (opcode == C_OPCODE_END) { + return c_node_cfg_link(ts->node, &shader->end); + } + /* FIXME add flow instruction handling */ + memset(&instruction, 0, sizeof(struct c_instruction)); + instruction.opcode = opcode; + instruction.ninput = fi->Instruction.NumSrcRegs; + instruction.write_mask = fi->Dst[0].Register.WriteMask; + for (i = 0; i < fi->Instruction.NumSrcRegs; i++) { + instruction.input[i].vector = ts->v[fi->Src[i].Register.File][fi->Src[i].Register.Index]; + instruction.input[i].swizzle[0] = fi->Src[i].Register.SwizzleX; + instruction.input[i].swizzle[1] = fi->Src[i].Register.SwizzleY; + instruction.input[i].swizzle[2] = fi->Src[i].Register.SwizzleZ; + instruction.input[i].swizzle[3] = fi->Src[i].Register.SwizzleW; + } + instruction.output.vector = ts->v[fi->Dst[0].Register.File][fi->Dst[0].Register.Index]; + instruction.output.swizzle[0] = (fi->Dst[0].Register.WriteMask & 0x1) ? C_SWIZZLE_X : C_SWIZZLE_D; + instruction.output.swizzle[1] = (fi->Dst[0].Register.WriteMask & 0x2) ? C_SWIZZLE_Y : C_SWIZZLE_D; + instruction.output.swizzle[2] = (fi->Dst[0].Register.WriteMask & 0x4) ? C_SWIZZLE_Z : C_SWIZZLE_D; + instruction.output.swizzle[3] = (fi->Dst[0].Register.WriteMask & 0x8) ? C_SWIZZLE_W : C_SWIZZLE_D; + return c_node_add_new_instruction(ts->node, &instruction); +} + +int c_shader_from_tgsi(struct c_shader *shader, unsigned type, + const struct tgsi_token *tokens) +{ + struct tgsi_shader ts; + int r = 0; + + c_shader_init(shader, type); + r = tgsi_shader_init(&ts, tokens, shader); + if (r) + goto out_err; + ts.shader = shader; + ts.node = &shader->entry; + while (!tgsi_parse_end_of_tokens(&ts.parser)) { + tgsi_parse_token(&ts.parser); + switch (ts.parser.FullToken.Token.Type) { + case TGSI_TOKEN_TYPE_IMMEDIATE: + r = ntransform_immediate(&ts); + if (r) + goto out_err; + break; + case TGSI_TOKEN_TYPE_DECLARATION: + r = ntransform_declaration(&ts); + if (r) + goto out_err; + break; + case TGSI_TOKEN_TYPE_INSTRUCTION: + r = ntransform_instruction(&ts); + if (r) + goto out_err; + break; + default: + r = -EINVAL; + goto out_err; + } + } + tgsi_shader_destroy(&ts); + return 0; +out_err: + c_shader_destroy(shader); + tgsi_shader_destroy(&ts); + return r; +} + +static unsigned tgsi_file_to_c_file(unsigned file) +{ + switch (file) { + case TGSI_FILE_CONSTANT: + return C_FILE_CONSTANT; + case TGSI_FILE_INPUT: + return C_FILE_INPUT; + case TGSI_FILE_OUTPUT: + return C_FILE_OUTPUT; + case TGSI_FILE_TEMPORARY: + return C_FILE_TEMPORARY; + case TGSI_FILE_SAMPLER: + return C_FILE_SAMPLER; + case TGSI_FILE_ADDRESS: + return C_FILE_ADDRESS; + case TGSI_FILE_IMMEDIATE: + return C_FILE_IMMEDIATE; + case TGSI_FILE_LOOP: + return C_FILE_LOOP; + case TGSI_FILE_PREDICATE: + return C_FILE_PREDICATE; + case TGSI_FILE_SYSTEM_VALUE: + return C_FILE_SYSTEM_VALUE; + case TGSI_FILE_NULL: + return C_FILE_NULL; + default: + fprintf(stderr, "%s:%d unsupported file %d\n", __func__, __LINE__, file); + return C_FILE_NULL; + } +} + +static unsigned tgsi_sname_to_c_sname(unsigned sname) +{ + switch (sname) { + case TGSI_SEMANTIC_POSITION: + return C_SEMANTIC_POSITION; + case TGSI_SEMANTIC_COLOR: + return C_SEMANTIC_COLOR; + case TGSI_SEMANTIC_BCOLOR: + return C_SEMANTIC_BCOLOR; + case TGSI_SEMANTIC_FOG: + return C_SEMANTIC_FOG; + case TGSI_SEMANTIC_PSIZE: + return C_SEMANTIC_PSIZE; + case TGSI_SEMANTIC_GENERIC: + return C_SEMANTIC_GENERIC; + case TGSI_SEMANTIC_NORMAL: + return C_SEMANTIC_NORMAL; + case TGSI_SEMANTIC_FACE: + return C_SEMANTIC_FACE; + case TGSI_SEMANTIC_EDGEFLAG: + return C_SEMANTIC_EDGEFLAG; + case TGSI_SEMANTIC_PRIMID: + return C_SEMANTIC_PRIMID; + case TGSI_SEMANTIC_INSTANCEID: + return C_SEMANTIC_INSTANCEID; + default: + return C_SEMANTIC_GENERIC; + } +} + +static int tgsi_opcode_to_c_opcode(unsigned opcode, unsigned *copcode) +{ + switch (opcode) { + case TGSI_OPCODE_MOV: + *copcode = C_OPCODE_MOV; + return 0; + case TGSI_OPCODE_MUL: + *copcode = C_OPCODE_MUL; + return 0; + case TGSI_OPCODE_MAD: + *copcode = C_OPCODE_MAD; + return 0; + case TGSI_OPCODE_END: + *copcode = C_OPCODE_END; + return 0; + case TGSI_OPCODE_ARL: + *copcode = C_OPCODE_ARL; + return 0; + case TGSI_OPCODE_LIT: + *copcode = C_OPCODE_LIT; + return 0; + case TGSI_OPCODE_RCP: + *copcode = C_OPCODE_RCP; + return 0; + case TGSI_OPCODE_RSQ: + *copcode = C_OPCODE_RSQ; + return 0; + case TGSI_OPCODE_EXP: + *copcode = C_OPCODE_EXP; + return 0; + case TGSI_OPCODE_LOG: + *copcode = C_OPCODE_LOG; + return 0; + case TGSI_OPCODE_ADD: + *copcode = C_OPCODE_ADD; + return 0; + case TGSI_OPCODE_DP3: + *copcode = C_OPCODE_DP3; + return 0; + case TGSI_OPCODE_DP4: + *copcode = C_OPCODE_DP4; + return 0; + case TGSI_OPCODE_DST: + *copcode = C_OPCODE_DST; + return 0; + case TGSI_OPCODE_MIN: + *copcode = C_OPCODE_MIN; + return 0; + case TGSI_OPCODE_MAX: + *copcode = C_OPCODE_MAX; + return 0; + case TGSI_OPCODE_SLT: + *copcode = C_OPCODE_SLT; + return 0; + case TGSI_OPCODE_SGE: + *copcode = C_OPCODE_SGE; + return 0; + case TGSI_OPCODE_SUB: + *copcode = C_OPCODE_SUB; + return 0; + case TGSI_OPCODE_LRP: + *copcode = C_OPCODE_LRP; + return 0; + case TGSI_OPCODE_CND: + *copcode = C_OPCODE_CND; + return 0; + case TGSI_OPCODE_DP2A: + *copcode = C_OPCODE_DP2A; + return 0; + case TGSI_OPCODE_FRC: + *copcode = C_OPCODE_FRC; + return 0; + case TGSI_OPCODE_CLAMP: + *copcode = C_OPCODE_CLAMP; + return 0; + case TGSI_OPCODE_FLR: + *copcode = C_OPCODE_FLR; + return 0; + case TGSI_OPCODE_ROUND: + *copcode = C_OPCODE_ROUND; + return 0; + case TGSI_OPCODE_EX2: + *copcode = C_OPCODE_EX2; + return 0; + case TGSI_OPCODE_LG2: + *copcode = C_OPCODE_LG2; + return 0; + case TGSI_OPCODE_POW: + *copcode = C_OPCODE_POW; + return 0; + case TGSI_OPCODE_XPD: + *copcode = C_OPCODE_XPD; + return 0; + case TGSI_OPCODE_ABS: + *copcode = C_OPCODE_ABS; + return 0; + case TGSI_OPCODE_RCC: + *copcode = C_OPCODE_RCC; + return 0; + case TGSI_OPCODE_DPH: + *copcode = C_OPCODE_DPH; + return 0; + case TGSI_OPCODE_COS: + *copcode = C_OPCODE_COS; + return 0; + case TGSI_OPCODE_DDX: + *copcode = C_OPCODE_DDX; + return 0; + case TGSI_OPCODE_DDY: + *copcode = C_OPCODE_DDY; + return 0; + case TGSI_OPCODE_KILP: + *copcode = C_OPCODE_KILP; + return 0; + case TGSI_OPCODE_PK2H: + *copcode = C_OPCODE_PK2H; + return 0; + case TGSI_OPCODE_PK2US: + *copcode = C_OPCODE_PK2US; + return 0; + case TGSI_OPCODE_PK4B: + *copcode = C_OPCODE_PK4B; + return 0; + case TGSI_OPCODE_PK4UB: + *copcode = C_OPCODE_PK4UB; + return 0; + case TGSI_OPCODE_RFL: + *copcode = C_OPCODE_RFL; + return 0; + case TGSI_OPCODE_SEQ: + *copcode = C_OPCODE_SEQ; + return 0; + case TGSI_OPCODE_SFL: + *copcode = C_OPCODE_SFL; + return 0; + case TGSI_OPCODE_SGT: + *copcode = C_OPCODE_SGT; + return 0; + case TGSI_OPCODE_SIN: + *copcode = C_OPCODE_SIN; + return 0; + case TGSI_OPCODE_SLE: + *copcode = C_OPCODE_SLE; + return 0; + case TGSI_OPCODE_SNE: + *copcode = C_OPCODE_SNE; + return 0; + case TGSI_OPCODE_STR: + *copcode = C_OPCODE_STR; + return 0; + case TGSI_OPCODE_TEX: + *copcode = C_OPCODE_TEX; + return 0; + case TGSI_OPCODE_TXD: + *copcode = C_OPCODE_TXD; + return 0; + case TGSI_OPCODE_TXP: + *copcode = C_OPCODE_TXP; + return 0; + case TGSI_OPCODE_UP2H: + *copcode = C_OPCODE_UP2H; + return 0; + case TGSI_OPCODE_UP2US: + *copcode = C_OPCODE_UP2US; + return 0; + case TGSI_OPCODE_UP4B: + *copcode = C_OPCODE_UP4B; + return 0; + case TGSI_OPCODE_UP4UB: + *copcode = C_OPCODE_UP4UB; + return 0; + case TGSI_OPCODE_X2D: + *copcode = C_OPCODE_X2D; + return 0; + case TGSI_OPCODE_ARA: + *copcode = C_OPCODE_ARA; + return 0; + case TGSI_OPCODE_ARR: + *copcode = C_OPCODE_ARR; + return 0; + case TGSI_OPCODE_BRA: + *copcode = C_OPCODE_BRA; + return 0; + case TGSI_OPCODE_CAL: + *copcode = C_OPCODE_CAL; + return 0; + case TGSI_OPCODE_RET: + *copcode = C_OPCODE_RET; + return 0; + case TGSI_OPCODE_SSG: + *copcode = C_OPCODE_SSG; + return 0; + case TGSI_OPCODE_CMP: + *copcode = C_OPCODE_CMP; + return 0; + case TGSI_OPCODE_SCS: + *copcode = C_OPCODE_SCS; + return 0; + case TGSI_OPCODE_TXB: + *copcode = C_OPCODE_TXB; + return 0; + case TGSI_OPCODE_NRM: + *copcode = C_OPCODE_NRM; + return 0; + case TGSI_OPCODE_DIV: + *copcode = C_OPCODE_DIV; + return 0; + case TGSI_OPCODE_DP2: + *copcode = C_OPCODE_DP2; + return 0; + case TGSI_OPCODE_TXL: + *copcode = C_OPCODE_TXL; + return 0; + case TGSI_OPCODE_BRK: + *copcode = C_OPCODE_BRK; + return 0; + case TGSI_OPCODE_IF: + *copcode = C_OPCODE_IF; + return 0; + case TGSI_OPCODE_BGNFOR: + *copcode = C_OPCODE_BGNFOR; + return 0; + case TGSI_OPCODE_REP: + *copcode = C_OPCODE_REP; + return 0; + case TGSI_OPCODE_ELSE: + *copcode = C_OPCODE_ELSE; + return 0; + case TGSI_OPCODE_ENDIF: + *copcode = C_OPCODE_ENDIF; + return 0; + case TGSI_OPCODE_ENDFOR: + *copcode = C_OPCODE_ENDFOR; + return 0; + case TGSI_OPCODE_ENDREP: + *copcode = C_OPCODE_ENDREP; + return 0; + case TGSI_OPCODE_PUSHA: + *copcode = C_OPCODE_PUSHA; + return 0; + case TGSI_OPCODE_POPA: + *copcode = C_OPCODE_POPA; + return 0; + case TGSI_OPCODE_CEIL: + *copcode = C_OPCODE_CEIL; + return 0; + case TGSI_OPCODE_I2F: + *copcode = C_OPCODE_I2F; + return 0; + case TGSI_OPCODE_NOT: + *copcode = C_OPCODE_NOT; + return 0; + case TGSI_OPCODE_TRUNC: + *copcode = C_OPCODE_TRUNC; + return 0; + case TGSI_OPCODE_SHL: + *copcode = C_OPCODE_SHL; + return 0; + case TGSI_OPCODE_AND: + *copcode = C_OPCODE_AND; + return 0; + case TGSI_OPCODE_OR: + *copcode = C_OPCODE_OR; + return 0; + case TGSI_OPCODE_MOD: + *copcode = C_OPCODE_MOD; + return 0; + case TGSI_OPCODE_XOR: + *copcode = C_OPCODE_XOR; + return 0; + case TGSI_OPCODE_SAD: + *copcode = C_OPCODE_SAD; + return 0; + case TGSI_OPCODE_TXF: + *copcode = C_OPCODE_TXF; + return 0; + case TGSI_OPCODE_TXQ: + *copcode = C_OPCODE_TXQ; + return 0; + case TGSI_OPCODE_CONT: + *copcode = C_OPCODE_CONT; + return 0; + case TGSI_OPCODE_EMIT: + *copcode = C_OPCODE_EMIT; + return 0; + case TGSI_OPCODE_ENDPRIM: + *copcode = C_OPCODE_ENDPRIM; + return 0; + case TGSI_OPCODE_BGNLOOP: + *copcode = C_OPCODE_BGNLOOP; + return 0; + case TGSI_OPCODE_BGNSUB: + *copcode = C_OPCODE_BGNSUB; + return 0; + case TGSI_OPCODE_ENDLOOP: + *copcode = C_OPCODE_ENDLOOP; + return 0; + case TGSI_OPCODE_ENDSUB: + *copcode = C_OPCODE_ENDSUB; + return 0; + case TGSI_OPCODE_NOP: + *copcode = C_OPCODE_NOP; + return 0; + case TGSI_OPCODE_NRM4: + *copcode = C_OPCODE_NRM4; + return 0; + case TGSI_OPCODE_CALLNZ: + *copcode = C_OPCODE_CALLNZ; + return 0; + case TGSI_OPCODE_IFC: + *copcode = C_OPCODE_IFC; + return 0; + case TGSI_OPCODE_BREAKC: + *copcode = C_OPCODE_BREAKC; + return 0; + case TGSI_OPCODE_KIL: + *copcode = C_OPCODE_KIL; + return 0; + case TGSI_OPCODE_F2I: + *copcode = C_OPCODE_F2I; + return 0; + case TGSI_OPCODE_IDIV: + *copcode = C_OPCODE_IDIV; + return 0; + case TGSI_OPCODE_IMAX: + *copcode = C_OPCODE_IMAX; + return 0; + case TGSI_OPCODE_IMIN: + *copcode = C_OPCODE_IMIN; + return 0; + case TGSI_OPCODE_INEG: + *copcode = C_OPCODE_INEG; + return 0; + case TGSI_OPCODE_ISGE: + *copcode = C_OPCODE_ISGE; + return 0; + case TGSI_OPCODE_ISHR: + *copcode = C_OPCODE_ISHR; + return 0; + case TGSI_OPCODE_ISLT: + *copcode = C_OPCODE_ISLT; + return 0; + case TGSI_OPCODE_F2U: + *copcode = C_OPCODE_F2U; + return 0; + case TGSI_OPCODE_U2F: + *copcode = C_OPCODE_U2F; + return 0; + case TGSI_OPCODE_UADD: + *copcode = C_OPCODE_UADD; + return 0; + case TGSI_OPCODE_UDIV: + *copcode = C_OPCODE_UDIV; + return 0; + case TGSI_OPCODE_UMAD: + *copcode = C_OPCODE_UMAD; + return 0; + case TGSI_OPCODE_UMAX: + *copcode = C_OPCODE_UMAX; + return 0; + case TGSI_OPCODE_UMIN: + *copcode = C_OPCODE_UMIN; + return 0; + case TGSI_OPCODE_UMOD: + *copcode = C_OPCODE_UMOD; + return 0; + case TGSI_OPCODE_UMUL: + *copcode = C_OPCODE_UMUL; + return 0; + case TGSI_OPCODE_USEQ: + *copcode = C_OPCODE_USEQ; + return 0; + case TGSI_OPCODE_USGE: + *copcode = C_OPCODE_USGE; + return 0; + case TGSI_OPCODE_USHR: + *copcode = C_OPCODE_USHR; + return 0; + case TGSI_OPCODE_USLT: + *copcode = C_OPCODE_USLT; + return 0; + case TGSI_OPCODE_USNE: + *copcode = C_OPCODE_USNE; + return 0; + case TGSI_OPCODE_SWITCH: + *copcode = C_OPCODE_SWITCH; + return 0; + case TGSI_OPCODE_CASE: + *copcode = C_OPCODE_CASE; + return 0; + case TGSI_OPCODE_DEFAULT: + *copcode = C_OPCODE_DEFAULT; + return 0; + case TGSI_OPCODE_ENDSWITCH: + *copcode = C_OPCODE_ENDSWITCH; + return 0; + default: + fprintf(stderr, "%s:%d unsupported opcode %d\n", __func__, __LINE__, opcode); + return -EINVAL; + } +} diff --git a/src/gallium/drivers/r600/r600_context.c b/src/gallium/drivers/r600/r600_context.c new file mode 100644 index 00000000000..faefdb4378e --- /dev/null +++ b/src/gallium/drivers/r600/r600_context.c @@ -0,0 +1,167 @@ +/* + * Copyright 2010 Jerome Glisse <[email protected]> + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Jerome Glisse + * Corbin Simpson + */ +#include <stdio.h> +#include <util/u_inlines.h> +#include <util/u_format.h> +#include <util/u_memory.h> +#include <util/u_blitter.h> +#include "r600_screen.h" +#include "r600_texture.h" +#include "r600_context.h" + +static void r600_destroy_context(struct pipe_context *context) +{ + struct r600_context *rctx = (struct r600_context*)context; + + FREE(rctx); +} + +static unsigned int r600_is_texture_referenced(struct pipe_context *context, + struct pipe_texture *texture, + unsigned face, unsigned level) +{ + struct pipe_buffer *buffer = NULL; + + r600_get_texture_buffer(context->screen, texture, &buffer, NULL); + return context->is_buffer_referenced(context, buffer); +} + +static unsigned int r600_is_buffer_referenced(struct pipe_context *context, struct pipe_buffer *buffer) +{ + return 0; +} + +static void r600_flush(struct pipe_context *ctx, unsigned flags, + struct pipe_fence_handle **fence) +{ + struct r600_context *rctx = (struct r600_context*)ctx; + struct r600_screen *rscreen = (struct r600_screen*)ctx->screen; +static int dc = 0; + + if (radeon_ctx_pm4(rctx->ctx)) + return; + if (dc) + return; + radeon_ctx_dump_bof(rctx->ctx, "gallium.bof"); + radeon_ctx_submit(rctx->ctx); + rctx->ctx = radeon_ctx_decref(rctx->ctx); + rctx->ctx = radeon_ctx(rscreen->rw); + dc++; +} + +struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv) +{ + struct r600_context *rctx = CALLOC_STRUCT(r600_context); + struct r600_screen* rscreen = r600_screen(screen); + + if (rctx == NULL) + return NULL; + rctx->context.winsys = rscreen->screen.winsys; + rctx->context.screen = screen; + rctx->context.priv = priv; + rctx->context.destroy = r600_destroy_context; + rctx->context.clear = r600_clear; + rctx->context.surface_copy = r600_surface_copy; + rctx->context.surface_fill = r600_surface_fill; + rctx->context.draw_arrays = r600_draw_arrays; + rctx->context.draw_elements = r600_draw_elements; + rctx->context.draw_range_elements = r600_draw_range_elements; + rctx->context.is_texture_referenced = r600_is_texture_referenced; + rctx->context.is_buffer_referenced = r600_is_buffer_referenced; + rctx->context.flush = r600_flush; + r600_init_query_functions(rctx); + r600_init_state_functions(rctx); +#if 0 + rctx->blitter = util_blitter_create(&rctx->context); + if (rctx->blitter == NULL) { + FREE(rctx); + return NULL; + } +#endif + + rctx->cb_cntl = radeon_state(rscreen->rw, R600_CB_CNTL_TYPE, R600_CB_CNTL); + rctx->cb_cntl->states[R600_CB_CNTL__CB_SHADER_MASK] = 0x0000000F; + rctx->cb_cntl->states[R600_CB_CNTL__CB_TARGET_MASK] = 0x0000000F; + rctx->cb_cntl->states[R600_CB_CNTL__CB_COLOR_CONTROL] = 0x00CC0000; + rctx->cb_cntl->states[R600_CB_CNTL__PA_SC_AA_CONFIG] = 0x00000000; + rctx->cb_cntl->states[R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_MCTX] = 0x00000000; + rctx->cb_cntl->states[R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX] = 0x00000000; + rctx->cb_cntl->states[R600_CB_CNTL__CB_CLRCMP_CONTROL] = 0x01000000; + rctx->cb_cntl->states[R600_CB_CNTL__CB_CLRCMP_SRC] = 0x00000000; + rctx->cb_cntl->states[R600_CB_CNTL__CB_CLRCMP_DST] = 0x000000FF; + rctx->cb_cntl->states[R600_CB_CNTL__CB_CLRCMP_MSK] = 0xFFFFFFFF; + rctx->cb_cntl->states[R600_CB_CNTL__PA_SC_AA_MASK] = 0xFFFFFFFF; + radeon_state_pm4(rctx->cb_cntl); + + rctx->config = radeon_state(rscreen->rw, R600_CONFIG_TYPE, R600_CONFIG); + rctx->config->states[R600_CONFIG__SQ_CONFIG] = 0xE400000C; + rctx->config->states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] = 0x403800C0; + rctx->config->states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2] = 0x00000000; + rctx->config->states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] = 0x00003090; + rctx->config->states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1] = 0x00800080; + rctx->config->states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2] = 0x00000000; + rctx->config->states[R600_CONFIG__SQ_DYN_GPR_CNTL_PS_FLUSH_REQ] = 0x00004000; + rctx->config->states[R600_CONFIG__TA_CNTL_AUX] = 0x07000002; + rctx->config->states[R600_CONFIG__VC_ENHANCE] = 0x00000000; + rctx->config->states[R600_CONFIG__DB_DEBUG] = 0x00000000; + rctx->config->states[R600_CONFIG__DB_WATERMARKS] = 0x00420204; + rctx->config->states[R600_CONFIG__SX_MISC] = 0x00000000; + rctx->config->states[R600_CONFIG__SPI_THREAD_GROUPING] = 0x00000001; + rctx->config->states[R600_CONFIG__CB_SHADER_CONTROL] = 0x00000003; + rctx->config->states[R600_CONFIG__SQ_ESGS_RING_ITEMSIZE] = 0x00000000; + rctx->config->states[R600_CONFIG__SQ_GSVS_RING_ITEMSIZE] = 0x00000000; + rctx->config->states[R600_CONFIG__SQ_ESTMP_RING_ITEMSIZE] = 0x00000000; + rctx->config->states[R600_CONFIG__SQ_GSTMP_RING_ITEMSIZE] = 0x00000000; + rctx->config->states[R600_CONFIG__SQ_VSTMP_RING_ITEMSIZE] = 0x00000000; + rctx->config->states[R600_CONFIG__SQ_PSTMP_RING_ITEMSIZE] = 0x00000000; + rctx->config->states[R600_CONFIG__SQ_FBUF_RING_ITEMSIZE] = 0x00000000; + rctx->config->states[R600_CONFIG__SQ_REDUC_RING_ITEMSIZE] = 0x00000000; + rctx->config->states[R600_CONFIG__SQ_GS_VERT_ITEMSIZE] = 0x00000000; + rctx->config->states[R600_CONFIG__VGT_OUTPUT_PATH_CNTL] = 0x00000000; + rctx->config->states[R600_CONFIG__VGT_HOS_CNTL] = 0x00000000; + rctx->config->states[R600_CONFIG__VGT_HOS_MAX_TESS_LEVEL] = 0x00000000; + rctx->config->states[R600_CONFIG__VGT_HOS_MIN_TESS_LEVEL] = 0x00000000; + rctx->config->states[R600_CONFIG__VGT_HOS_REUSE_DEPTH] = 0x00000000; + rctx->config->states[R600_CONFIG__VGT_GROUP_PRIM_TYPE] = 0x00000000; + rctx->config->states[R600_CONFIG__VGT_GROUP_FIRST_DECR] = 0x00000000; + rctx->config->states[R600_CONFIG__VGT_GROUP_DECR] = 0x00000000; + rctx->config->states[R600_CONFIG__VGT_GROUP_VECT_0_CNTL] = 0x00000000; + rctx->config->states[R600_CONFIG__VGT_GROUP_VECT_1_CNTL] = 0x00000000; + rctx->config->states[R600_CONFIG__VGT_GROUP_VECT_0_FMT_CNTL] = 0x00000000; + rctx->config->states[R600_CONFIG__VGT_GROUP_VECT_1_FMT_CNTL] = 0x00000000; + rctx->config->states[R600_CONFIG__VGT_GS_MODE] = 0x00000000; + rctx->config->states[R600_CONFIG__PA_SC_MODE_CNTL] = 0x00514000; + rctx->config->states[R600_CONFIG__VGT_STRMOUT_EN] = 0x00000000; + rctx->config->states[R600_CONFIG__VGT_REUSE_OFF] = 0x00000001; + rctx->config->states[R600_CONFIG__VGT_VTX_CNT_EN] = 0x00000000; + rctx->config->states[R600_CONFIG__VGT_STRMOUT_BUFFER_EN] = 0x00000000; + radeon_state_pm4(rctx->config); + + rctx->ctx = radeon_ctx(rscreen->rw); + rctx->draw = radeon_draw(rscreen->rw); + return &rctx->context; +} diff --git a/src/gallium/drivers/r600/r600_context.h b/src/gallium/drivers/r600/r600_context.h new file mode 100644 index 00000000000..4646df3b56f --- /dev/null +++ b/src/gallium/drivers/r600/r600_context.h @@ -0,0 +1,101 @@ +/* + * Copyright 2010 Jerome Glisse <[email protected]> + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef R600_CONTEXT_H +#define R600_CONTEXT_H + +#include <pipe/p_state.h> +#include <pipe/p_context.h> +#include <tgsi/tgsi_scan.h> +#include <tgsi/tgsi_parse.h> +#include <tgsi/tgsi_util.h> +#include <util/u_blitter.h> +#include "radeon.h" +#include "r600_shader.h" + +struct r600_state; +typedef void (*r600_state_destroy_t)(struct r600_state *rstate); + +struct r600_state { + unsigned type; + struct r600_atom *atom; + void *state; + unsigned nbuffers; + struct pipe_buffer *buffer[256]; + unsigned nsurfaces; + struct pipe_surface *surface[256]; + r600_state_destroy_t destroy; +}; + +struct r600_pipe_shader { + unsigned type; + struct r600_shader shader; + struct radeon_bo *bo; + struct radeon_state *state; +}; + +struct r600_context { + struct pipe_context context; + struct radeon_ctx *ctx; + struct radeon_state *cb_cntl; + struct radeon_state *db; + struct radeon_state *config; + struct r600_pipe_shader *ps_shader; + struct r600_pipe_shader *vs_shader; + unsigned flat_shade; + unsigned nvertex_buffer; + unsigned nvertex_element; + struct pipe_vertex_buffer vertex_buffer[PIPE_MAX_ATTRIBS]; + struct pipe_vertex_element vertex_element[PIPE_MAX_ATTRIBS]; + struct blitter_context *blitter; + struct pipe_stencil_ref stencil_ref; + struct pipe_framebuffer_state fb_state; + struct radeon_draw *draw; +}; + +void r600_draw_arrays(struct pipe_context *ctx, unsigned mode, + unsigned start, unsigned count); +void r600_draw_elements(struct pipe_context *ctx, + struct pipe_buffer *index_buffer, + unsigned index_size, unsigned mode, + unsigned start, unsigned count); +void r600_draw_range_elements(struct pipe_context *ctx, + struct pipe_buffer *index_buffer, + unsigned indexSize, unsigned minIndex, + unsigned maxIndex, unsigned mode, + unsigned start, unsigned count); + +void r600_state_destroy_common(struct r600_state *state); +struct r600_state *r600_state_new(r600_state_destroy_t destroy); +struct r600_state *r600_state_destroy(struct r600_state *state); + +void r600_init_state_functions(struct r600_context *rctx); +void r600_init_query_functions(struct r600_context* rctx); +struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv); + +void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *rpshader); +struct r600_pipe_shader *r600_pipe_shader_create(struct pipe_context *ctx, + unsigned type, + const struct tgsi_token *tokens); +int r600_pipe_shader_update(struct pipe_context *ctx, struct r600_pipe_shader *rpshader); + +#endif diff --git a/src/gallium/drivers/r600/r600_draw.c b/src/gallium/drivers/r600/r600_draw.c new file mode 100644 index 00000000000..b9037963117 --- /dev/null +++ b/src/gallium/drivers/r600/r600_draw.c @@ -0,0 +1,215 @@ +/* + * Copyright 2010 Jerome Glisse <[email protected]> + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Jerome Glisse + * Corbin Simpson + */ +#include <stdio.h> +#include <errno.h> +#include <pipe/p_screen.h> +#include <util/u_format.h> +#include <util/u_math.h> +#include <util/u_inlines.h> +#include <util/u_memory.h> +#include "r600_screen.h" +#include "r600_context.h" +#include "r600d.h" + +struct r600_draw { + struct pipe_context *ctx; + struct radeon_state *draw; + struct radeon_state *vgt; + unsigned mode; + unsigned start; + unsigned count; + unsigned index_size; + struct pipe_buffer *index_buffer; +}; + +static int r600_draw_common(struct r600_draw *draw) +{ + struct r600_context *rctx = (struct r600_context*)draw->ctx; + struct r600_screen *rscreen = (struct r600_screen*)draw->ctx->screen; + struct radeon_state *vs_resource; + struct r600_pipe_buffer *rbuffer; + unsigned i, j, offset, format, prim; + u32 vgt_dma_index_type, vgt_draw_initiator; + int r; + + switch (draw->index_size) { + case 2: + vgt_draw_initiator = 0; + vgt_dma_index_type = 0; + break; + case 4: + vgt_draw_initiator = 0; + vgt_dma_index_type = 1; + break; + case 0: + vgt_draw_initiator = 2; + vgt_dma_index_type = 0; + break; + default: + fprintf(stderr, "%s %d unsupported index size %d\n", __func__, __LINE__, draw->index_size); + return -EINVAL; + } + r = r600_conv_pipe_prim(draw->mode, &prim); + if (r) + return r; + /* rebuild vertex shader if input format changed */ + r = r600_pipe_shader_update(draw->ctx, rctx->vs_shader); + if (r) + return r; + r = r600_pipe_shader_update(draw->ctx, rctx->ps_shader); + if (r) + return r; + r = radeon_draw_set(rctx->draw, rctx->vs_shader->state); + if (r) + return r; + r = radeon_draw_set(rctx->draw, rctx->ps_shader->state); + if (r) + return r; + r = radeon_draw_set(rctx->draw, rctx->cb_cntl); + if (r) + return r; + r = radeon_draw_set(rctx->draw, rctx->db); + if (r) + return r; + r = radeon_draw_set(rctx->draw, rctx->config); + if (r) + return r; + + for (i = 0 ; i < rctx->nvertex_element; i++) { + j = rctx->vertex_element[i].vertex_buffer_index; + rbuffer = (struct r600_pipe_buffer*)rctx->vertex_buffer[j].buffer; + offset = rctx->vertex_element[i].src_offset + rctx->vertex_buffer[j].buffer_offset; + r = r600_conv_pipe_format(rctx->vertex_element[i].src_format, &format); + if (r) + return r; + vs_resource = radeon_state(rscreen->rw, R600_VS_RESOURCE_TYPE, R600_VS_RESOURCE + i); + if (vs_resource == NULL) + return -ENOMEM; + vs_resource->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo); + vs_resource->nbo = 1; + vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD0] = offset; + vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD1] = rbuffer->bo->size - offset; + vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD2] = S_038008_STRIDE(rctx->vertex_buffer[j].stride) | + S_038008_DATA_FORMAT(format); + vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD3] = 0x00000000; + vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD4] = 0x00000000; + vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD5] = 0x00000000; + vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD6] = 0xC0000000; + vs_resource->placement[0] = RADEON_GEM_DOMAIN_GTT; + vs_resource->placement[1] = RADEON_GEM_DOMAIN_GTT; + r = radeon_draw_set_new(rctx->draw, vs_resource); + if (r) + return r; + } + /* FIXME start need to change winsys */ + draw->draw = radeon_state(rscreen->rw, R600_DRAW_TYPE, R600_DRAW); + if (draw->draw == NULL) + return -ENOMEM; + draw->draw->states[R600_DRAW__VGT_NUM_INDICES] = draw->count; + draw->draw->states[R600_DRAW__VGT_DRAW_INITIATOR] = vgt_draw_initiator; + if (draw->index_buffer) { + rbuffer = (struct r600_pipe_buffer*)draw->index_buffer; + draw->draw->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo); + draw->draw->placement[0] = RADEON_GEM_DOMAIN_GTT; + draw->draw->placement[1] = RADEON_GEM_DOMAIN_GTT; + draw->draw->nbo = 1; + } + r = radeon_draw_set_new(rctx->draw, draw->draw); + if (r) + return r; + draw->vgt = radeon_state(rscreen->rw, R600_VGT_TYPE, R600_VGT); + if (draw->vgt == NULL) + return -ENOMEM; + draw->vgt->states[R600_VGT__VGT_PRIMITIVE_TYPE] = prim; + draw->vgt->states[R600_VGT__VGT_MAX_VTX_INDX] = 0x00FFFFFF; + draw->vgt->states[R600_VGT__VGT_MIN_VTX_INDX] = 0x00000000; + draw->vgt->states[R600_VGT__VGT_INDX_OFFSET] = draw->start; + draw->vgt->states[R600_VGT__VGT_MULTI_PRIM_IB_RESET_INDX] = 0x00000000; + draw->vgt->states[R600_VGT__VGT_DMA_INDEX_TYPE] = vgt_dma_index_type; + draw->vgt->states[R600_VGT__VGT_PRIMITIVEID_EN] = 0x00000000; + draw->vgt->states[R600_VGT__VGT_DMA_NUM_INSTANCES] = 0x00000001; + draw->vgt->states[R600_VGT__VGT_MULTI_PRIM_IB_RESET_EN] = 0x00000000; + draw->vgt->states[R600_VGT__VGT_INSTANCE_STEP_RATE_0] = 0x00000000; + draw->vgt->states[R600_VGT__VGT_INSTANCE_STEP_RATE_1] = 0x00000000; + r = radeon_draw_set_new(rctx->draw, draw->vgt); + if (r) + return r; + /* FIXME */ + r = radeon_ctx_set_draw_new(rctx->ctx, rctx->draw); + if (r) + return r; + rctx->draw = radeon_draw_duplicate(rctx->draw); + return 0; +} + +void r600_draw_range_elements(struct pipe_context *ctx, + struct pipe_buffer *index_buffer, + unsigned index_size, unsigned min_index, + unsigned max_index, unsigned mode, + unsigned start, unsigned count) +{ + struct r600_draw draw; + + draw.ctx = ctx; + draw.mode = mode; + draw.start = start; + draw.count = count; + draw.index_size = index_size; + draw.index_buffer = index_buffer; +printf("index_size %d min %d max %d start %d count %d\n", index_size, min_index, max_index, start, count); + r600_draw_common(&draw); +} + +void r600_draw_elements(struct pipe_context *ctx, + struct pipe_buffer *index_buffer, + unsigned index_size, unsigned mode, + unsigned start, unsigned count) +{ + struct r600_draw draw; + + draw.ctx = ctx; + draw.mode = mode; + draw.start = start; + draw.count = count; + draw.index_size = index_size; + draw.index_buffer = index_buffer; + r600_draw_common(&draw); +} + +void r600_draw_arrays(struct pipe_context *ctx, unsigned mode, + unsigned start, unsigned count) +{ + struct r600_draw draw; + + draw.ctx = ctx; + draw.mode = mode; + draw.start = start; + draw.count = count; + draw.index_size = 0; + draw.index_buffer = NULL; + r600_draw_common(&draw); +} diff --git a/src/gallium/drivers/r600/r600_helper.c b/src/gallium/drivers/r600/r600_helper.c new file mode 100644 index 00000000000..7757452104e --- /dev/null +++ b/src/gallium/drivers/r600/r600_helper.c @@ -0,0 +1,176 @@ +/* + * Copyright 2010 Jerome Glisse <[email protected]> + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Jerome Glisse + */ +#include <stdio.h> +#include <errno.h> +#include <util/u_inlines.h> +#include <util/u_format.h> +#include <util/u_memory.h> +#include "r600_screen.h" +#include "r600d.h" + +int r600_conv_pipe_format(unsigned pformat, unsigned *format) +{ + switch (pformat) { + case PIPE_FORMAT_R32G32B32_FLOAT: + *format = 0x30; + return 0; + case PIPE_FORMAT_R32G32B32A32_FLOAT: + *format = V_0280A0_COLOR_32_32_32_32_FLOAT; + return 0; + case PIPE_FORMAT_A8R8G8B8_UNORM: + case PIPE_FORMAT_X8R8G8B8_UNORM: + case PIPE_FORMAT_B8G8R8A8_UNORM: + case PIPE_FORMAT_B8G8R8X8_UNORM: + case PIPE_FORMAT_R8G8B8A8_UNORM: + case PIPE_FORMAT_R8G8B8X8_UNORM: + case PIPE_FORMAT_R8G8B8A8_USCALED: + case PIPE_FORMAT_R8G8B8X8_USCALED: + case PIPE_FORMAT_R8G8B8A8_SNORM: + case PIPE_FORMAT_R8G8B8X8_SNORM: + case PIPE_FORMAT_A8B8G8R8_SNORM: + case PIPE_FORMAT_X8B8G8R8_SNORM: + case PIPE_FORMAT_R8G8B8A8_SSCALED: + case PIPE_FORMAT_R8G8B8X8_SSCALED: + *format = V_0280A0_COLOR_8_8_8_8; + return 0; + case PIPE_FORMAT_A1R5G5B5_UNORM: + case PIPE_FORMAT_A4R4G4B4_UNORM: + case PIPE_FORMAT_R5G6B5_UNORM: + case PIPE_FORMAT_A2B10G10R10_UNORM: + case PIPE_FORMAT_L8_UNORM: + case PIPE_FORMAT_A8_UNORM: + case PIPE_FORMAT_I8_UNORM: + case PIPE_FORMAT_A8L8_UNORM: + case PIPE_FORMAT_L16_UNORM: + case PIPE_FORMAT_YCBCR: + case PIPE_FORMAT_YCBCR_REV: + case PIPE_FORMAT_Z16_UNORM: + case PIPE_FORMAT_Z32_UNORM: + case PIPE_FORMAT_Z32_FLOAT: + case PIPE_FORMAT_S8Z24_UNORM: + case PIPE_FORMAT_Z24S8_UNORM: + case PIPE_FORMAT_X8Z24_UNORM: + case PIPE_FORMAT_Z24X8_UNORM: + case PIPE_FORMAT_S8_UNORM: + case PIPE_FORMAT_R64_FLOAT: + case PIPE_FORMAT_R64G64_FLOAT: + case PIPE_FORMAT_R64G64B64_FLOAT: + case PIPE_FORMAT_R64G64B64A64_FLOAT: + case PIPE_FORMAT_R32_FLOAT: + case PIPE_FORMAT_R32G32_FLOAT: + case PIPE_FORMAT_R32_UNORM: + case PIPE_FORMAT_R32G32_UNORM: + case PIPE_FORMAT_R32G32B32_UNORM: + case PIPE_FORMAT_R32G32B32A32_UNORM: + case PIPE_FORMAT_R32_USCALED: + case PIPE_FORMAT_R32G32_USCALED: + case PIPE_FORMAT_R32G32B32_USCALED: + case PIPE_FORMAT_R32G32B32A32_USCALED: + case PIPE_FORMAT_R32_SNORM: + case PIPE_FORMAT_R32G32_SNORM: + case PIPE_FORMAT_R32G32B32_SNORM: + case PIPE_FORMAT_R32G32B32A32_SNORM: + case PIPE_FORMAT_R32_SSCALED: + case PIPE_FORMAT_R32G32_SSCALED: + case PIPE_FORMAT_R32G32B32_SSCALED: + case PIPE_FORMAT_R32G32B32A32_SSCALED: + case PIPE_FORMAT_R16_UNORM: + case PIPE_FORMAT_R16G16_UNORM: + case PIPE_FORMAT_R16G16B16_UNORM: + case PIPE_FORMAT_R16G16B16A16_UNORM: + case PIPE_FORMAT_R16_USCALED: + case PIPE_FORMAT_R16G16_USCALED: + case PIPE_FORMAT_R16G16B16_USCALED: + case PIPE_FORMAT_R16G16B16A16_USCALED: + case PIPE_FORMAT_R16_SNORM: + case PIPE_FORMAT_R16G16_SNORM: + case PIPE_FORMAT_R16G16B16_SNORM: + case PIPE_FORMAT_R16G16B16A16_SNORM: + case PIPE_FORMAT_R16_SSCALED: + case PIPE_FORMAT_R16G16_SSCALED: + case PIPE_FORMAT_R16G16B16_SSCALED: + case PIPE_FORMAT_R16G16B16A16_SSCALED: + case PIPE_FORMAT_R8_UNORM: + case PIPE_FORMAT_R8G8_UNORM: + case PIPE_FORMAT_R8G8B8_UNORM: + case PIPE_FORMAT_R8_USCALED: + case PIPE_FORMAT_R8G8_USCALED: + case PIPE_FORMAT_R8G8B8_USCALED: + case PIPE_FORMAT_R8_SNORM: + case PIPE_FORMAT_R8G8_SNORM: + case PIPE_FORMAT_R8G8B8_SNORM: + case PIPE_FORMAT_B6G5R5_SNORM: + case PIPE_FORMAT_R8_SSCALED: + case PIPE_FORMAT_R8G8_SSCALED: + case PIPE_FORMAT_R8G8B8_SSCALED: + case PIPE_FORMAT_R32_FIXED: + case PIPE_FORMAT_R32G32_FIXED: + case PIPE_FORMAT_R32G32B32_FIXED: + case PIPE_FORMAT_R32G32B32A32_FIXED: + default: + fprintf(stderr, "%s:%d unsupported %d\n", __func__, __LINE__, pformat); + return -EINVAL; + } +} + +int r600_conv_pipe_prim(unsigned pprim, unsigned *prim) +{ + switch (pprim) { + case PIPE_PRIM_POINTS: + *prim = V_008958_DI_PT_POINTLIST; + return 0; + case PIPE_PRIM_LINES: + *prim = V_008958_DI_PT_LINELIST; + return 0; + case PIPE_PRIM_LINE_STRIP: + *prim = V_008958_DI_PT_LINESTRIP; + return 0; + case PIPE_PRIM_LINE_LOOP: + *prim = V_008958_DI_PT_LINELOOP; + return 0; + case PIPE_PRIM_TRIANGLES: + *prim = V_008958_DI_PT_TRILIST; + return 0; + case PIPE_PRIM_TRIANGLE_STRIP: + *prim = V_008958_DI_PT_TRISTRIP; + return 0; + case PIPE_PRIM_TRIANGLE_FAN: + *prim = V_008958_DI_PT_TRIFAN; + return 0; + case PIPE_PRIM_POLYGON: + *prim = V_008958_DI_PT_POLYGON; + return 0; + case PIPE_PRIM_QUADS: + *prim = V_008958_DI_PT_QUADLIST; + return 0; + case PIPE_PRIM_QUAD_STRIP: + *prim = V_008958_DI_PT_QUADSTRIP; + return 0; + default: + fprintf(stderr, "%s:%d unsupported %d\n", __func__, __LINE__, pprim); + return -EINVAL; + } +} diff --git a/src/gallium/drivers/r600/r600_query.c b/src/gallium/drivers/r600/r600_query.c new file mode 100644 index 00000000000..3101141278d --- /dev/null +++ b/src/gallium/drivers/r600/r600_query.c @@ -0,0 +1,66 @@ +/* + * Copyright 2010 Jerome Glisse <[email protected]> + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Jerome Glisse + * Corbin Simpson + */ +#include <util/u_inlines.h> +#include <util/u_format.h> +#include <util/u_memory.h> +#include "r600_screen.h" +#include "r600_texture.h" +#include "r600_context.h" + +static struct pipe_query *r600_create_query(struct pipe_context *pipe, unsigned query_type) +{ + return NULL; +} + +static void r600_destroy_query(struct pipe_context *pipe, struct pipe_query *query) +{ + FREE(query); +} + +static void r600_begin_query(struct pipe_context *pipe, struct pipe_query *query) +{ +} + +static void r600_end_query(struct pipe_context *pipe, struct pipe_query *query) +{ +} + +static boolean r600_get_query_result(struct pipe_context *pipe, + struct pipe_query *query, + boolean wait, uint64_t *result) +{ + return TRUE; +} + +void r600_init_query_functions(struct r600_context* rctx) +{ + rctx->context.create_query = r600_create_query; + rctx->context.destroy_query = r600_destroy_query; + rctx->context.begin_query = r600_begin_query; + rctx->context.end_query = r600_end_query; + rctx->context.get_query_result = r600_get_query_result; +} diff --git a/src/gallium/drivers/r600/r600_screen.c b/src/gallium/drivers/r600/r600_screen.c new file mode 100644 index 00000000000..db17b88e9ac --- /dev/null +++ b/src/gallium/drivers/r600/r600_screen.c @@ -0,0 +1,241 @@ +/* + * Copyright 2010 Jerome Glisse <[email protected]> + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Jerome Glisse + * Corbin Simpson + */ +#include <util/u_inlines.h> +#include <util/u_format.h> +#include <util/u_memory.h> +#include "r600_screen.h" +#include "r600_texture.h" +#include "r600_context.h" + +static const char* r600_get_vendor(struct pipe_screen* pscreen) +{ + return "X.Org"; +} + +static const char* r600_get_name(struct pipe_screen* pscreen) +{ + return "R600"; +} + +static int r600_get_param(struct pipe_screen* pscreen, int param) +{ + switch (param) { + case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS: + case PIPE_CAP_MAX_COMBINED_SAMPLERS: + return 16; + case PIPE_CAP_NPOT_TEXTURES: + return 1; + case PIPE_CAP_TWO_SIDED_STENCIL: + return 1; + case PIPE_CAP_GLSL: + return 1; + case PIPE_CAP_DUAL_SOURCE_BLEND: + return 1; + case PIPE_CAP_ANISOTROPIC_FILTER: + return 1; + case PIPE_CAP_POINT_SPRITE: + return 1; + case PIPE_CAP_MAX_RENDER_TARGETS: + /* FIXME some r6xx are buggy and can only do 4 */ + return 8; + case PIPE_CAP_OCCLUSION_QUERY: + return 1; + case PIPE_CAP_TEXTURE_SHADOW_MAP: + return 1; + case PIPE_CAP_MAX_TEXTURE_2D_LEVELS: + case PIPE_CAP_MAX_TEXTURE_3D_LEVELS: + case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS: + /* FIXME not sure here */ + return 13; + case PIPE_CAP_TEXTURE_MIRROR_CLAMP: + return 1; + case PIPE_CAP_TEXTURE_MIRROR_REPEAT: + return 1; + case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS: + /* FIXME allow this once infrastructure is there */ + return 0; + case PIPE_CAP_TGSI_CONT_SUPPORTED: + return 0; + case PIPE_CAP_BLEND_EQUATION_SEPARATE: + return 1; + case PIPE_CAP_SM3: + return 1; + case PIPE_CAP_INDEP_BLEND_ENABLE: + return 1; + case PIPE_CAP_INDEP_BLEND_FUNC: + /* FIXME allow this */ + return 0; + case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT: + case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER: + return 1; + case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT: + case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER: + return 0; + default: + debug_printf("r600: unknown param %d\n", param); + return 0; + } +} + +static float r600_get_paramf(struct pipe_screen* pscreen, int param) +{ + switch (param) { + case PIPE_CAP_MAX_LINE_WIDTH: + case PIPE_CAP_MAX_LINE_WIDTH_AA: + case PIPE_CAP_MAX_POINT_WIDTH: + case PIPE_CAP_MAX_POINT_WIDTH_AA: + return 8192.0f; + case PIPE_CAP_MAX_TEXTURE_ANISOTROPY: + return 16.0f; + case PIPE_CAP_MAX_TEXTURE_LOD_BIAS: + return 16.0f; + default: + debug_printf("r600: unsupported paramf %d\n", param); + return 0.0f; + } +} + +static boolean r600_is_format_supported(struct pipe_screen* screen, + enum pipe_format format, + enum pipe_texture_target target, + unsigned usage, + unsigned geom_flags) +{ + if (target >= PIPE_MAX_TEXTURE_TYPES) { + debug_printf("r600: unsupported texture type %d\n", target); + return FALSE; + } + switch (format) { + case PIPE_FORMAT_A4R4G4B4_UNORM: + case PIPE_FORMAT_R5G6B5_UNORM: + case PIPE_FORMAT_A1R5G5B5_UNORM: + case PIPE_FORMAT_A8_UNORM: + case PIPE_FORMAT_L8_UNORM: + case PIPE_FORMAT_A8R8G8B8_SRGB: + case PIPE_FORMAT_R8G8B8A8_SRGB: + case PIPE_FORMAT_DXT1_RGB: + case PIPE_FORMAT_DXT1_RGBA: + case PIPE_FORMAT_DXT3_RGBA: + case PIPE_FORMAT_DXT5_RGBA: + case PIPE_FORMAT_YCBCR: + case PIPE_FORMAT_L8_SRGB: + case PIPE_FORMAT_A8L8_SRGB: + case PIPE_FORMAT_A8L8_UNORM: + case PIPE_FORMAT_A8R8G8B8_UNORM: + case PIPE_FORMAT_X8R8G8B8_UNORM: + case PIPE_FORMAT_R8G8B8A8_UNORM: + case PIPE_FORMAT_R8G8B8X8_UNORM: + case PIPE_FORMAT_I8_UNORM: + case PIPE_FORMAT_Z16_UNORM: + case PIPE_FORMAT_Z24X8_UNORM: + case PIPE_FORMAT_Z24S8_UNORM: + case PIPE_FORMAT_Z32_UNORM: + case PIPE_FORMAT_S8Z24_UNORM: + case PIPE_FORMAT_X8Z24_UNORM: + return TRUE; + default: + /* Unknown format... */ + break; + } + return FALSE; +} + +static struct pipe_transfer* r600_get_tex_transfer(struct pipe_screen *screen, + struct pipe_texture *texture, + unsigned face, unsigned level, + unsigned zslice, + enum pipe_transfer_usage usage, + unsigned x, unsigned y, + unsigned w, unsigned h) +{ + struct r600_texture *rtex = (struct r600_texture*)texture; + struct r600_transfer *trans; + + trans = CALLOC_STRUCT(r600_transfer); + if (trans == NULL) + return NULL; + pipe_texture_reference(&trans->transfer.texture, texture); + trans->transfer.x = x; + trans->transfer.y = y; + trans->transfer.width = w; + trans->transfer.height = h; + trans->transfer.stride = rtex->stride[level]; + trans->transfer.usage = usage; + trans->transfer.zslice = zslice; + trans->transfer.face = face; + trans->offset = r600_texture_get_offset(rtex, level, zslice, face); + return &trans->transfer; +} + +static void r600_tex_transfer_destroy(struct pipe_transfer *trans) +{ +} + +static void* r600_transfer_map(struct pipe_screen* screen, struct pipe_transfer* transfer) +{ + /* FIXME implement */ + return NULL; +} + +static void r600_transfer_unmap(struct pipe_screen* screen, struct pipe_transfer* transfer) +{ +} + +static void r600_destroy_screen(struct pipe_screen* pscreen) +{ + struct r600_screen* rscreen = r600_screen(pscreen); + + if (rscreen == NULL) + return; + FREE(rscreen); +} + +struct pipe_screen *radeon_create_screen(struct radeon *rw) +{ + struct r600_screen* rscreen; + + rscreen = CALLOC_STRUCT(r600_screen); + if (rscreen == NULL) { + return NULL; + } + rscreen->rw = rw; + rscreen->screen.winsys = (struct pipe_winsys*)rw; + rscreen->screen.destroy = r600_destroy_screen; + rscreen->screen.get_name = r600_get_name; + rscreen->screen.get_vendor = r600_get_vendor; + rscreen->screen.get_param = r600_get_param; + rscreen->screen.get_paramf = r600_get_paramf; + rscreen->screen.is_format_supported = r600_is_format_supported; + rscreen->screen.context_create = r600_create_context; + rscreen->screen.get_tex_transfer = r600_get_tex_transfer; + rscreen->screen.tex_transfer_destroy = r600_tex_transfer_destroy; + rscreen->screen.transfer_map = r600_transfer_map; + rscreen->screen.transfer_unmap = r600_transfer_unmap; + r600_screen_init_buffer_functions(&rscreen->screen); + r600_init_screen_texture_functions(&rscreen->screen); + return &rscreen->screen; +} diff --git a/src/gallium/drivers/r600/r600_screen.h b/src/gallium/drivers/r600/r600_screen.h new file mode 100644 index 00000000000..97d57c027ed --- /dev/null +++ b/src/gallium/drivers/r600/r600_screen.h @@ -0,0 +1,88 @@ +/* + * Copyright 2010 Jerome Glisse <[email protected]> + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef R600_SCREEN_H +#define R600_SCREEN_H + +#include <pipe/p_state.h> +#include <pipe/p_screen.h> +#include <pipebuffer/pb_buffer.h> +#include <xf86drm.h> +#include <radeon_drm.h> +#include "radeon.h" + +#define r600_screen(s) ((struct r600_screen*)s) + +struct r600_transfer { + struct pipe_transfer transfer; + unsigned offset; +}; + +struct r600_pipe_buffer { + struct pipe_buffer base; + struct radeon_bo *bo; + u32 domain; + u32 flink; + struct pb_buffer *pb; +}; + +struct r600_screen { + struct pipe_screen screen; + struct radeon *rw; +}; + +void r600_screen_init_buffer_functions(struct pipe_screen *screen); +void r600_clear(struct pipe_context *ctx, + unsigned buffers, + const float *rgba, + double depth, + unsigned stencil); +void r600_surface_copy(struct pipe_context *ctx, + struct pipe_surface *dst, + unsigned dstx, unsigned dsty, + struct pipe_surface *src, + unsigned srcx, unsigned srcy, + unsigned width, unsigned height); +void r600_surface_fill(struct pipe_context *ctx, + struct pipe_surface *dst, + unsigned dstx, unsigned dsty, + unsigned width, unsigned height, + unsigned value); + +/* helpers */ +int r600_conv_pipe_format(unsigned pformat, unsigned *format); +int r600_conv_pipe_prim(unsigned pprim, unsigned *prim); + +union r600_float_to_u32_u { + u32 u; + float f; +}; + +static inline u32 r600_float_to_u32(float f) +{ + union r600_float_to_u32_u c; + + c.f = f; + return c.u; +} + +#endif diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c new file mode 100644 index 00000000000..f8a18658a98 --- /dev/null +++ b/src/gallium/drivers/r600/r600_shader.c @@ -0,0 +1,218 @@ +/* + * Copyright 2010 Jerome Glisse <[email protected]> + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Jerome Glisse + */ +#include <stdio.h> +#include <errno.h> +#include <util/u_inlines.h> +#include <util/u_format.h> +#include <util/u_memory.h> +#include <tgsi/tgsi_dump.h> +#include "r600_screen.h" +#include "r600_texture.h" +#include "r600_context.h" +#include "r600d.h" + +static int r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *rpshader) +{ + struct r600_screen *rscreen = (struct r600_screen*)ctx->screen; + struct r600_shader *rshader = &rpshader->shader; + struct radeon_state *state; + unsigned i, tmp; + + rpshader->state = radeon_state_decref(rpshader->state); + state = radeon_state(rscreen->rw, R600_VS_SHADER_TYPE, R600_VS_SHADER); + if (state == NULL) + return -ENOMEM; + for (i = 0; i < rshader->noutput; i += 4) { + tmp = rshader->output[i].sid; + tmp |= rshader->output[i + 1].sid << 8; + tmp |= rshader->output[i + 2].sid << 16; + tmp |= rshader->output[i + 3].sid << 24; + state->states[R600_VS_SHADER__SPI_VS_OUT_ID_0 + i / 4] = tmp; + } + state->states[R600_VS_SHADER__SPI_VS_OUT_CONFIG] = S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 1); + state->states[R600_VS_SHADER__SQ_PGM_RESOURCES_VS] = S_028868_NUM_GPRS(rshader->ngpr); + rpshader->state = state; + rpshader->state->bo[0] = radeon_bo_incref(rscreen->rw, rpshader->bo); + rpshader->state->bo[1] = radeon_bo_incref(rscreen->rw, rpshader->bo); + rpshader->state->nbo = 2; + rpshader->state->placement[0] = RADEON_GEM_DOMAIN_GTT; + return radeon_state_pm4(state); +} + +static int r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *rpshader) +{ + struct r600_screen *rscreen = (struct r600_screen*)ctx->screen; + struct r600_shader *rshader = &rpshader->shader; + struct radeon_state *state; + unsigned i, tmp; + + rpshader->state = radeon_state_decref(rpshader->state); + state = radeon_state(rscreen->rw, R600_PS_SHADER_TYPE, R600_PS_SHADER); + if (state == NULL) + return -ENOMEM; + for (i = 0; i < rshader->ninput; i++) { + tmp = S_028644_SEMANTIC(rshader->input[i].sid); + tmp |= S_028644_SEL_CENTROID(1); + tmp |= S_028644_FLAT_SHADE(rshader->flat_shade); + state->states[R600_PS_SHADER__SPI_PS_INPUT_CNTL_0 + i] = tmp; + } + state->states[R600_PS_SHADER__SPI_PS_IN_CONTROL_0] = S_0286CC_NUM_INTERP(rshader->ninput) | + S_0286CC_PERSP_GRADIENT_ENA(1); + state->states[R600_PS_SHADER__SPI_PS_IN_CONTROL_1] = 0x00000000; + state->states[R600_PS_SHADER__SQ_PGM_RESOURCES_PS] = S_028868_NUM_GPRS(rshader->ngpr); + state->states[R600_PS_SHADER__SQ_PGM_EXPORTS_PS] = 0x00000002; + rpshader->state = state; + rpshader->state->bo[0] = radeon_bo_incref(rscreen->rw, rpshader->bo); + rpshader->state->nbo = 1; + rpshader->state->placement[0] = RADEON_GEM_DOMAIN_GTT; + return radeon_state_pm4(state); +} + +static int r600_pipe_shader(struct pipe_context *ctx, struct r600_pipe_shader *rpshader) +{ + struct r600_screen *rscreen = (struct r600_screen*)ctx->screen; + struct r600_context *rctx = (struct r600_context*)ctx; + struct r600_shader *rshader = &rpshader->shader; + int r; + + /* copy new shader */ + radeon_bo_decref(rscreen->rw, rpshader->bo); + rpshader->bo = NULL; + rpshader->bo = radeon_bo(rscreen->rw, 0, rshader->ndw * 4, + 4096, NULL); + if (rpshader->bo == NULL) { + return -ENOMEM; + } + radeon_bo_map(rscreen->rw, rpshader->bo); + memcpy(rpshader->bo->data, rshader->bcode, rshader->ndw * 4); + radeon_bo_unmap(rscreen->rw, rpshader->bo); + /* build state */ + rshader->flat_shade = rctx->flat_shade; + switch (rpshader->type) { + case C_PROGRAM_TYPE_VS: + r = r600_pipe_shader_vs(ctx, rpshader); + break; + case C_PROGRAM_TYPE_FS: + r = r600_pipe_shader_ps(ctx, rpshader); + break; + default: + r = -EINVAL; + break; + } + return r; +} + +struct r600_pipe_shader *r600_pipe_shader_create(struct pipe_context *ctx, unsigned type, const struct tgsi_token *tokens) +{ + struct r600_pipe_shader *rpshader = CALLOC_STRUCT(r600_pipe_shader); + struct r600_shader *rshader = &rpshader->shader; + int r; + + if (rpshader == NULL) + return NULL; + rpshader->type = type; + c_list_init(&rshader->nodes); + fprintf(stderr, "<<\n"); + tgsi_dump(tokens, 0); + fprintf(stderr, "--------------------------------------------------------------\n"); + r = c_shader_from_tgsi(&rshader->cshader, type, tokens); + if (r) { + r600_pipe_shader_destroy(ctx, rpshader); + fprintf(stderr, "ERROR(%s %d)>>\n\n", __func__, __LINE__); + return NULL; + } + r = r600_shader_insert_fetch(&rshader->cshader); + if (r) { + r600_pipe_shader_destroy(ctx, rpshader); + fprintf(stderr, "ERROR(%s %d)>>\n\n", __func__, __LINE__); + return NULL; + } + r = c_shader_build_dominator_tree(&rshader->cshader); + if (r) { + r600_pipe_shader_destroy(ctx, rpshader); + fprintf(stderr, "ERROR(%s %d)>>\n\n", __func__, __LINE__); + return NULL; + } + c_shader_dump(&rshader->cshader); + r = r700_shader_translate(rshader); + if (r) { + r600_pipe_shader_destroy(ctx, rpshader); + fprintf(stderr, "ERROR(%s %d)>>\n\n", __func__, __LINE__); + return NULL; + } +#if 1 +#if 0 + fprintf(stderr, "--------------------------------------------------------------\n"); + for (int i = 0; i < rshader->ndw; i++) { + fprintf(stderr, "0x%08X\n", rshader->bcode[i]); + } +#endif + fprintf(stderr, ">>\n\n"); +#endif + return rpshader; +} + +void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *rpshader) +{ + struct r600_screen *rscreen = (struct r600_screen*)ctx->screen; + + if (rpshader == NULL) + return; + radeon_bo_decref(rscreen->rw, rpshader->bo); + rpshader->bo = NULL; + r600_shader_cleanup(&rpshader->shader); + FREE(rpshader); +} + +int r600_pipe_shader_update(struct pipe_context *ctx, struct r600_pipe_shader *rpshader) +{ + struct r600_context *rctx = (struct r600_context*)ctx; + struct r600_shader *rshader; + enum pipe_format resource_format[160]; + unsigned i, nresources = 0; + int r; + + if (rpshader == NULL) + return -EINVAL; + rshader = &rpshader->shader; + switch (rpshader->type) { + case C_PROGRAM_TYPE_VS: + for (i = 0; i < rctx->nvertex_element; i++) { + resource_format[nresources++] = rctx->vertex_element[i].src_format; + } + break; + default: + break; + } + /* there should be enough input */ + if (nresources < rshader->nresource) + return -EINVAL; + /* FIXME compare resources */ + r = r600_shader_update(rshader, resource_format); + if (r) + return r; + return r600_pipe_shader(ctx, rpshader); +} diff --git a/src/gallium/drivers/r600/r600_shader.h b/src/gallium/drivers/r600/r600_shader.h new file mode 100644 index 00000000000..45ab88b58f5 --- /dev/null +++ b/src/gallium/drivers/r600/r600_shader.h @@ -0,0 +1,130 @@ +/* + * Copyright 2010 Jerome Glisse <[email protected]> + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef R600_SHADER_H +#define R600_SHADER_H + +#include "r600_compiler.h" +#include "radeon.h" + +struct r600_state; + +struct r600_shader_vfetch { + struct r600_shader_vfetch *next; + struct r600_shader_vfetch *prev; + unsigned cf_addr; + unsigned sel[4]; + unsigned chan[4]; + unsigned dsel[4]; +}; + +struct r600_shader_operand { + struct c_vector *vector; + unsigned sel; + unsigned chan; + unsigned neg; + unsigned abs; +}; + +struct r600_shader_inst { + unsigned is_op3; + unsigned opcode; + unsigned inst; + struct r600_shader_operand src[3]; + struct r600_shader_operand dst; + unsigned last; +}; + +struct r600_shader_alu { + struct r600_shader_alu *next; + struct r600_shader_alu *prev; + unsigned nalu; + unsigned nliteral; + struct r600_shader_inst alu[5]; + u32 literal[4]; +}; + +struct r600_shader_node { + struct r600_shader_node *next; + struct r600_shader_node *prev; + unsigned cf_id; /**< cf index (in dw) in byte code */ + unsigned cf_addr; /**< instructions index (in dw) in byte code */ + unsigned nslot; /**< number of slot (2 dw) needed by this node */ + unsigned nfetch; + struct c_node *node; /**< compiler node from which this node originate */ + struct r600_shader_vfetch vfetch; /**< list of vfetch instructions */ + struct r600_shader_alu alu; /**< list of alu instructions */ +}; + +struct r600_shader_io { + unsigned name; + unsigned gpr; + int sid; +}; + +struct r600_shader { + unsigned stack_size; /**< stack size needed by this shader */ + unsigned ngpr; /**< number of GPR needed by this shader */ + unsigned nconstant; /**< number of constants used by this shader */ + unsigned nresource; /**< number of resources used by this shader */ + unsigned noutput; + unsigned ninput; + unsigned nvector; + unsigned ncf; /**< total number of cf clauses */ + unsigned nslot; /**< total number of slots (2 dw) */ + unsigned flat_shade; /**< are we flat shading */ + struct r600_shader_node nodes; /**< list of node */ + struct r600_shader_node *cur_node; /**< current node (used during nodes list creation) */ + struct r600_shader_io input[32]; + struct r600_shader_io output[32]; + /* TODO replace GPR by some better register allocator */ + struct c_vector **gpr; + unsigned ndw; /**< bytes code size in dw */ + u32 *bcode; /**< bytes code */ + enum pipe_format resource_format[160]; /**< format of resource */ + struct c_shader cshader; +}; + +void r600_shader_cleanup(struct r600_shader *rshader); +int r600_shader_register(struct r600_shader *rshader); +int r600_shader_node(struct r600_shader *shader); +void r600_shader_node_place(struct r600_shader *rshader); +int r600_shader_find_gpr(struct r600_shader *rshader, struct c_vector *v, + unsigned swizzle, unsigned *sel, unsigned *chan); +int r600_shader_vfetch_bytecode(struct r600_shader *rshader, + struct r600_shader_node *rnode, + struct r600_shader_vfetch *vfetch, + unsigned *cid); +int r600_shader_update(struct r600_shader *rshader, + enum pipe_format *resource_format); +int r600_shader_legalize(struct r600_shader *rshader); + +int r700_shader_translate(struct r600_shader *rshader); + +int c_shader_from_tgsi(struct c_shader *shader, unsigned type, + const struct tgsi_token *tokens); +int r600_shader_register(struct r600_shader *rshader); +int r600_shader_translate_rec(struct r600_shader *rshader, struct c_node *node); +int r700_shader_translate(struct r600_shader *rshader); +int r600_shader_insert_fetch(struct c_shader *shader); + +#endif diff --git a/src/gallium/drivers/r600/r600_sq.h b/src/gallium/drivers/r600/r600_sq.h new file mode 100644 index 00000000000..71aa09719e0 --- /dev/null +++ b/src/gallium/drivers/r600/r600_sq.h @@ -0,0 +1,606 @@ +/* + * Copyright 2010 Jerome Glisse <[email protected]> + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Jerome Glisse + */ +#ifndef R600_SQ_H +#define R600_SQ_H + +#define P_SQ_CF_WORD0 +#define S_SQ_CF_WORD0_ADDR(x) (((x) & 0xFFFFFFFF) << 0) +#define G_SQ_CF_WORD0_ADDR(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_SQ_CF_WORD0_ADDR 0x00000000 +#define P_SQ_CF_WORD1 +#define S_SQ_CF_WORD1_POP_COUNT(x) (((x) & 0x7) << 0) +#define G_SQ_CF_WORD1_POP_COUNT(x) (((x) >> 0) & 0x7) +#define C_SQ_CF_WORD1_POP_COUNT 0xFFFFFFF8 +#define S_SQ_CF_WORD1_CF_CONST(x) (((x) & 0x1F) << 3) +#define G_SQ_CF_WORD1_CF_CONST(x) (((x) >> 3) & 0x1F) +#define C_SQ_CF_WORD1_CF_CONST 0xFFFFFF07 +#define S_SQ_CF_WORD1_COND(x) (((x) & 0x3) << 8) +#define G_SQ_CF_WORD1_COND(x) (((x) >> 8) & 0x3) +#define C_SQ_CF_WORD1_COND 0xFFFFFCFF +#define S_SQ_CF_WORD1_COUNT(x) (((x) & 0x7) << 10) +#define G_SQ_CF_WORD1_COUNT(x) (((x) >> 10) & 0x7) +#define C_SQ_CF_WORD1_COUNT 0xFFFFE3FF +#define S_SQ_CF_WORD1_CALL_COUNT(x) (((x) & 0x3F) << 13) +#define G_SQ_CF_WORD1_CALL_COUNT(x) (((x) >> 13) & 0x3F) +#define C_SQ_CF_WORD1_CALL_COUNT 0xFFF81FFF +#define S_SQ_CF_WORD1_END_OF_PROGRAM(x) (((x) & 0x1) << 21) +#define G_SQ_CF_WORD1_END_OF_PROGRAM(x) (((x) >> 21) & 0x1) +#define C_SQ_CF_WORD1_END_OF_PROGRAM 0xFFDFFFFF +#define S_SQ_CF_WORD1_VALID_PIXEL_MODE(x) (((x) & 0x1) << 22) +#define G_SQ_CF_WORD1_VALID_PIXEL_MODE(x) (((x) >> 22) & 0x1) +#define C_SQ_CF_WORD1_VALID_PIXEL_MODE 0xFFBFFFFF +#define S_SQ_CF_WORD1_CF_INST(x) (((x) & 0x7F) << 23) +#define G_SQ_CF_WORD1_CF_INST(x) (((x) >> 23) & 0x7F) +#define C_SQ_CF_WORD1_CF_INST 0xC07FFFFF +#define V_SQ_CF_WORD1_SQ_CF_INST_NOP 0x00000000 +#define V_SQ_CF_WORD1_SQ_CF_INST_TEX 0x00000001 +#define V_SQ_CF_WORD1_SQ_CF_INST_VTX 0x00000002 +#define V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC 0x00000003 +#define V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START 0x00000004 +#define V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END 0x00000005 +#define V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_DX10 0x00000006 +#define V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL 0x00000007 +#define V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE 0x00000008 +#define V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK 0x00000009 +#define V_SQ_CF_WORD1_SQ_CF_INST_JUMP 0x0000000A +#define V_SQ_CF_WORD1_SQ_CF_INST_PUSH 0x0000000B +#define V_SQ_CF_WORD1_SQ_CF_INST_PUSH_ELSE 0x0000000C +#define V_SQ_CF_WORD1_SQ_CF_INST_ELSE 0x0000000D +#define V_SQ_CF_WORD1_SQ_CF_INST_POP 0x0000000E +#define V_SQ_CF_WORD1_SQ_CF_INST_POP_JUMP 0x0000000F +#define V_SQ_CF_WORD1_SQ_CF_INST_POP_PUSH 0x00000010 +#define V_SQ_CF_WORD1_SQ_CF_INST_POP_PUSH_ELSE 0x00000011 +#define V_SQ_CF_WORD1_SQ_CF_INST_CALL 0x00000012 +#define V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS 0x00000013 +#define V_SQ_CF_WORD1_SQ_CF_INST_RETURN 0x00000014 +#define V_SQ_CF_WORD1_SQ_CF_INST_EMIT_VERTEX 0x00000015 +#define V_SQ_CF_WORD1_SQ_CF_INST_EMIT_CUT_VERTEX 0x00000016 +#define V_SQ_CF_WORD1_SQ_CF_INST_CUT_VERTEX 0x00000017 +#define V_SQ_CF_WORD1_SQ_CF_INST_KILL 0x00000018 +#define S_SQ_CF_WORD1_WHOLE_QUAD_MODE(x) (((x) & 0x1) << 30) +#define G_SQ_CF_WORD1_WHOLE_QUAD_MODE(x) (((x) >> 30) & 0x1) +#define C_SQ_CF_WORD1_WHOLE_QUAD_MODE 0xBFFFFFFF +#define S_SQ_CF_WORD1_BARRIER(x) (((x) & 0x1) << 31) +#define G_SQ_CF_WORD1_BARRIER(x) (((x) >> 31) & 0x1) +#define C_SQ_CF_WORD1_BARRIER 0x7FFFFFFF +#define P_SQ_CF_ALU_WORD0 +#define S_SQ_CF_ALU_WORD0_ALU_ADDR(x) (((x) & 0x3FFFFF) << 0) +#define G_SQ_CF_ALU_WORD0_ALU_ADDR(x) (((x) >> 0) & 0x3FFFFF) +#define C_SQ_CF_ALU_WORD0_ALU_ADDR 0xFFC00000 +#define S_SQ_CF_ALU_WORD0_KCACHE_BANK0(x) (((x) & 0xF) << 22) +#define G_SQ_CF_ALU_WORD0_KCACHE_BANK0(x) (((x) >> 22) & 0xF) +#define C_SQ_CF_ALU_WORD0_KCACHE_BANK0 0xFC3FFFFF +#define S_SQ_CF_ALU_WORD0_KCACHE_BANK1(x) (((x) & 0xF) << 26) +#define G_SQ_CF_ALU_WORD0_KCACHE_BANK1(x) (((x) >> 26) & 0xF) +#define C_SQ_CF_ALU_WORD0_KCACHE_BANK1 0xC3FFFFFF +#define S_SQ_CF_ALU_WORD0_KCACHE_MODE0(x) (((x) & 0x3) << 30) +#define G_SQ_CF_ALU_WORD0_KCACHE_MODE0(x) (((x) >> 30) & 0x3) +#define C_SQ_CF_ALU_WORD0_KCACHE_MODE0 0x3FFFFFFF +#define P_SQ_CF_ALU_WORD1 +#define S_SQ_CF_ALU_WORD1_KCACHE_MODE1(x) (((x) & 0x3) << 0) +#define G_SQ_CF_ALU_WORD1_KCACHE_MODE1(x) (((x) >> 0) & 0x3) +#define C_SQ_CF_ALU_WORD1_KCACHE_MODE1 0xFFFFFFFC +#define S_SQ_CF_ALU_WORD1_KCACHE_ADDR0(x) (((x) & 0xFF) << 2) +#define G_SQ_CF_ALU_WORD1_KCACHE_ADDR0(x) (((x) >> 2) & 0xFF) +#define C_SQ_CF_ALU_WORD1_KCACHE_ADDR0 0xFFFFFC03 +#define S_SQ_CF_ALU_WORD1_KCACHE_ADDR1(x) (((x) & 0xFF) << 10) +#define G_SQ_CF_ALU_WORD1_KCACHE_ADDR1(x) (((x) >> 10) & 0xFF) +#define C_SQ_CF_ALU_WORD1_KCACHE_ADDR1 0xFFFC03FF +#define S_SQ_CF_ALU_WORD1_ALU_COUNT(x) (((x) & 0x7F) << 18) +#define G_SQ_CF_ALU_WORD1_ALU_COUNT(x) (((x) >> 18) & 0x7F) +#define C_SQ_CF_ALU_WORD1_ALU_COUNT 0xFE03FFFF +#define S_SQ_CF_ALU_WORD1_USES_WATERFALL(x) (((x) & 0x1) << 25) +#define G_SQ_CF_ALU_WORD1_USES_WATERFALL(x) (((x) >> 25) & 0x1) +#define C_SQ_CF_ALU_WORD1_USES_WATERFALL 0xFDFFFFFF +#define S_SQ_CF_ALU_WORD1_CF_ALU_INST(x) (((x) & 0xF) << 26) +#define G_SQ_CF_ALU_WORD1_CF_ALU_INST(x) (((x) >> 26) & 0xF) +#define C_SQ_CF_ALU_WORD1_CF_ALU_INST 0xC3FFFFFF +#define V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU 0x00000008 +#define V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE 0x00000009 +#define V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER 0x0000000A +#define V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER 0x0000000B +#define V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_CONTINUE 0x0000000D +#define V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_BREAK 0x0000000E +#define V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_ELSE_AFTER 0x0000000F +#define S_SQ_CF_ALU_WORD1_WHOLE_QUAD_MODE(x) (((x) & 0x1) << 30) +#define G_SQ_CF_ALU_WORD1_WHOLE_QUAD_MODE(x) (((x) >> 30) & 0x1) +#define C_SQ_CF_ALU_WORD1_WHOLE_QUAD_MODE 0xBFFFFFFF +#define S_SQ_CF_ALU_WORD1_BARRIER(x) (((x) & 0x1) << 31) +#define G_SQ_CF_ALU_WORD1_BARRIER(x) (((x) >> 31) & 0x1) +#define C_SQ_CF_ALU_WORD1_BARRIER 0x7FFFFFFF +#define P_SQ_CF_ALLOC_EXPORT_WORD0 +#define S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(x) (((x) & 0x1FFF) << 0) +#define G_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(x) (((x) >> 0) & 0x1FFF) +#define C_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE 0xFFFFE000 +#define S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(x) (((x) & 0x3) << 13) +#define G_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(x) (((x) >> 13) & 0x3) +#define C_SQ_CF_ALLOC_EXPORT_WORD0_TYPE 0xFFFF9FFF +#define V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL 0x00000000 +#define V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS 0x00000001 +#define V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM 0x00000002 +#define V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_SX 0x00000003 +#define S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(x) (((x) & 0x7F) << 15) +#define G_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(x) (((x) >> 15) & 0x7F) +#define C_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR 0xFFC07FFF +#define S_SQ_CF_ALLOC_EXPORT_WORD0_RW_REL(x) (((x) & 0x1) << 22) +#define G_SQ_CF_ALLOC_EXPORT_WORD0_RW_REL(x) (((x) >> 22) & 0x1) +#define C_SQ_CF_ALLOC_EXPORT_WORD0_RW_REL 0xFFBFFFFF +#define S_SQ_CF_ALLOC_EXPORT_WORD0_INDEX_GPR(x) (((x) & 0x7F) << 23) +#define G_SQ_CF_ALLOC_EXPORT_WORD0_INDEX_GPR(x) (((x) >> 23) & 0x7F) +#define C_SQ_CF_ALLOC_EXPORT_WORD0_INDEX_GPR 0xC07FFFFF +#define S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(x) (((x) & 0x3) << 30) +#define G_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(x) (((x) >> 30) & 0x3) +#define C_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE 0x3FFFFFFF +#define P_SQ_CF_ALLOC_EXPORT_WORD1 +#define S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(x) (((x) & 0xF) << 17) +#define G_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(x) (((x) >> 17) & 0xF) +#define C_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT 0xFFE1FFFF +#define S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(x) (((x) & 0x1) << 21) +#define G_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(x) (((x) >> 21) & 0x1) +#define C_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM 0xFFDFFFFF +#define S_SQ_CF_ALLOC_EXPORT_WORD1_VALID_PIXEL_MODE(x) (((x) & 0x1) << 22) +#define G_SQ_CF_ALLOC_EXPORT_WORD1_VALID_PIXEL_MODE(x) (((x) >> 22) & 0x1) +#define C_SQ_CF_ALLOC_EXPORT_WORD1_VALID_PIXEL_MODE 0xFFBFFFFF +#define S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(x) (((x) & 0x7F) << 23) +#define G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(x) (((x) >> 23) & 0x7F) +#define C_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST 0xC07FFFFF +#define V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0 0x00000020 +#define V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1 0x00000021 +#define V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2 0x00000022 +#define V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3 0x00000023 +#define V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_SCRATCH 0x00000024 +#define V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_REDUCTION 0x00000025 +#define V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_RING 0x00000026 +#define V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT 0x00000027 +#define V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE 0x00000028 +#define S_SQ_CF_ALLOC_EXPORT_WORD1_WHOLE_QUAD_MODE(x) (((x) & 0x1) << 30) +#define G_SQ_CF_ALLOC_EXPORT_WORD1_WHOLE_QUAD_MODE(x) (((x) >> 30) & 0x1) +#define C_SQ_CF_ALLOC_EXPORT_WORD1_WHOLE_QUAD_MODE 0xBFFFFFFF +#define S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(x) (((x) & 0x1) << 31) +#define G_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(x) (((x) >> 31) & 0x1) +#define C_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER 0x7FFFFFFF +#define P_SQ_CF_ALLOC_EXPORT_WORD1_BUF +#define S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE(x) (((x) & 0xFFF) << 0) +#define G_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE(x) (((x) >> 0) & 0xFFF) +#define C_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE 0xFFFFF000 +#define S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(x) (((x) & 0xF) << 12) +#define G_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(x) (((x) >> 12) & 0xF) +#define C_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK 0xFFFF0FFF +#define P_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ +#define S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(x) (((x) & 0x7) << 0) +#define G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(x) (((x) >> 0) & 0x7) +#define C_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X 0xFFFFFFF8 +#define S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(x) (((x) & 0x7) << 3) +#define G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(x) (((x) >> 3) & 0x7) +#define C_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y 0xFFFFFFC7 +#define S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(x) (((x) & 0x7) << 6) +#define G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(x) (((x) >> 6) & 0x7) +#define C_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z 0xFFFFFE3F +#define S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(x) (((x) & 0x7) << 9) +#define G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(x) (((x) >> 9) & 0x7) +#define C_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W 0xFFFFF1FF +#define P_SQ_ALU_WORD0 +#define S_SQ_ALU_WORD0_SRC0_SEL(x) (((x) & 0x1FF) << 0) +#define G_SQ_ALU_WORD0_SRC0_SEL(x) (((x) >> 0) & 0x1FF) +#define C_SQ_ALU_WORD0_SRC0_SEL 0xFFFFFE00 +#define S_SQ_ALU_WORD0_SRC0_REL(x) (((x) & 0x1) << 9) +#define G_SQ_ALU_WORD0_SRC0_REL(x) (((x) >> 9) & 0x1) +#define C_SQ_ALU_WORD0_SRC0_REL 0xFFFFFDFF +#define S_SQ_ALU_WORD0_SRC0_CHAN(x) (((x) & 0x3) << 10) +#define G_SQ_ALU_WORD0_SRC0_CHAN(x) (((x) >> 10) & 0x3) +#define C_SQ_ALU_WORD0_SRC0_CHAN 0xFFFFF3FF +#define S_SQ_ALU_WORD0_SRC0_NEG(x) (((x) & 0x1) << 12) +#define G_SQ_ALU_WORD0_SRC0_NEG(x) (((x) >> 12) & 0x1) +#define C_SQ_ALU_WORD0_SRC0_NEG 0xFFFFEFFF +#define S_SQ_ALU_WORD0_SRC1_SEL(x) (((x) & 0x1FF) << 13) +#define G_SQ_ALU_WORD0_SRC1_SEL(x) (((x) >> 13) & 0x1FF) +#define C_SQ_ALU_WORD0_SRC1_SEL 0xFFC01FFF +#define S_SQ_ALU_WORD0_SRC1_REL(x) (((x) & 0x1) << 22) +#define G_SQ_ALU_WORD0_SRC1_REL(x) (((x) >> 22) & 0x1) +#define C_SQ_ALU_WORD0_SRC1_REL 0xFFBFFFFF +#define S_SQ_ALU_WORD0_SRC1_CHAN(x) (((x) & 0x3) << 23) +#define G_SQ_ALU_WORD0_SRC1_CHAN(x) (((x) >> 23) & 0x3) +#define C_SQ_ALU_WORD0_SRC1_CHAN 0xFE7FFFFF +#define S_SQ_ALU_WORD0_SRC1_NEG(x) (((x) & 0x1) << 25) +#define G_SQ_ALU_WORD0_SRC1_NEG(x) (((x) >> 25) & 0x1) +#define C_SQ_ALU_WORD0_SRC1_NEG 0xFDFFFFFF +#define S_SQ_ALU_WORD0_INDEX_MODE(x) (((x) & 0x7) << 26) +#define G_SQ_ALU_WORD0_INDEX_MODE(x) (((x) >> 26) & 0x7) +#define C_SQ_ALU_WORD0_INDEX_MODE 0xE3FFFFFF +#define S_SQ_ALU_WORD0_PRED_SEL(x) (((x) & 0x3) << 29) +#define G_SQ_ALU_WORD0_PRED_SEL(x) (((x) >> 29) & 0x3) +#define C_SQ_ALU_WORD0_PRED_SEL 0x9FFFFFFF +#define S_SQ_ALU_WORD0_LAST(x) (((x) & 0x1) << 31) +#define G_SQ_ALU_WORD0_LAST(x) (((x) >> 31) & 0x1) +#define C_SQ_ALU_WORD0_LAST 0x7FFFFFFF +#define P_SQ_ALU_WORD1 +#define S_SQ_ALU_WORD1_ENCODING(x) (((x) & 0x7) << 15) +#define G_SQ_ALU_WORD1_ENCODING(x) (((x) >> 15) & 0x7) +#define C_SQ_ALU_WORD1_ENCODING 0xFFFC7FFF +#define S_SQ_ALU_WORD1_BANK_SWIZZLE(x) (((x) & 0x7) << 18) +#define G_SQ_ALU_WORD1_BANK_SWIZZLE(x) (((x) >> 18) & 0x7) +#define C_SQ_ALU_WORD1_BANK_SWIZZLE 0xFFE3FFFF +#define S_SQ_ALU_WORD1_DST_GPR(x) (((x) & 0x7F) << 21) +#define G_SQ_ALU_WORD1_DST_GPR(x) (((x) >> 21) & 0x7F) +#define C_SQ_ALU_WORD1_DST_GPR 0xF01FFFFF +#define S_SQ_ALU_WORD1_DST_REL(x) (((x) & 0x1) << 28) +#define G_SQ_ALU_WORD1_DST_REL(x) (((x) >> 28) & 0x1) +#define C_SQ_ALU_WORD1_DST_REL 0xEFFFFFFF +#define S_SQ_ALU_WORD1_DST_CHAN(x) (((x) & 0x3) << 29) +#define G_SQ_ALU_WORD1_DST_CHAN(x) (((x) >> 29) & 0x3) +#define C_SQ_ALU_WORD1_DST_CHAN 0x9FFFFFFF +#define S_SQ_ALU_WORD1_CLAMP(x) (((x) & 0x1) << 31) +#define G_SQ_ALU_WORD1_CLAMP(x) (((x) >> 31) & 0x1) +#define C_SQ_ALU_WORD1_CLAMP 0x7FFFFFFF +#define P_SQ_ALU_WORD1_OP2 +#define S_SQ_ALU_WORD1_OP2_SRC0_ABS(x) (((x) & 0x1) << 0) +#define G_SQ_ALU_WORD1_OP2_SRC0_ABS(x) (((x) >> 0) & 0x1) +#define C_SQ_ALU_WORD1_OP2_SRC0_ABS 0xFFFFFFFE +#define S_SQ_ALU_WORD1_OP2_SRC1_ABS(x) (((x) & 0x1) << 1) +#define G_SQ_ALU_WORD1_OP2_SRC1_ABS(x) (((x) >> 1) & 0x1) +#define C_SQ_ALU_WORD1_OP2_SRC1_ABS 0xFFFFFFFD +#define S_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(x) (((x) & 0x1) << 2) +#define G_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(x) (((x) >> 2) & 0x1) +#define C_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK 0xFFFFFFFB +#define S_SQ_ALU_WORD1_OP2_UPDATE_PRED(x) (((x) & 0x1) << 3) +#define G_SQ_ALU_WORD1_OP2_UPDATE_PRED(x) (((x) >> 3) & 0x1) +#define C_SQ_ALU_WORD1_OP2_UPDATE_PRED 0xFFFFFFF7 +#define S_SQ_ALU_WORD1_OP2_WRITE_MASK(x) (((x) & 0x1) << 4) +#define G_SQ_ALU_WORD1_OP2_WRITE_MASK(x) (((x) >> 4) & 0x1) +#define C_SQ_ALU_WORD1_OP2_WRITE_MASK 0xFFFFFFEF +#define S_SQ_ALU_WORD1_OP2_FOG_MERGE(x) (((x) & 0x1) << 5) +#define G_SQ_ALU_WORD1_OP2_FOG_MERGE(x) (((x) >> 5) & 0x1) +#define C_SQ_ALU_WORD1_OP2_FOG_MERGE 0xFFFFFFDF +#define S_SQ_ALU_WORD1_OP2_OMOD(x) (((x) & 0x3) << 6) +#define G_SQ_ALU_WORD1_OP2_OMOD(x) (((x) >> 6) & 0x3) +#define C_SQ_ALU_WORD1_OP2_OMOD 0xFFFFFF3F +#define S_SQ_ALU_WORD1_OP2_ALU_INST(x) (((x) & 0x3FF) << 8) +#define G_SQ_ALU_WORD1_OP2_ALU_INST(x) (((x) >> 8) & 0x3FF) +#define C_SQ_ALU_WORD1_OP2_ALU_INST 0xFFFC00FF +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD 0x00000000 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL 0x00000001 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL_IEEE 0x00000002 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX 0x00000003 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN 0x00000004 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_DX10 0x00000005 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_DX10 0x00000006 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE 0x00000008 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT 0x00000009 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE 0x0000000A +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE 0x0000000B +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE_DX10 0x0000000C +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_DX10 0x0000000D +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_DX10 0x0000000E +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE_DX10 0x0000000F +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT 0x00000010 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC 0x00000011 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CEIL 0x00000012 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RNDNE 0x00000013 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR 0x00000014 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA 0x00000015 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR 0x00000016 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT 0x00000018 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV 0x00000019 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP 0x0000001A +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_UINT 0x0000001E +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_UINT 0x0000001F +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE 0x00000020 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT 0x00000021 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE 0x00000022 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE 0x00000023 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_INV 0x00000024 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_POP 0x00000025 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_CLR 0x00000026 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_RESTORE 0x00000027 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH 0x00000028 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH 0x00000029 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH 0x0000002A +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH 0x0000002B +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE 0x0000002C +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT 0x0000002D +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE 0x0000002E +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE 0x0000002F +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_AND_INT 0x00000030 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_OR_INT 0x00000031 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT 0x00000032 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOT_INT 0x00000033 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT 0x00000034 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT 0x00000035 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_INT 0x00000036 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_INT 0x00000037 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_UINT 0x00000038 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_UINT 0x00000039 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE_INT 0x0000003A +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_INT 0x0000003B +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_INT 0x0000003C +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE_INT 0x0000003D +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_UINT 0x0000003E +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT 0x0000003F +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_UINT 0x00000040 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_UINT 0x00000041 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT 0x00000042 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_INT 0x00000043 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_INT 0x00000044 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT 0x00000045 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE_INT 0x00000046 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_INT 0x00000047 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_INT 0x00000048 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE_INT 0x00000049 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH_INT 0x0000004A +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH_INT 0x0000004B +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH_INT 0x0000004C +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH_INT 0x0000004D +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLT_PUSH_INT 0x0000004E +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLE_PUSH_INT 0x0000004F +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4 0x00000050 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE 0x00000051 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE 0x00000052 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX4 0x00000053 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_GPR_INT 0x00000060 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE 0x00000061 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED 0x00000062 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE 0x00000063 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED 0x00000064 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_FF 0x00000065 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE 0x00000066 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED 0x00000067 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_FF 0x00000068 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE 0x00000069 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SQRT_IEEE 0x0000006A +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT 0x0000006B +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT 0x0000006C +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT 0x0000006D +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN 0x0000006E +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS 0x0000006F +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT 0x00000070 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT 0x00000071 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT 0x00000072 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT 0x00000073 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_INT 0x00000074 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT 0x00000075 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT 0x00000076 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_INT 0x00000077 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_UINT 0x00000078 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT 0x00000079 +#define P_SQ_ALU_WORD1_OP3 +#define S_SQ_ALU_WORD1_OP3_SRC2_SEL(x) (((x) & 0x1FF) << 0) +#define G_SQ_ALU_WORD1_OP3_SRC2_SEL(x) (((x) >> 0) & 0x1FF) +#define C_SQ_ALU_WORD1_OP3_SRC2_SEL 0xFFFFFE00 +#define S_SQ_ALU_WORD1_OP3_SRC2_REL(x) (((x) & 0x1) << 9) +#define G_SQ_ALU_WORD1_OP3_SRC2_REL(x) (((x) >> 9) & 0x1) +#define C_SQ_ALU_WORD1_OP3_SRC2_REL 0xFFFFFDFF +#define S_SQ_ALU_WORD1_OP3_SRC2_CHAN(x) (((x) & 0x3) << 10) +#define G_SQ_ALU_WORD1_OP3_SRC2_CHAN(x) (((x) >> 10) & 0x3) +#define C_SQ_ALU_WORD1_OP3_SRC2_CHAN 0xFFFFF3FF +#define S_SQ_ALU_WORD1_OP3_SRC2_NEG(x) (((x) & 0x1) << 12) +#define G_SQ_ALU_WORD1_OP3_SRC2_NEG(x) (((x) >> 12) & 0x1) +#define C_SQ_ALU_WORD1_OP3_SRC2_NEG 0xFFFFEFFF +#define S_SQ_ALU_WORD1_OP3_ALU_INST(x) (((x) & 0x1F) << 13) +#define G_SQ_ALU_WORD1_OP3_ALU_INST(x) (((x) >> 13) & 0x1F) +#define C_SQ_ALU_WORD1_OP3_ALU_INST 0xFFFC1FFF +#define V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT 0x0000000C +#define V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT_M2 0x0000000D +#define V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT_M4 0x0000000E +#define V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT_D2 0x0000000F +#define V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD 0x00000010 +#define V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD_M2 0x00000011 +#define V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD_M4 0x00000012 +#define V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD_D2 0x00000013 +#define V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD_IEEE 0x00000014 +#define V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD_IEEE_M2 0x00000015 +#define V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD_IEEE_M4 0x00000016 +#define V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD_IEEE_D2 0x00000017 +#define V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDE 0x00000018 +#define V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT 0x00000019 +#define V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE 0x0000001A +#define V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDE_INT 0x0000001C +#define V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT_INT 0x0000001D +#define V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE_INT 0x0000001E +#define P_SQ_VTX_WORD0 +#define S_SQ_VTX_WORD0_VTX_INST(x) (((x) & 0x1F) << 0) +#define G_SQ_VTX_WORD0_VTX_INST(x) (((x) >> 0) & 0x1F) +#define C_SQ_VTX_WORD0_VTX_INST 0xFFFFFFE0 +#define S_SQ_VTX_WORD0_FETCH_TYPE(x) (((x) & 0x3) << 5) +#define G_SQ_VTX_WORD0_FETCH_TYPE(x) (((x) >> 5) & 0x3) +#define C_SQ_VTX_WORD0_FETCH_TYPE 0xFFFFFF9F +#define S_SQ_VTX_WORD0_FETCH_WHOLE_QUAD(x) (((x) & 0x1) << 7) +#define G_SQ_VTX_WORD0_FETCH_WHOLE_QUAD(x) (((x) >> 7) & 0x1) +#define C_SQ_VTX_WORD0_FETCH_WHOLE_QUAD 0xFFFFFF7F +#define S_SQ_VTX_WORD0_BUFFER_ID(x) (((x) & 0xFF) << 8) +#define G_SQ_VTX_WORD0_BUFFER_ID(x) (((x) >> 8) & 0xFF) +#define C_SQ_VTX_WORD0_BUFFER_ID 0xFFFF00FF +#define S_SQ_VTX_WORD0_SRC_GPR(x) (((x) & 0x7F) << 16) +#define G_SQ_VTX_WORD0_SRC_GPR(x) (((x) >> 16) & 0x7F) +#define C_SQ_VTX_WORD0_SRC_GPR 0xFF80FFFF +#define S_SQ_VTX_WORD0_SRC_REL(x) (((x) & 0x1) << 23) +#define G_SQ_VTX_WORD0_SRC_REL(x) (((x) >> 23) & 0x1) +#define C_SQ_VTX_WORD0_SRC_REL 0xFF7FFFFF +#define S_SQ_VTX_WORD0_SRC_SEL_X(x) (((x) & 0x3) << 24) +#define G_SQ_VTX_WORD0_SRC_SEL_X(x) (((x) >> 24) & 0x3) +#define C_SQ_VTX_WORD0_SRC_SEL_X 0xFCFFFFFF +#define S_SQ_VTX_WORD0_MEGA_FETCH_COUNT(x) (((x) & 0x3F) << 26) +#define G_SQ_VTX_WORD0_MEGA_FETCH_COUNT(x) (((x) >> 26) & 0x3F) +#define C_SQ_VTX_WORD0_MEGA_FETCH_COUNT 0x03FFFFFF +#define P_SQ_VTX_WORD1 +#define S_SQ_VTX_WORD1_DST_SEL_X(x) (((x) & 0x7) << 9) +#define G_SQ_VTX_WORD1_DST_SEL_X(x) (((x) >> 9) & 0x7) +#define C_SQ_VTX_WORD1_DST_SEL_X 0xFFFFF1FF +#define S_SQ_VTX_WORD1_DST_SEL_Y(x) (((x) & 0x7) << 12) +#define G_SQ_VTX_WORD1_DST_SEL_Y(x) (((x) >> 12) & 0x7) +#define C_SQ_VTX_WORD1_DST_SEL_Y 0xFFFF8FFF +#define S_SQ_VTX_WORD1_DST_SEL_Z(x) (((x) & 0x7) << 15) +#define G_SQ_VTX_WORD1_DST_SEL_Z(x) (((x) >> 15) & 0x7) +#define C_SQ_VTX_WORD1_DST_SEL_Z 0xFFFC7FFF +#define S_SQ_VTX_WORD1_DST_SEL_W(x) (((x) & 0x7) << 18) +#define G_SQ_VTX_WORD1_DST_SEL_W(x) (((x) >> 18) & 0x7) +#define C_SQ_VTX_WORD1_DST_SEL_W 0xFFE3FFFF +#define S_SQ_VTX_WORD1_USE_CONST_FIELDS(x) (((x) & 0x1) << 21) +#define G_SQ_VTX_WORD1_USE_CONST_FIELDS(x) (((x) >> 21) & 0x1) +#define C_SQ_VTX_WORD1_USE_CONST_FIELDS 0xFFDFFFFF +#define S_SQ_VTX_WORD1_DATA_FORMAT(x) (((x) & 0x3F) << 22) +#define G_SQ_VTX_WORD1_DATA_FORMAT(x) (((x) >> 22) & 0x3F) +#define C_SQ_VTX_WORD1_DATA_FORMAT 0xF03FFFFF +#define S_SQ_VTX_WORD1_NUM_FORMAT_ALL(x) (((x) & 0x3) << 28) +#define G_SQ_VTX_WORD1_NUM_FORMAT_ALL(x) (((x) >> 28) & 0x3) +#define C_SQ_VTX_WORD1_NUM_FORMAT_ALL 0xCFFFFFFF +#define S_SQ_VTX_WORD1_FORMAT_COMP_ALL(x) (((x) & 0x1) << 30) +#define G_SQ_VTX_WORD1_FORMAT_COMP_ALL(x) (((x) >> 30) & 0x1) +#define C_SQ_VTX_WORD1_FORMAT_COMP_ALL 0xBFFFFFFF +#define S_SQ_VTX_WORD1_SRF_MODE_ALL(x) (((x) & 0x1) << 31) +#define G_SQ_VTX_WORD1_SRF_MODE_ALL(x) (((x) >> 31) & 0x1) +#define C_SQ_VTX_WORD1_SRF_MODE_ALL 0x7FFFFFFF +#define P_SQ_VTX_WORD1_GPR +#define S_SQ_VTX_WORD1_GPR_DST_GPR(x) (((x) & 0x7F) << 0) +#define G_SQ_VTX_WORD1_GPR_DST_GPR(x) (((x) >> 0) & 0x7F) +#define C_SQ_VTX_WORD1_GPR_DST_GPR 0xFFFFFF80 +#define S_SQ_VTX_WORD1_GPR_DST_REL(x) (((x) & 0x1) << 7) +#define G_SQ_VTX_WORD1_GPR_DST_REL(x) (((x) >> 7) & 0x1) +#define C_SQ_VTX_WORD1_GPR_DST_REL 0xFFFFFF7F +#define P_SQ_VTX_WORD1_SEM +#define S_SQ_VTX_WORD1_SEM_SEMANTIC_ID(x) (((x) & 0xFF) << 0) +#define G_SQ_VTX_WORD1_SEM_SEMANTIC_ID(x) (((x) >> 0) & 0xFF) +#define C_SQ_VTX_WORD1_SEM_SEMANTIC_ID 0xFFFFFF00 +#define P_SQ_VTX_WORD2 +#define S_SQ_VTX_WORD2_OFFSET(x) (((x) & 0xFFFF) << 0) +#define G_SQ_VTX_WORD2_OFFSET(x) (((x) >> 0) & 0xFFFF) +#define C_SQ_VTX_WORD2_OFFSET 0xFFFF0000 +#define S_SQ_VTX_WORD2_ENDIAN_SWAP(x) (((x) & 0x3) << 16) +#define G_SQ_VTX_WORD2_ENDIAN_SWAP(x) (((x) >> 16) & 0x3) +#define C_SQ_VTX_WORD2_ENDIAN_SWAP 0xFFFCFFFF +#define S_SQ_VTX_WORD2_CONST_BUF_NO_STRIDE(x) (((x) & 0x1) << 18) +#define G_SQ_VTX_WORD2_CONST_BUF_NO_STRIDE(x) (((x) >> 18) & 0x1) +#define C_SQ_VTX_WORD2_CONST_BUF_NO_STRIDE 0xFFFBFFFF +#define S_SQ_VTX_WORD2_MEGA_FETCH(x) (((x) & 0x1) << 19) +#define G_SQ_VTX_WORD2_MEGA_FETCH(x) (((x) >> 19) & 0x1) +#define C_SQ_VTX_WORD2_MEGA_FETCH 0xFFF7FFFF +#define S_SQ_VTX_WORD2_ALT_CONST(x) (((x) & 0x1) << 20) +#define G_SQ_VTX_WORD2_ALT_CONST(x) (((x) >> 20) & 0x1) +#define C_SQ_VTX_WORD2_ALT_CONST 0xFFEFFFFF +#define P_SQ_TEX_WORD0 +#define S_SQ_TEX_WORD0_TEX_INST(x) (((x) & 0x1F) << 0) +#define G_SQ_TEX_WORD0_TEX_INST(x) (((x) >> 0) & 0x1F) +#define C_SQ_TEX_WORD0_TEX_INST 0xFFFFFFE0 +#define S_SQ_TEX_WORD0_BC_FRAC_MODE(x) (((x) & 0x1) << 5) +#define G_SQ_TEX_WORD0_BC_FRAC_MODE(x) (((x) >> 5) & 0x1) +#define C_SQ_TEX_WORD0_BC_FRAC_MODE 0xFFFFFFDF +#define S_SQ_TEX_WORD0_FETCH_WHOLE_QUAD(x) (((x) & 0x1) << 7) +#define G_SQ_TEX_WORD0_FETCH_WHOLE_QUAD(x) (((x) >> 7) & 0x1) +#define C_SQ_TEX_WORD0_FETCH_WHOLE_QUAD 0xFFFFFF7F +#define S_SQ_TEX_WORD0_RESOURCE_ID(x) (((x) & 0xFF) << 8) +#define G_SQ_TEX_WORD0_RESOURCE_ID(x) (((x) >> 8) & 0xFF) +#define C_SQ_TEX_WORD0_RESOURCE_ID 0xFFFF00FF +#define S_SQ_TEX_WORD0_SRC_GPR(x) (((x) & 0x7F) << 16) +#define G_SQ_TEX_WORD0_SRC_GPR(x) (((x) >> 16) & 0x7F) +#define C_SQ_TEX_WORD0_SRC_GPR 0xFF80FFFF +#define S_SQ_TEX_WORD0_SRC_REL(x) (((x) & 0x1) << 23) +#define G_SQ_TEX_WORD0_SRC_REL(x) (((x) >> 23) & 0x1) +#define C_SQ_TEX_WORD0_SRC_REL 0xFF7FFFFF +#define S_SQ_TEX_WORD0_ALT_CONST(x) (((x) & 0x1) << 24) +#define G_SQ_TEX_WORD0_ALT_CONST(x) (((x) >> 24) & 0x1) +#define C_SQ_TEX_WORD0_ALT_CONST 0xFEFFFFFF +#define P_SQ_TEX_WORD1 +#define S_SQ_TEX_WORD1_DST_GPR(x) (((x) & 0x7F) << 0) +#define G_SQ_TEX_WORD1_DST_GPR(x) (((x) >> 0) & 0x7F) +#define C_SQ_TEX_WORD1_DST_GPR 0xFFFFFF80 +#define S_SQ_TEX_WORD1_DST_REL(x) (((x) & 0x1) << 7) +#define G_SQ_TEX_WORD1_DST_REL(x) (((x) >> 7) & 0x1) +#define C_SQ_TEX_WORD1_DST_REL 0xFFFFFF7F +#define S_SQ_TEX_WORD1_DST_SEL_X(x) (((x) & 0x7) << 9) +#define G_SQ_TEX_WORD1_DST_SEL_X(x) (((x) >> 9) & 0x7) +#define C_SQ_TEX_WORD1_DST_SEL_X 0xFFFFF1FF +#define S_SQ_TEX_WORD1_DST_SEL_Y(x) (((x) & 0x7) << 12) +#define G_SQ_TEX_WORD1_DST_SEL_Y(x) (((x) >> 12) & 0x7) +#define C_SQ_TEX_WORD1_DST_SEL_Y 0xFFFF8FFF +#define S_SQ_TEX_WORD1_DST_SEL_Z(x) (((x) & 0x7) << 15) +#define G_SQ_TEX_WORD1_DST_SEL_Z(x) (((x) >> 15) & 0x7) +#define C_SQ_TEX_WORD1_DST_SEL_Z 0xFFFC7FFF +#define S_SQ_TEX_WORD1_DST_SEL_W(x) (((x) & 0x7) << 18) +#define G_SQ_TEX_WORD1_DST_SEL_W(x) (((x) >> 18) & 0x7) +#define C_SQ_TEX_WORD1_DST_SEL_W 0xFFE3FFFF +#define S_SQ_TEX_WORD1_LOD_BIAS(x) (((x) & 0x7F) << 21) +#define G_SQ_TEX_WORD1_LOD_BIAS(x) (((x) >> 21) & 0x7F) +#define C_SQ_TEX_WORD1_LOD_BIAS 0xF01FFFFF +#define S_SQ_TEX_WORD1_COORD_TYPE_X(x) (((x) & 0x1) << 28) +#define G_SQ_TEX_WORD1_COORD_TYPE_X(x) (((x) >> 28) & 0x1) +#define C_SQ_TEX_WORD1_COORD_TYPE_X 0xEFFFFFFF +#define S_SQ_TEX_WORD1_COORD_TYPE_Y(x) (((x) & 0x1) << 29) +#define G_SQ_TEX_WORD1_COORD_TYPE_Y(x) (((x) >> 29) & 0x1) +#define C_SQ_TEX_WORD1_COORD_TYPE_Y 0xDFFFFFFF +#define S_SQ_TEX_WORD1_COORD_TYPE_Z(x) (((x) & 0x1) << 30) +#define G_SQ_TEX_WORD1_COORD_TYPE_Z(x) (((x) >> 30) & 0x1) +#define C_SQ_TEX_WORD1_COORD_TYPE_Z 0xBFFFFFFF +#define S_SQ_TEX_WORD1_COORD_TYPE_W(x) (((x) & 0x1) << 31) +#define G_SQ_TEX_WORD1_COORD_TYPE_W(x) (((x) >> 31) & 0x1) +#define C_SQ_TEX_WORD1_COORD_TYPE_W 0x7FFFFFFF +#define P_SQ_TEX_WORD2 +#define S_SQ_TEX_WORD2_OFFSET_X(x) (((x) & 0x1F) << 0) +#define G_SQ_TEX_WORD2_OFFSET_X(x) (((x) >> 0) & 0x1F) +#define C_SQ_TEX_WORD2_OFFSET_X 0xFFFFFFE0 +#define S_SQ_TEX_WORD2_OFFSET_Y(x) (((x) & 0x1F) << 5) +#define G_SQ_TEX_WORD2_OFFSET_Y(x) (((x) >> 5) & 0x1F) +#define C_SQ_TEX_WORD2_OFFSET_Y 0xFFFFFC1F +#define S_SQ_TEX_WORD2_OFFSET_Z(x) (((x) & 0x1F) << 10) +#define G_SQ_TEX_WORD2_OFFSET_Z(x) (((x) >> 10) & 0x1F) +#define C_SQ_TEX_WORD2_OFFSET_Z 0xFFFF83FF +#define S_SQ_TEX_WORD2_SAMPLER_ID(x) (((x) & 0x1F) << 15) +#define G_SQ_TEX_WORD2_SAMPLER_ID(x) (((x) >> 15) & 0x1F) +#define C_SQ_TEX_WORD2_SAMPLER_ID 0xFFF07FFF +#define S_SQ_TEX_WORD2_SRC_SEL_X(x) (((x) & 0x7) << 20) +#define G_SQ_TEX_WORD2_SRC_SEL_X(x) (((x) >> 20) & 0x7) +#define C_SQ_TEX_WORD2_SRC_SEL_X 0xFF8FFFFF +#define S_SQ_TEX_WORD2_SRC_SEL_Y(x) (((x) & 0x7) << 23) +#define G_SQ_TEX_WORD2_SRC_SEL_Y(x) (((x) >> 23) & 0x7) +#define C_SQ_TEX_WORD2_SRC_SEL_Y 0xFC7FFFFF +#define S_SQ_TEX_WORD2_SRC_SEL_Z(x) (((x) & 0x7) << 26) +#define G_SQ_TEX_WORD2_SRC_SEL_Z(x) (((x) >> 26) & 0x7) +#define C_SQ_TEX_WORD2_SRC_SEL_Z 0xE3FFFFFF +#define S_SQ_TEX_WORD2_SRC_SEL_W(x) (((x) & 0x7) << 29) +#define G_SQ_TEX_WORD2_SRC_SEL_W(x) (((x) >> 29) & 0x7) +#define C_SQ_TEX_WORD2_SRC_SEL_W 0x1FFFFFFF +#define P_SQ_ALU_WORD1_OP2_V2 +#define S_SQ_ALU_WORD1_OP2_V2_SRC0_ABS(x) (((x) & 0x1) << 0) +#define G_SQ_ALU_WORD1_OP2_V2_SRC0_ABS(x) (((x) >> 0) & 0x1) +#define C_SQ_ALU_WORD1_OP2_V2_SRC0_ABS 0xFFFFFFFE +#define S_SQ_ALU_WORD1_OP2_V2_SRC1_ABS(x) (((x) & 0x1) << 1) +#define G_SQ_ALU_WORD1_OP2_V2_SRC1_ABS(x) (((x) >> 1) & 0x1) +#define C_SQ_ALU_WORD1_OP2_V2_SRC1_ABS 0xFFFFFFFD +#define S_SQ_ALU_WORD1_OP2_V2_UPDATE_EXECUTE_MASK(x) (((x) & 0x1) << 2) +#define G_SQ_ALU_WORD1_OP2_V2_UPDATE_EXECUTE_MASK(x) (((x) >> 2) & 0x1) +#define C_SQ_ALU_WORD1_OP2_V2_UPDATE_EXECUTE_MASK 0xFFFFFFFB +#define S_SQ_ALU_WORD1_OP2_V2_UPDATE_PRED(x) (((x) & 0x1) << 3) +#define G_SQ_ALU_WORD1_OP2_V2_UPDATE_PRED(x) (((x) >> 3) & 0x1) +#define C_SQ_ALU_WORD1_OP2_V2_UPDATE_PRED 0xFFFFFFF7 +#define S_SQ_ALU_WORD1_OP2_V2_WRITE_MASK(x) (((x) & 0x1) << 4) +#define G_SQ_ALU_WORD1_OP2_V2_WRITE_MASK(x) (((x) >> 4) & 0x1) +#define C_SQ_ALU_WORD1_OP2_V2_WRITE_MASK 0xFFFFFFEF +#define S_SQ_ALU_WORD1_OP2_V2_OMOD(x) (((x) & 0x3) << 5) +#define G_SQ_ALU_WORD1_OP2_V2_OMOD(x) (((x) >> 5) & 0x3) +#define C_SQ_ALU_WORD1_OP2_V2_OMOD 0xFFFFFF9F +#define S_SQ_ALU_WORD1_OP2_V2_ALU_INST(x) (((x) & 0x7FF) << 7) +#define G_SQ_ALU_WORD1_OP2_V2_ALU_INST(x) (((x) >> 7) & 0x7FF) +#define C_SQ_ALU_WORD1_OP2_V2_ALU_INST 0xFFFC007F + +#endif diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c new file mode 100644 index 00000000000..96d45807e09 --- /dev/null +++ b/src/gallium/drivers/r600/r600_state.c @@ -0,0 +1,433 @@ +/* + * Copyright 2010 Jerome Glisse <[email protected]> + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Jerome Glisse + */ +#include <stdio.h> +#include <util/u_inlines.h> +#include <util/u_format.h> +#include <util/u_memory.h> +#include "r600_screen.h" +#include "r600_texture.h" +#include "r600_context.h" +#include "r600d.h" + + +static void r600_delete_state(struct pipe_context *ctx, void *state) +{ + struct radeon_state *rstate = state; + + radeon_state_decref(rstate); +} + +static void *r600_create_blend_state(struct pipe_context *ctx, + const struct pipe_blend_state *state) +{ + struct r600_screen *rscreen = (struct r600_screen*)ctx->screen; + struct radeon_state *rstate; + + rstate = radeon_state(rscreen->rw, R600_BLEND_TYPE, R600_BLEND); + if (rstate == NULL) + return NULL; + rstate->states[R600_BLEND__CB_BLEND_RED] = 0x00000000; + rstate->states[R600_BLEND__CB_BLEND_GREEN] = 0x00000000; + rstate->states[R600_BLEND__CB_BLEND_BLUE] = 0x00000000; + rstate->states[R600_BLEND__CB_BLEND_ALPHA] = 0x00000000; + rstate->states[R600_BLEND__CB_BLEND0_CONTROL] = 0x00010001; + rstate->states[R600_BLEND__CB_BLEND1_CONTROL] = 0x00000000; + rstate->states[R600_BLEND__CB_BLEND2_CONTROL] = 0x00000000; + rstate->states[R600_BLEND__CB_BLEND3_CONTROL] = 0x00000000; + rstate->states[R600_BLEND__CB_BLEND4_CONTROL] = 0x00000000; + rstate->states[R600_BLEND__CB_BLEND5_CONTROL] = 0x00000000; + rstate->states[R600_BLEND__CB_BLEND6_CONTROL] = 0x00000000; + rstate->states[R600_BLEND__CB_BLEND7_CONTROL] = 0x00000000; + rstate->states[R600_BLEND__CB_BLEND_CONTROL] = 0x00000000; + if (radeon_state_pm4(rstate)) { + radeon_state_decref(rstate); + return NULL; + } + return rstate; +} + +static void r600_bind_blend_state(struct pipe_context *ctx, void *state) +{ + struct r600_context *rctx = (struct r600_context*)ctx; + radeon_draw_set(rctx->draw, state); +} + +static void r600_set_blend_color(struct pipe_context *ctx, + const struct pipe_blend_color *color) +{ +} + +static void r600_set_clip_state(struct pipe_context *ctx, + const struct pipe_clip_state *state) +{ +} + +static void r600_set_framebuffer_state(struct pipe_context *ctx, + const struct pipe_framebuffer_state *state) +{ + struct r600_screen *rscreen = (struct r600_screen*)ctx->screen; + struct r600_context *rctx = (struct r600_context*)ctx; + struct r600_texture *rtex; + struct r600_pipe_buffer *rbuffer; + struct radeon_state *rstate; + unsigned level = state->cbufs[0]->level; + unsigned pitch, slice; + + rstate = radeon_state(rscreen->rw, R600_CB0_TYPE, R600_CB0); + if (rstate == NULL) + return; + rtex = (struct r600_texture*)state->cbufs[0]->texture; + rbuffer = (struct r600_pipe_buffer*)rtex->buffer; + rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo); + rstate->bo[1] = radeon_bo_incref(rscreen->rw, rbuffer->bo); + rstate->bo[2] = radeon_bo_incref(rscreen->rw, rbuffer->bo); + rstate->placement[0] = RADEON_GEM_DOMAIN_GTT; + rstate->placement[2] = RADEON_GEM_DOMAIN_GTT; + rstate->placement[4] = RADEON_GEM_DOMAIN_GTT; + rstate->nbo = 3; + pitch = rtex->pitch[level] / 8 - 1; + slice = rtex->pitch[level] * state->cbufs[0]->height / 64 - 1; + rstate->states[R600_CB0__CB_COLOR0_BASE] = 0x00000000; + rstate->states[R600_CB0__CB_COLOR0_INFO] = 0x08110068; + rstate->states[R600_CB0__CB_COLOR0_SIZE] = S_028060_PITCH_TILE_MAX(pitch) | + S_028060_SLICE_TILE_MAX(slice); + rstate->states[R600_CB0__CB_COLOR0_VIEW] = 0x00000000; + rstate->states[R600_CB0__CB_COLOR0_FRAG] = 0x00000000; + rstate->states[R600_CB0__CB_COLOR0_TILE] = 0x00000000; + rstate->states[R600_CB0__CB_COLOR0_MASK] = 0x00000000; + if (radeon_state_pm4(rstate)) { + radeon_state_decref(rstate); + return; + } + radeon_draw_set_new(rctx->draw, rstate); + rctx->db = radeon_state_decref(rctx->db); + rctx->db = radeon_state(rscreen->rw, R600_DB_TYPE, R600_DB); + rctx->db->bo[0] = radeon_bo_incref(rscreen->rw, rstate->bo[0]); + rctx->db->nbo = 1; + rctx->db->placement[0] = RADEON_GEM_DOMAIN_GTT; +} + +static void *r600_create_fs_state(struct pipe_context *ctx, + const struct pipe_shader_state *shader) +{ + return r600_pipe_shader_create(ctx, C_PROGRAM_TYPE_FS, shader->tokens); +} + +static void r600_bind_fs_state(struct pipe_context *ctx, void *state) +{ + struct r600_context *rctx = (struct r600_context*)ctx; + + rctx->ps_shader = state; +} + +static void *r600_create_vs_state(struct pipe_context *ctx, + const struct pipe_shader_state *shader) +{ + return r600_pipe_shader_create(ctx, C_PROGRAM_TYPE_VS, shader->tokens); +} + +static void r600_bind_vs_state(struct pipe_context *ctx, void *state) +{ + struct r600_context *rctx = (struct r600_context*)ctx; + + rctx->vs_shader = state; +} + +static void r600_set_polygon_stipple(struct pipe_context *ctx, + const struct pipe_poly_stipple *state) +{ +} + +static void *r600_create_rs_state(struct pipe_context *ctx, + const struct pipe_rasterizer_state *state) +{ + struct r600_screen *rscreen = (struct r600_screen*)ctx->screen; + struct r600_context *rctx = (struct r600_context*)ctx; + struct radeon_state *rstate; + + rctx->flat_shade = state->flatshade; + rstate = radeon_state(rscreen->rw, R600_RASTERIZER_TYPE, R600_RASTERIZER); + if (rstate == NULL) + return NULL; + rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] = 0x00000001; + rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] = 0x00000000; + rstate->states[R600_RASTERIZER__PA_SU_SC_MODE_CNTL] = 0x00080000; + rstate->states[R600_RASTERIZER__PA_CL_VS_OUT_CNTL] = 0x00000000; + rstate->states[R600_RASTERIZER__PA_CL_NANINF_CNTL] = 0x00000000; + rstate->states[R600_RASTERIZER__PA_SU_POINT_SIZE] = 0x00080008; + rstate->states[R600_RASTERIZER__PA_SU_POINT_MINMAX] = 0x00000000; + rstate->states[R600_RASTERIZER__PA_SU_LINE_CNTL] = 0x00000008; + rstate->states[R600_RASTERIZER__PA_SC_LINE_STIPPLE] = 0x00000005; + rstate->states[R600_RASTERIZER__PA_SC_MPASS_PS_CNTL] = 0x00000000; + rstate->states[R600_RASTERIZER__PA_SC_LINE_CNTL] = 0x00000400; + rstate->states[R600_RASTERIZER__PA_CL_GB_VERT_CLIP_ADJ] = 0x3F800000; + rstate->states[R600_RASTERIZER__PA_CL_GB_VERT_DISC_ADJ] = 0x3F800000; + rstate->states[R600_RASTERIZER__PA_CL_GB_HORZ_CLIP_ADJ] = 0x3F800000; + rstate->states[R600_RASTERIZER__PA_CL_GB_HORZ_DISC_ADJ] = 0x3F800000; + rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_DB_FMT_CNTL] = 0x00000000; + rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_CLAMP] = 0x00000000; + rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_SCALE] = 0x00000000; + rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_OFFSET] = 0x00000000; + rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_SCALE] = 0x00000000; + rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_OFFSET] = 0x00000000; + if (radeon_state_pm4(rstate)) { + radeon_state_decref(rstate); + return NULL; + } + return rstate; +} + +static void r600_bind_rs_state(struct pipe_context *ctx, void *state) +{ + struct r600_context *rctx = (struct r600_context*)ctx; + radeon_draw_set(rctx->draw, state); +} + +static void *r600_create_sampler_state(struct pipe_context *ctx, + const struct pipe_sampler_state *state) +{ + return NULL; +} + +static void r600_bind_sampler_states(struct pipe_context *ctx, + unsigned count, void **states) +{ +} + +static void r600_set_sampler_textures(struct pipe_context *ctx, + unsigned count, + struct pipe_texture **texture) +{ +} + +static void r600_set_scissor_state(struct pipe_context *ctx, + const struct pipe_scissor_state *state) +{ + struct r600_screen *rscreen = (struct r600_screen*)ctx->screen; + struct r600_context *rctx = (struct r600_context*)ctx; + struct radeon_state *rstate; + u32 tl, br; + + tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) | S_028240_WINDOW_OFFSET_DISABLE(1); + br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy); + rstate = radeon_state(rscreen->rw, R600_SCISSOR_TYPE, R600_SCISSOR); + if (rstate == NULL) + return; + rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_TL] = tl; + rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_BR] = br; + rstate->states[R600_SCISSOR__PA_SC_WINDOW_OFFSET] = 0x00000000; + rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_TL] = tl; + rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_BR] = br; + rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_RULE] = 0x0000FFFF; + rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_0_TL] = tl; + rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_0_BR] = br; + rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_1_TL] = tl; + rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_1_BR] = br; + rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_2_TL] = tl; + rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_2_BR] = br; + rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_3_TL] = tl; + rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_3_BR] = br; + rstate->states[R600_SCISSOR__PA_SC_EDGERULE] = 0xAAAAAAAA; + rstate->states[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_TL] = tl; + rstate->states[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_BR] = br; + rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL] = tl; + rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR] = br; + if (radeon_state_pm4(rstate)) { + radeon_state_decref(rstate); + return; + } + radeon_draw_set_new(rctx->draw, rstate); +} + +static void r600_set_viewport_state(struct pipe_context *ctx, + const struct pipe_viewport_state *state) +{ + struct r600_screen *rscreen = (struct r600_screen*)ctx->screen; + struct r600_context *rctx = (struct r600_context*)ctx; + struct radeon_state *rstate; + + rstate = radeon_state(rscreen->rw, R600_VIEWPORT_TYPE, R600_VIEWPORT); + if (rstate == NULL) + return; + rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMIN_0] = 0x00000000; + rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMAX_0] = 0x3F800000; + rstate->states[R600_VIEWPORT__PA_CL_VPORT_XSCALE_0] = r600_float_to_u32(state->scale[0]); + rstate->states[R600_VIEWPORT__PA_CL_VPORT_YSCALE_0] = r600_float_to_u32(state->scale[1]); + rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZSCALE_0] = r600_float_to_u32(state->scale[2]); + rstate->states[R600_VIEWPORT__PA_CL_VPORT_XOFFSET_0] = r600_float_to_u32(state->translate[0]); + rstate->states[R600_VIEWPORT__PA_CL_VPORT_YOFFSET_0] = r600_float_to_u32(state->translate[1]); + rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZOFFSET_0] = r600_float_to_u32(state->translate[2]); + rstate->states[R600_VIEWPORT__PA_CL_VTE_CNTL] = 0x0000043F; + if (radeon_state_pm4(rstate)) { + radeon_state_decref(rstate); + return; + } + radeon_draw_set_new(rctx->draw, rstate); +} + +static void r600_set_vertex_buffers(struct pipe_context *ctx, + unsigned count, + const struct pipe_vertex_buffer *buffers) +{ + struct r600_context *rctx = (struct r600_context*)ctx; + + memcpy(rctx->vertex_buffer, buffers, sizeof(struct pipe_vertex_buffer) * count); + rctx->nvertex_buffer = count; +} + +static void r600_set_vertex_elements(struct pipe_context *ctx, + unsigned count, + const struct pipe_vertex_element *elements) +{ + struct r600_context *rctx = (struct r600_context*)ctx; + + memcpy(rctx->vertex_element, elements, sizeof(struct pipe_vertex_element) * count); + rctx->nvertex_element = count; +} + +static void *r600_create_dsa_state(struct pipe_context *ctx, + const struct pipe_depth_stencil_alpha_state *state) +{ + struct r600_screen *rscreen = (struct r600_screen*)ctx->screen; + struct radeon_state *rstate; + + rstate = radeon_state(rscreen->rw, R600_DSA_TYPE, R600_DSA); + if (rstate == NULL) + return NULL; + rstate->states[R600_DSA__DB_STENCIL_CLEAR] = 0x00000000; + rstate->states[R600_DSA__DB_DEPTH_CLEAR] = 0x3F800000; + rstate->states[R600_DSA__SX_ALPHA_TEST_CONTROL] = 0x00000000; + rstate->states[R600_DSA__DB_STENCILREFMASK] = 0xFFFFFF00; + rstate->states[R600_DSA__DB_STENCILREFMASK_BF] = 0xFFFFFF00; + rstate->states[R600_DSA__SX_ALPHA_REF] = 0x00000000; + rstate->states[R600_DSA__SPI_FOG_FUNC_SCALE] = 0x00000000; + rstate->states[R600_DSA__SPI_FOG_FUNC_BIAS] = 0x00000000; + rstate->states[R600_DSA__SPI_FOG_CNTL] = 0x00000000; + rstate->states[R600_DSA__DB_DEPTH_CONTROL] = 0x00700700; + rstate->states[R600_DSA__DB_SHADER_CONTROL] = 0x00000210; + rstate->states[R600_DSA__DB_RENDER_CONTROL] = 0x00000060; + rstate->states[R600_DSA__DB_RENDER_OVERRIDE] = 0x0000002A; + rstate->states[R600_DSA__DB_SRESULTS_COMPARE_STATE1] = 0x00000000; + rstate->states[R600_DSA__DB_PRELOAD_CONTROL] = 0x00000000; + rstate->states[R600_DSA__DB_ALPHA_TO_MASK] = 0x0000AA00; + if (radeon_state_pm4(rstate)) { + radeon_state_decref(rstate); + return NULL; + } + return rstate; +} + +static void r600_bind_dsa_state(struct pipe_context *ctx, void *state) +{ + struct r600_context *rctx = (struct r600_context*)ctx; + radeon_draw_set(rctx->draw, state); +} + +static void r600_set_constant_buffer(struct pipe_context *ctx, + uint shader, uint index, + struct pipe_buffer *buffer) +{ + struct r600_screen *rscreen = (struct r600_screen*)ctx->screen; + struct r600_context *rctx = (struct r600_context*)ctx; + unsigned nconstant = 0, i, type, id; + struct radeon_state *rstate; + u32 *ptr; + + switch (shader) { + case PIPE_SHADER_VERTEX: + id = R600_VS_CONSTANT; + type = R600_VS_CONSTANT_TYPE; + break; + case PIPE_SHADER_FRAGMENT: + id = R600_PS_CONSTANT; + type = R600_PS_CONSTANT_TYPE; + break; + default: + fprintf(stderr, "%s:%d unsupported %d\n", __func__, __LINE__, shader); + return; + } + if (buffer && buffer->size > 0) { + nconstant = buffer->size / 16; + ptr = pipe_buffer_map(ctx->screen, buffer, PIPE_BUFFER_USAGE_CPU_READ); + if (ptr == NULL) + return; + for (i = 0; i < nconstant; i++) { + rstate = radeon_state(rscreen->rw, type, id + i); + if (rstate == NULL) + return; + rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT0_0] = ptr[i * 4 + 0]; + rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT1_0] = ptr[i * 4 + 1]; + rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT2_0] = ptr[i * 4 + 2]; + rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT3_0] = ptr[i * 4 + 3]; + if (radeon_state_pm4(rstate)) + return; + if (radeon_draw_set_new(rctx->draw, rstate)) + return; + } + pipe_buffer_unmap(ctx->screen, buffer); + } +} + +static void r600_set_stencil_ref(struct pipe_context *ctx, + const struct pipe_stencil_ref *sr) +{ + struct r600_context *rctx = (struct r600_context*)ctx; + rctx->stencil_ref = *sr; +} + +void r600_init_state_functions(struct r600_context *rctx) +{ + rctx->context.create_blend_state = r600_create_blend_state; + rctx->context.bind_blend_state = r600_bind_blend_state; + rctx->context.delete_blend_state = r600_delete_state; + rctx->context.set_blend_color = r600_set_blend_color; + rctx->context.set_clip_state = r600_set_clip_state; + rctx->context.set_constant_buffer = r600_set_constant_buffer; + rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state; + rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state; + rctx->context.delete_depth_stencil_alpha_state = r600_delete_state; + rctx->context.set_framebuffer_state = r600_set_framebuffer_state; + rctx->context.create_fs_state = r600_create_fs_state; + rctx->context.bind_fs_state = r600_bind_fs_state; + rctx->context.delete_fs_state = r600_delete_state; + rctx->context.set_polygon_stipple = r600_set_polygon_stipple; + rctx->context.create_rasterizer_state = r600_create_rs_state; + rctx->context.bind_rasterizer_state = r600_bind_rs_state; + rctx->context.delete_rasterizer_state = r600_delete_state; + rctx->context.create_sampler_state = r600_create_sampler_state; + rctx->context.bind_fragment_sampler_states = r600_bind_sampler_states; + rctx->context.bind_vertex_sampler_states = r600_bind_sampler_states; + rctx->context.delete_sampler_state = r600_delete_state; + rctx->context.set_fragment_sampler_textures = r600_set_sampler_textures; + rctx->context.set_scissor_state = r600_set_scissor_state; + rctx->context.set_viewport_state = r600_set_viewport_state; + rctx->context.set_vertex_buffers = r600_set_vertex_buffers; + rctx->context.set_vertex_elements = r600_set_vertex_elements; + rctx->context.create_vs_state = r600_create_vs_state; + rctx->context.bind_vs_state = r600_bind_vs_state; + rctx->context.delete_vs_state = r600_delete_state; + rctx->context.set_stencil_ref = r600_set_stencil_ref; +} diff --git a/src/gallium/drivers/r600/r600_texture.c b/src/gallium/drivers/r600/r600_texture.c new file mode 100644 index 00000000000..708f9effa32 --- /dev/null +++ b/src/gallium/drivers/r600/r600_texture.c @@ -0,0 +1,198 @@ +/* + * Copyright 2010 Jerome Glisse <[email protected]> + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Jerome Glisse + * Corbin Simpson + */ +#include <pipe/p_screen.h> +#include <util/u_format.h> +#include <util/u_math.h> +#include <util/u_inlines.h> +#include <util/u_memory.h> +#include "r600_screen.h" +#include "r600_texture.h" + +unsigned long r600_texture_get_offset(struct r600_texture *rtex, unsigned level, unsigned zslice, unsigned face) +{ + unsigned long offset = rtex->offset[level]; + + switch (rtex->tex.target) { + case PIPE_TEXTURE_3D: + assert(face == 0); + return offset + zslice * rtex->layer_size[level]; + case PIPE_TEXTURE_CUBE: + assert(zslice == 0); + return offset + face * rtex->layer_size[level]; + default: + assert(zslice == 0 && face == 0); + return offset; + } +} + +static void r600_setup_miptree(struct r600_screen *rscreen, struct r600_texture *rtex) +{ + struct pipe_texture *ptex = &rtex->tex; + unsigned long w, h, stride, size, layer_size, i, offset; + + for (i = 0, offset = 0; i <= ptex->last_level; i++) { + w = u_minify(ptex->width0, i); + h = u_minify(ptex->height0, i); + stride = align(util_format_get_stride(ptex->format, w), 32); + layer_size = stride * h; + if (ptex->target == PIPE_TEXTURE_CUBE) + size = layer_size * 6; + else + size = layer_size * u_minify(ptex->depth0, i); + rtex->offset[i] = offset; + rtex->layer_size[i] = layer_size; + rtex->pitch[i] = stride / util_format_get_blocksize(ptex->format); + rtex->stride[i] = stride; + offset += align(size, 32); + } + rtex->size = offset; +} + +static struct pipe_texture *r600_texture_create(struct pipe_screen *screen, const struct pipe_texture *template) +{ + struct r600_texture *rtex = CALLOC_STRUCT(r600_texture); + struct r600_screen *rscreen = r600_screen(screen); + + if (!rtex) { + return NULL; + } + rtex->tex = *template; + pipe_reference_init(&rtex->tex.reference, 1); + rtex->tex.screen = screen; + r600_setup_miptree(rscreen, rtex); + rtex->buffer = screen->buffer_create(screen, 4096, PIPE_BUFFER_USAGE_PIXEL, rtex->size); + if (!rtex->buffer) { + FREE(rtex); + return NULL; + } + return (struct pipe_texture*)&rtex->tex; +} + +static void r600_texture_destroy(struct pipe_texture *ptex) +{ + struct r600_texture *rtex = (struct r600_texture*)ptex; + + pipe_buffer_reference(&rtex->buffer, NULL); + FREE(rtex); +} + +static struct pipe_surface *r600_get_tex_surface(struct pipe_screen *screen, + struct pipe_texture *texture, + unsigned face, unsigned level, + unsigned zslice, unsigned flags) +{ + struct r600_texture *rtex = (struct r600_texture*)texture; + struct pipe_surface *surface = CALLOC_STRUCT(pipe_surface); + unsigned long offset; + + if (surface == NULL) + return NULL; + offset = r600_texture_get_offset(rtex, level, zslice, face); + pipe_reference_init(&surface->reference, 1); + pipe_texture_reference(&surface->texture, texture); + surface->format = texture->format; + surface->width = u_minify(texture->width0, level); + surface->height = u_minify(texture->height0, level); + surface->offset = offset; + surface->usage = flags; + surface->zslice = zslice; + surface->texture = texture; + surface->face = face; + surface->level = level; + return surface; +} + +static void r600_tex_surface_destroy(struct pipe_surface *surface) +{ + pipe_texture_reference(&surface->texture, NULL); + FREE(surface); +} + +static struct pipe_texture *r600_texture_blanket(struct pipe_screen *screen, + const struct pipe_texture *base, + const unsigned *stride, + struct pipe_buffer *buffer) +{ + struct r600_texture *rtex; + + /* Support only 2D textures without mipmaps */ + if (base->target != PIPE_TEXTURE_2D || base->depth0 != 1 || base->last_level != 0) + return NULL; + rtex = CALLOC_STRUCT(r600_texture); + if (rtex == NULL) + return NULL; + rtex->tex = *base; + pipe_reference_init(&rtex->tex.reference, 1); + rtex->tex.screen = screen; + rtex->stride_override = *stride; + rtex->pitch[0] = *stride / util_format_get_blocksize(base->format); + rtex->stride[0] = *stride; + rtex->offset[0] = 0; + rtex->size = align(rtex->stride[0] * base->height0, 32); + pipe_buffer_reference(&rtex->buffer, buffer); + return &rtex->tex; +} + +static struct pipe_video_surface *r600_video_surface_create(struct pipe_screen *screen, + enum pipe_video_chroma_format chroma_format, + unsigned width, unsigned height) +{ + return NULL; +} + +static void r600_video_surface_destroy(struct pipe_video_surface *vsfc) +{ + FREE(vsfc); +} + +void r600_init_screen_texture_functions(struct pipe_screen *screen) +{ + screen->texture_create = r600_texture_create; + screen->texture_destroy = r600_texture_destroy; + screen->get_tex_surface = r600_get_tex_surface; + screen->tex_surface_destroy = r600_tex_surface_destroy; + screen->texture_blanket = r600_texture_blanket; + screen->video_surface_create = r600_video_surface_create; + screen->video_surface_destroy= r600_video_surface_destroy; +} + +boolean r600_get_texture_buffer(struct pipe_screen *screen, + struct pipe_texture *texture, + struct pipe_buffer **buffer, + unsigned *stride) +{ + struct r600_texture *rtex = (struct r600_texture*)texture; + + if (rtex == NULL) { + return FALSE; + } + pipe_buffer_reference(buffer, rtex->buffer); + if (stride) { + *stride = rtex->stride[0]; + } + return TRUE; +} diff --git a/src/gallium/drivers/r600/r600_texture.h b/src/gallium/drivers/r600/r600_texture.h new file mode 100644 index 00000000000..a4424161ebc --- /dev/null +++ b/src/gallium/drivers/r600/r600_texture.h @@ -0,0 +1,46 @@ +/* + * Copyright 2010 Jerome Glisse <[email protected]> + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef R600_TEXTURE_H +#define R600_TEXTURE_H + +#include <pipe/p_state.h> + +struct r600_texture { + struct pipe_texture tex; + unsigned long offset[PIPE_MAX_TEXTURE_LEVELS]; + unsigned long pitch[PIPE_MAX_TEXTURE_LEVELS]; + unsigned long stride[PIPE_MAX_TEXTURE_LEVELS]; + unsigned long layer_size[PIPE_MAX_TEXTURE_LEVELS]; + unsigned long stride_override; + unsigned long size; + struct pipe_buffer *buffer; +}; + +unsigned long r600_texture_get_offset(struct r600_texture *rtex, unsigned level, unsigned zslice, unsigned face); +void r600_init_screen_texture_functions(struct pipe_screen *screen); +boolean r600_get_texture_buffer(struct pipe_screen *screen, + struct pipe_texture *texture, + struct pipe_buffer **buffer, + unsigned *stride); + +#endif diff --git a/src/gallium/drivers/r600/r600d.h b/src/gallium/drivers/r600/r600d.h new file mode 100644 index 00000000000..d2c7248ff2b --- /dev/null +++ b/src/gallium/drivers/r600/r600d.h @@ -0,0 +1,677 @@ +/* + * Copyright 2010 Jerome Glisse <[email protected]> + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Jerome Glisse + */ +#ifndef R600D_H +#define R600D_H + +#define PKT3_NOP 0x10 +#define PKT3_INDIRECT_BUFFER_END 0x17 +#define PKT3_SET_PREDICATION 0x20 +#define PKT3_REG_RMW 0x21 +#define PKT3_COND_EXEC 0x22 +#define PKT3_PRED_EXEC 0x23 +#define PKT3_START_3D_CMDBUF 0x24 +#define PKT3_DRAW_INDEX_2 0x27 +#define PKT3_CONTEXT_CONTROL 0x28 +#define PKT3_DRAW_INDEX_IMMD_BE 0x29 +#define PKT3_INDEX_TYPE 0x2A +#define PKT3_DRAW_INDEX 0x2B +#define PKT3_DRAW_INDEX_AUTO 0x2D +#define PKT3_DRAW_INDEX_IMMD 0x2E +#define PKT3_NUM_INSTANCES 0x2F +#define PKT3_STRMOUT_BUFFER_UPDATE 0x34 +#define PKT3_INDIRECT_BUFFER_MP 0x38 +#define PKT3_MEM_SEMAPHORE 0x39 +#define PKT3_MPEG_INDEX 0x3A +#define PKT3_WAIT_REG_MEM 0x3C +#define PKT3_MEM_WRITE 0x3D +#define PKT3_INDIRECT_BUFFER 0x32 +#define PKT3_CP_INTERRUPT 0x40 +#define PKT3_SURFACE_SYNC 0x43 +#define PKT3_ME_INITIALIZE 0x44 +#define PKT3_COND_WRITE 0x45 +#define PKT3_EVENT_WRITE 0x46 +#define PKT3_EVENT_WRITE_EOP 0x47 +#define PKT3_ONE_REG_WRITE 0x57 +#define PKT3_SET_CONFIG_REG 0x68 +#define PKT3_SET_CONTEXT_REG 0x69 +#define PKT3_SET_ALU_CONST 0x6A +#define PKT3_SET_BOOL_CONST 0x6B +#define PKT3_SET_LOOP_CONST 0x6C +#define PKT3_SET_RESOURCE 0x6D +#define PKT3_SET_SAMPLER 0x6E +#define PKT3_SET_CTL_CONST 0x6F +#define PKT3_SURFACE_BASE_UPDATE 0x73 + +#define PKT_TYPE_S(x) (((x) & 0x3) << 30) +#define PKT_TYPE_G(x) (((x) >> 30) & 0x3) +#define PKT_TYPE_C 0x3FFFFFFF +#define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16) +#define PKT_COUNT_G(x) (((x) >> 16) & 0x3FFF) +#define PKT_COUNT_C 0xC000FFFF +#define PKT0_BASE_INDEX_S(x) (((x) & 0xFFFF) << 0) +#define PKT0_BASE_INDEX_G(x) (((x) >> 0) & 0xFFFF) +#define PKT0_BASE_INDEX_C 0xFFFF0000 +#define PKT3_IT_OPCODE_S(x) (((x) & 0xFF) << 8) +#define PKT3_IT_OPCODE_G(x) (((x) >> 8) & 0xFF) +#define PKT3_IT_OPCODE_C 0xFFFF00FF +#define PKT0(index, count) (PKT_TYPE_S(0) | PKT0_BASE_INDEX_S(index) | PKT_COUNT_S(count)) +#define PKT3(op, count) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count)) + +/* Registers */ +#define R_0280A0_CB_COLOR0_INFO 0x0280A0 +#define S_0280A0_ENDIAN(x) (((x) & 0x3) << 0) +#define G_0280A0_ENDIAN(x) (((x) >> 0) & 0x3) +#define C_0280A0_ENDIAN 0xFFFFFFFC +#define S_0280A0_FORMAT(x) (((x) & 0x3F) << 2) +#define G_0280A0_FORMAT(x) (((x) >> 2) & 0x3F) +#define C_0280A0_FORMAT 0xFFFFFF03 +#define V_0280A0_COLOR_INVALID 0x00000000 +#define V_0280A0_COLOR_8 0x00000001 +#define V_0280A0_COLOR_4_4 0x00000002 +#define V_0280A0_COLOR_3_3_2 0x00000003 +#define V_0280A0_COLOR_16 0x00000005 +#define V_0280A0_COLOR_16_FLOAT 0x00000006 +#define V_0280A0_COLOR_8_8 0x00000007 +#define V_0280A0_COLOR_5_6_5 0x00000008 +#define V_0280A0_COLOR_6_5_5 0x00000009 +#define V_0280A0_COLOR_1_5_5_5 0x0000000A +#define V_0280A0_COLOR_4_4_4_4 0x0000000B +#define V_0280A0_COLOR_5_5_5_1 0x0000000C +#define V_0280A0_COLOR_32 0x0000000D +#define V_0280A0_COLOR_32_FLOAT 0x0000000E +#define V_0280A0_COLOR_16_16 0x0000000F +#define V_0280A0_COLOR_16_16_FLOAT 0x00000010 +#define V_0280A0_COLOR_8_24 0x00000011 +#define V_0280A0_COLOR_8_24_FLOAT 0x00000012 +#define V_0280A0_COLOR_24_8 0x00000013 +#define V_0280A0_COLOR_24_8_FLOAT 0x00000014 +#define V_0280A0_COLOR_10_11_11 0x00000015 +#define V_0280A0_COLOR_10_11_11_FLOAT 0x00000016 +#define V_0280A0_COLOR_11_11_10 0x00000017 +#define V_0280A0_COLOR_11_11_10_FLOAT 0x00000018 +#define V_0280A0_COLOR_2_10_10_10 0x00000019 +#define V_0280A0_COLOR_8_8_8_8 0x0000001A +#define V_0280A0_COLOR_10_10_10_2 0x0000001B +#define V_0280A0_COLOR_X24_8_32_FLOAT 0x0000001C +#define V_0280A0_COLOR_32_32 0x0000001D +#define V_0280A0_COLOR_32_32_FLOAT 0x0000001E +#define V_0280A0_COLOR_16_16_16_16 0x0000001F +#define V_0280A0_COLOR_16_16_16_16_FLOAT 0x00000020 +#define V_0280A0_COLOR_32_32_32_32 0x00000022 +#define V_0280A0_COLOR_32_32_32_32_FLOAT 0x00000023 +#define S_0280A0_ARRAY_MODE(x) (((x) & 0xF) << 8) +#define G_0280A0_ARRAY_MODE(x) (((x) >> 8) & 0xF) +#define C_0280A0_ARRAY_MODE 0xFFFFF0FF +#define V_0280A0_ARRAY_LINEAR_GENERAL 0x00000000 +#define V_0280A0_ARRAY_LINEAR_ALIGNED 0x00000001 +#define V_0280A0_ARRAY_1D_TILED_THIN1 0x00000002 +#define V_0280A0_ARRAY_2D_TILED_THIN1 0x00000004 +#define S_0280A0_NUMBER_TYPE(x) (((x) & 0x7) << 12) +#define G_0280A0_NUMBER_TYPE(x) (((x) >> 12) & 0x7) +#define C_0280A0_NUMBER_TYPE 0xFFFF8FFF +#define S_0280A0_READ_SIZE(x) (((x) & 0x1) << 15) +#define G_0280A0_READ_SIZE(x) (((x) >> 15) & 0x1) +#define C_0280A0_READ_SIZE 0xFFFF7FFF +#define S_0280A0_COMP_SWAP(x) (((x) & 0x3) << 16) +#define G_0280A0_COMP_SWAP(x) (((x) >> 16) & 0x3) +#define C_0280A0_COMP_SWAP 0xFFFCFFFF +#define S_0280A0_TILE_MODE(x) (((x) & 0x3) << 18) +#define G_0280A0_TILE_MODE(x) (((x) >> 18) & 0x3) +#define C_0280A0_TILE_MODE 0xFFF3FFFF +#define S_0280A0_BLEND_CLAMP(x) (((x) & 0x1) << 20) +#define G_0280A0_BLEND_CLAMP(x) (((x) >> 20) & 0x1) +#define C_0280A0_BLEND_CLAMP 0xFFEFFFFF +#define S_0280A0_CLEAR_COLOR(x) (((x) & 0x1) << 21) +#define G_0280A0_CLEAR_COLOR(x) (((x) >> 21) & 0x1) +#define C_0280A0_CLEAR_COLOR 0xFFDFFFFF +#define S_0280A0_BLEND_BYPASS(x) (((x) & 0x1) << 22) +#define G_0280A0_BLEND_BYPASS(x) (((x) >> 22) & 0x1) +#define C_0280A0_BLEND_BYPASS 0xFFBFFFFF +#define S_0280A0_BLEND_FLOAT32(x) (((x) & 0x1) << 23) +#define G_0280A0_BLEND_FLOAT32(x) (((x) >> 23) & 0x1) +#define C_0280A0_BLEND_FLOAT32 0xFF7FFFFF +#define S_0280A0_SIMPLE_FLOAT(x) (((x) & 0x1) << 24) +#define G_0280A0_SIMPLE_FLOAT(x) (((x) >> 24) & 0x1) +#define C_0280A0_SIMPLE_FLOAT 0xFEFFFFFF +#define S_0280A0_ROUND_MODE(x) (((x) & 0x1) << 25) +#define G_0280A0_ROUND_MODE(x) (((x) >> 25) & 0x1) +#define C_0280A0_ROUND_MODE 0xFDFFFFFF +#define S_0280A0_TILE_COMPACT(x) (((x) & 0x1) << 26) +#define G_0280A0_TILE_COMPACT(x) (((x) >> 26) & 0x1) +#define C_0280A0_TILE_COMPACT 0xFBFFFFFF +#define S_0280A0_SOURCE_FORMAT(x) (((x) & 0x1) << 27) +#define G_0280A0_SOURCE_FORMAT(x) (((x) >> 27) & 0x1) +#define C_0280A0_SOURCE_FORMAT 0xF7FFFFFF +#define R_028060_CB_COLOR0_SIZE 0x028060 +#define S_028060_PITCH_TILE_MAX(x) (((x) & 0x3FF) << 0) +#define G_028060_PITCH_TILE_MAX(x) (((x) >> 0) & 0x3FF) +#define C_028060_PITCH_TILE_MAX 0xFFFFFC00 +#define S_028060_SLICE_TILE_MAX(x) (((x) & 0xFFFFF) << 10) +#define G_028060_SLICE_TILE_MAX(x) (((x) >> 10) & 0xFFFFF) +#define C_028060_SLICE_TILE_MAX 0xC00003FF +#define R_028800_DB_DEPTH_CONTROL 0x028800 +#define S_028800_STENCIL_ENABLE(x) (((x) & 0x1) << 0) +#define G_028800_STENCIL_ENABLE(x) (((x) >> 0) & 0x1) +#define C_028800_STENCIL_ENABLE 0xFFFFFFFE +#define S_028800_Z_ENABLE(x) (((x) & 0x1) << 1) +#define G_028800_Z_ENABLE(x) (((x) >> 1) & 0x1) +#define C_028800_Z_ENABLE 0xFFFFFFFD +#define S_028800_Z_WRITE_ENABLE(x) (((x) & 0x1) << 2) +#define G_028800_Z_WRITE_ENABLE(x) (((x) >> 2) & 0x1) +#define C_028800_Z_WRITE_ENABLE 0xFFFFFFFB +#define S_028800_ZFUNC(x) (((x) & 0x7) << 4) +#define G_028800_ZFUNC(x) (((x) >> 4) & 0x7) +#define C_028800_ZFUNC 0xFFFFFF8F +#define S_028800_BACKFACE_ENABLE(x) (((x) & 0x1) << 7) +#define G_028800_BACKFACE_ENABLE(x) (((x) >> 7) & 0x1) +#define C_028800_BACKFACE_ENABLE 0xFFFFFF7F +#define S_028800_STENCILFUNC(x) (((x) & 0x7) << 8) +#define G_028800_STENCILFUNC(x) (((x) >> 8) & 0x7) +#define C_028800_STENCILFUNC 0xFFFFF8FF +#define S_028800_STENCILFAIL(x) (((x) & 0x7) << 11) +#define G_028800_STENCILFAIL(x) (((x) >> 11) & 0x7) +#define C_028800_STENCILFAIL 0xFFFFC7FF +#define S_028800_STENCILZPASS(x) (((x) & 0x7) << 14) +#define G_028800_STENCILZPASS(x) (((x) >> 14) & 0x7) +#define C_028800_STENCILZPASS 0xFFFE3FFF +#define S_028800_STENCILZFAIL(x) (((x) & 0x7) << 17) +#define G_028800_STENCILZFAIL(x) (((x) >> 17) & 0x7) +#define C_028800_STENCILZFAIL 0xFFF1FFFF +#define S_028800_STENCILFUNC_BF(x) (((x) & 0x7) << 20) +#define G_028800_STENCILFUNC_BF(x) (((x) >> 20) & 0x7) +#define C_028800_STENCILFUNC_BF 0xFF8FFFFF +#define S_028800_STENCILFAIL_BF(x) (((x) & 0x7) << 23) +#define G_028800_STENCILFAIL_BF(x) (((x) >> 23) & 0x7) +#define C_028800_STENCILFAIL_BF 0xFC7FFFFF +#define S_028800_STENCILZPASS_BF(x) (((x) & 0x7) << 26) +#define G_028800_STENCILZPASS_BF(x) (((x) >> 26) & 0x7) +#define C_028800_STENCILZPASS_BF 0xE3FFFFFF +#define S_028800_STENCILZFAIL_BF(x) (((x) & 0x7) << 29) +#define G_028800_STENCILZFAIL_BF(x) (((x) >> 29) & 0x7) +#define C_028800_STENCILZFAIL_BF 0x1FFFFFFF +#define R_028010_DB_DEPTH_INFO 0x028010 +#define S_028010_FORMAT(x) (((x) & 0x7) << 0) +#define G_028010_FORMAT(x) (((x) >> 0) & 0x7) +#define C_028010_FORMAT 0xFFFFFFF8 +#define V_028010_DEPTH_INVALID 0x00000000 +#define V_028010_DEPTH_16 0x00000001 +#define V_028010_DEPTH_X8_24 0x00000002 +#define V_028010_DEPTH_8_24 0x00000003 +#define V_028010_DEPTH_X8_24_FLOAT 0x00000004 +#define V_028010_DEPTH_8_24_FLOAT 0x00000005 +#define V_028010_DEPTH_32_FLOAT 0x00000006 +#define V_028010_DEPTH_X24_8_32_FLOAT 0x00000007 +#define S_028010_READ_SIZE(x) (((x) & 0x1) << 3) +#define G_028010_READ_SIZE(x) (((x) >> 3) & 0x1) +#define C_028010_READ_SIZE 0xFFFFFFF7 +#define S_028010_ARRAY_MODE(x) (((x) & 0xF) << 15) +#define G_028010_ARRAY_MODE(x) (((x) >> 15) & 0xF) +#define C_028010_ARRAY_MODE 0xFFF87FFF +#define S_028010_TILE_SURFACE_ENABLE(x) (((x) & 0x1) << 25) +#define G_028010_TILE_SURFACE_ENABLE(x) (((x) >> 25) & 0x1) +#define C_028010_TILE_SURFACE_ENABLE 0xFDFFFFFF +#define S_028010_TILE_COMPACT(x) (((x) & 0x1) << 26) +#define G_028010_TILE_COMPACT(x) (((x) >> 26) & 0x1) +#define C_028010_TILE_COMPACT 0xFBFFFFFF +#define S_028010_ZRANGE_PRECISION(x) (((x) & 0x1) << 31) +#define G_028010_ZRANGE_PRECISION(x) (((x) >> 31) & 0x1) +#define C_028010_ZRANGE_PRECISION 0x7FFFFFFF +#define R_028000_DB_DEPTH_SIZE 0x028000 +#define S_028000_PITCH_TILE_MAX(x) (((x) & 0x3FF) << 0) +#define G_028000_PITCH_TILE_MAX(x) (((x) >> 0) & 0x3FF) +#define C_028000_PITCH_TILE_MAX 0xFFFFFC00 +#define S_028000_SLICE_TILE_MAX(x) (((x) & 0xFFFFF) << 10) +#define G_028000_SLICE_TILE_MAX(x) (((x) >> 10) & 0xFFFFF) +#define C_028000_SLICE_TILE_MAX 0xC00003FF +#define R_028004_DB_DEPTH_VIEW 0x028004 +#define S_028004_SLICE_START(x) (((x) & 0x7FF) << 0) +#define G_028004_SLICE_START(x) (((x) >> 0) & 0x7FF) +#define C_028004_SLICE_START 0xFFFFF800 +#define S_028004_SLICE_MAX(x) (((x) & 0x7FF) << 13) +#define G_028004_SLICE_MAX(x) (((x) >> 13) & 0x7FF) +#define C_028004_SLICE_MAX 0xFF001FFF +#define R_028D24_DB_HTILE_SURFACE 0x028D24 +#define S_028D24_HTILE_WIDTH(x) (((x) & 0x1) << 0) +#define G_028D24_HTILE_WIDTH(x) (((x) >> 0) & 0x1) +#define C_028D24_HTILE_WIDTH 0xFFFFFFFE +#define S_028D24_HTILE_HEIGHT(x) (((x) & 0x1) << 1) +#define G_028D24_HTILE_HEIGHT(x) (((x) >> 1) & 0x1) +#define C_028D24_HTILE_HEIGHT 0xFFFFFFFD +#define S_028D24_LINEAR(x) (((x) & 0x1) << 2) +#define G_028D24_LINEAR(x) (((x) >> 2) & 0x1) +#define C_028D24_LINEAR 0xFFFFFFFB +#define S_028D24_FULL_CACHE(x) (((x) & 0x1) << 3) +#define G_028D24_FULL_CACHE(x) (((x) >> 3) & 0x1) +#define C_028D24_FULL_CACHE 0xFFFFFFF7 +#define S_028D24_HTILE_USES_PRELOAD_WIN(x) (((x) & 0x1) << 4) +#define G_028D24_HTILE_USES_PRELOAD_WIN(x) (((x) >> 4) & 0x1) +#define C_028D24_HTILE_USES_PRELOAD_WIN 0xFFFFFFEF +#define S_028D24_PRELOAD(x) (((x) & 0x1) << 5) +#define G_028D24_PRELOAD(x) (((x) >> 5) & 0x1) +#define C_028D24_PRELOAD 0xFFFFFFDF +#define S_028D24_PREFETCH_WIDTH(x) (((x) & 0x3F) << 6) +#define G_028D24_PREFETCH_WIDTH(x) (((x) >> 6) & 0x3F) +#define C_028D24_PREFETCH_WIDTH 0xFFFFF03F +#define S_028D24_PREFETCH_HEIGHT(x) (((x) & 0x3F) << 12) +#define G_028D24_PREFETCH_HEIGHT(x) (((x) >> 12) & 0x3F) +#define C_028D24_PREFETCH_HEIGHT 0xFFFC0FFF +#define R_028D34_DB_PREFETCH_LIMIT 0x028D34 +#define S_028D34_DEPTH_HEIGHT_TILE_MAX(x) (((x) & 0x3FF) << 0) +#define G_028D34_DEPTH_HEIGHT_TILE_MAX(x) (((x) >> 0) & 0x3FF) +#define C_028D34_DEPTH_HEIGHT_TILE_MAX 0xFFFFFC00 +#define R_028D10_DB_RENDER_OVERRIDE 0x028D10 +#define S_028D10_FORCE_HIZ_ENABLE(x) (((x) & 0x3) << 0) +#define G_028D10_FORCE_HIZ_ENABLE(x) (((x) >> 0) & 0x3) +#define C_028D10_FORCE_HIZ_ENABLE 0xFFFFFFFC +#define S_028D10_FORCE_HIS_ENABLE0(x) (((x) & 0x3) << 2) +#define G_028D10_FORCE_HIS_ENABLE0(x) (((x) >> 2) & 0x3) +#define C_028D10_FORCE_HIS_ENABLE0 0xFFFFFFF3 +#define S_028D10_FORCE_HIS_ENABLE1(x) (((x) & 0x3) << 4) +#define G_028D10_FORCE_HIS_ENABLE1(x) (((x) >> 4) & 0x3) +#define C_028D10_FORCE_HIS_ENABLE1 0xFFFFFFCF +#define S_028D10_FORCE_SHADER_Z_ORDER(x) (((x) & 0x1) << 6) +#define G_028D10_FORCE_SHADER_Z_ORDER(x) (((x) >> 6) & 0x1) +#define C_028D10_FORCE_SHADER_Z_ORDER 0xFFFFFFBF +#define S_028D10_FAST_Z_DISABLE(x) (((x) & 0x1) << 7) +#define G_028D10_FAST_Z_DISABLE(x) (((x) >> 7) & 0x1) +#define C_028D10_FAST_Z_DISABLE 0xFFFFFF7F +#define S_028D10_FAST_STENCIL_DISABLE(x) (((x) & 0x1) << 8) +#define G_028D10_FAST_STENCIL_DISABLE(x) (((x) >> 8) & 0x1) +#define C_028D10_FAST_STENCIL_DISABLE 0xFFFFFEFF +#define S_028D10_NOOP_CULL_DISABLE(x) (((x) & 0x1) << 9) +#define G_028D10_NOOP_CULL_DISABLE(x) (((x) >> 9) & 0x1) +#define C_028D10_NOOP_CULL_DISABLE 0xFFFFFDFF +#define S_028D10_FORCE_COLOR_KILL(x) (((x) & 0x1) << 10) +#define G_028D10_FORCE_COLOR_KILL(x) (((x) >> 10) & 0x1) +#define C_028D10_FORCE_COLOR_KILL 0xFFFFFBFF +#define S_028D10_FORCE_Z_READ(x) (((x) & 0x1) << 11) +#define G_028D10_FORCE_Z_READ(x) (((x) >> 11) & 0x1) +#define C_028D10_FORCE_Z_READ 0xFFFFF7FF +#define S_028D10_FORCE_STENCIL_READ(x) (((x) & 0x1) << 12) +#define G_028D10_FORCE_STENCIL_READ(x) (((x) >> 12) & 0x1) +#define C_028D10_FORCE_STENCIL_READ 0xFFFFEFFF +#define S_028D10_FORCE_FULL_Z_RANGE(x) (((x) & 0x3) << 13) +#define G_028D10_FORCE_FULL_Z_RANGE(x) (((x) >> 13) & 0x3) +#define C_028D10_FORCE_FULL_Z_RANGE 0xFFFF9FFF +#define S_028D10_FORCE_QC_SMASK_CONFLICT(x) (((x) & 0x1) << 15) +#define G_028D10_FORCE_QC_SMASK_CONFLICT(x) (((x) >> 15) & 0x1) +#define C_028D10_FORCE_QC_SMASK_CONFLICT 0xFFFF7FFF +#define S_028D10_DISABLE_VIEWPORT_CLAMP(x) (((x) & 0x1) << 16) +#define G_028D10_DISABLE_VIEWPORT_CLAMP(x) (((x) >> 16) & 0x1) +#define C_028D10_DISABLE_VIEWPORT_CLAMP 0xFFFEFFFF +#define S_028D10_IGNORE_SC_ZRANGE(x) (((x) & 0x1) << 17) +#define G_028D10_IGNORE_SC_ZRANGE(x) (((x) >> 17) & 0x1) +#define C_028D10_IGNORE_SC_ZRANGE 0xFFFDFFFF +#define R_028A40_VGT_GS_MODE 0x028A40 +#define S_028A40_MODE(x) (((x) & 0x3) << 0) +#define G_028A40_MODE(x) (((x) >> 0) & 0x3) +#define C_028A40_MODE 0xFFFFFFFC +#define S_028A40_ES_PASSTHRU(x) (((x) & 0x1) << 2) +#define G_028A40_ES_PASSTHRU(x) (((x) >> 2) & 0x1) +#define C_028A40_ES_PASSTHRU 0xFFFFFFFB +#define S_028A40_CUT_MODE(x) (((x) & 0x3) << 3) +#define G_028A40_CUT_MODE(x) (((x) >> 3) & 0x3) +#define C_028A40_CUT_MODE 0xFFFFFFE7 +#define R_008040_WAIT_UNTIL 0x008040 +#define S_008040_WAIT_CP_DMA_IDLE(x) (((x) & 0x1) << 8) +#define G_008040_WAIT_CP_DMA_IDLE(x) (((x) >> 8) & 0x1) +#define C_008040_WAIT_CP_DMA_IDLE 0xFFFFFEFF +#define S_008040_WAIT_CMDFIFO(x) (((x) & 0x1) << 10) +#define G_008040_WAIT_CMDFIFO(x) (((x) >> 10) & 0x1) +#define C_008040_WAIT_CMDFIFO 0xFFFFFBFF +#define S_008040_WAIT_2D_IDLE(x) (((x) & 0x1) << 14) +#define G_008040_WAIT_2D_IDLE(x) (((x) >> 14) & 0x1) +#define C_008040_WAIT_2D_IDLE 0xFFFFBFFF +#define S_008040_WAIT_3D_IDLE(x) (((x) & 0x1) << 15) +#define G_008040_WAIT_3D_IDLE(x) (((x) >> 15) & 0x1) +#define C_008040_WAIT_3D_IDLE 0xFFFF7FFF +#define S_008040_WAIT_2D_IDLECLEAN(x) (((x) & 0x1) << 16) +#define G_008040_WAIT_2D_IDLECLEAN(x) (((x) >> 16) & 0x1) +#define C_008040_WAIT_2D_IDLECLEAN 0xFFFEFFFF +#define S_008040_WAIT_3D_IDLECLEAN(x) (((x) & 0x1) << 17) +#define G_008040_WAIT_3D_IDLECLEAN(x) (((x) >> 17) & 0x1) +#define C_008040_WAIT_3D_IDLECLEAN 0xFFFDFFFF +#define S_008040_WAIT_EXTERN_SIG(x) (((x) & 0x1) << 19) +#define G_008040_WAIT_EXTERN_SIG(x) (((x) >> 19) & 0x1) +#define C_008040_WAIT_EXTERN_SIG 0xFFF7FFFF +#define S_008040_CMDFIFO_ENTRIES(x) (((x) & 0x1F) << 20) +#define G_008040_CMDFIFO_ENTRIES(x) (((x) >> 20) & 0x1F) +#define C_008040_CMDFIFO_ENTRIES 0xFE0FFFFF +#define R_0286CC_SPI_PS_IN_CONTROL_0 0x0286CC +#define S_0286CC_NUM_INTERP(x) (((x) & 0x3F) << 0) +#define G_0286CC_NUM_INTERP(x) (((x) >> 0) & 0x3F) +#define C_0286CC_NUM_INTERP 0xFFFFFFC0 +#define S_0286CC_POSITION_ENA(x) (((x) & 0x1) << 8) +#define G_0286CC_POSITION_ENA(x) (((x) >> 8) & 0x1) +#define C_0286CC_POSITION_ENA 0xFFFFFEFF +#define S_0286CC_POSITION_CENTROID(x) (((x) & 0x1) << 9) +#define G_0286CC_POSITION_CENTROID(x) (((x) >> 9) & 0x1) +#define C_0286CC_POSITION_CENTROID 0xFFFFFDFF +#define S_0286CC_POSITION_ADDR(x) (((x) & 0x1F) << 10) +#define G_0286CC_POSITION_ADDR(x) (((x) >> 10) & 0x1F) +#define C_0286CC_POSITION_ADDR 0xFFFF83FF +#define S_0286CC_PARAM_GEN(x) (((x) & 0xF) << 15) +#define G_0286CC_PARAM_GEN(x) (((x) >> 15) & 0xF) +#define C_0286CC_PARAM_GEN 0xFFF87FFF +#define S_0286CC_PARAM_GEN_ADDR(x) (((x) & 0x7F) << 19) +#define G_0286CC_PARAM_GEN_ADDR(x) (((x) >> 19) & 0x7F) +#define C_0286CC_PARAM_GEN_ADDR 0xFC07FFFF +#define S_0286CC_BARYC_SAMPLE_CNTL(x) (((x) & 0x3) << 26) +#define G_0286CC_BARYC_SAMPLE_CNTL(x) (((x) >> 26) & 0x3) +#define C_0286CC_BARYC_SAMPLE_CNTL 0xF3FFFFFF +#define S_0286CC_PERSP_GRADIENT_ENA(x) (((x) & 0x1) << 28) +#define G_0286CC_PERSP_GRADIENT_ENA(x) (((x) >> 28) & 0x1) +#define C_0286CC_PERSP_GRADIENT_ENA 0xEFFFFFFF +#define S_0286CC_LINEAR_GRADIENT_ENA(x) (((x) & 0x1) << 29) +#define G_0286CC_LINEAR_GRADIENT_ENA(x) (((x) >> 29) & 0x1) +#define C_0286CC_LINEAR_GRADIENT_ENA 0xDFFFFFFF +#define S_0286CC_POSITION_SAMPLE(x) (((x) & 0x1) << 30) +#define G_0286CC_POSITION_SAMPLE(x) (((x) >> 30) & 0x1) +#define C_0286CC_POSITION_SAMPLE 0xBFFFFFFF +#define S_0286CC_BARYC_AT_SAMPLE_ENA(x) (((x) & 0x1) << 31) +#define G_0286CC_BARYC_AT_SAMPLE_ENA(x) (((x) >> 31) & 0x1) +#define C_0286CC_BARYC_AT_SAMPLE_ENA 0x7FFFFFFF +#define R_0286D0_SPI_PS_IN_CONTROL_1 0x0286D0 +#define S_0286D0_GEN_INDEX_PIX(x) (((x) & 0x1) << 0) +#define G_0286D0_GEN_INDEX_PIX(x) (((x) >> 0) & 0x1) +#define C_0286D0_GEN_INDEX_PIX 0xFFFFFFFE +#define S_0286D0_GEN_INDEX_PIX_ADDR(x) (((x) & 0x7F) << 1) +#define G_0286D0_GEN_INDEX_PIX_ADDR(x) (((x) >> 1) & 0x7F) +#define C_0286D0_GEN_INDEX_PIX_ADDR 0xFFFFFF01 +#define S_0286D0_FRONT_FACE_ENA(x) (((x) & 0x1) << 8) +#define G_0286D0_FRONT_FACE_ENA(x) (((x) >> 8) & 0x1) +#define C_0286D0_FRONT_FACE_ENA 0xFFFFFEFF +#define S_0286D0_FRONT_FACE_CHAN(x) (((x) & 0x3) << 9) +#define G_0286D0_FRONT_FACE_CHAN(x) (((x) >> 9) & 0x3) +#define C_0286D0_FRONT_FACE_CHAN 0xFFFFF9FF +#define S_0286D0_FRONT_FACE_ALL_BITS(x) (((x) & 0x1) << 11) +#define G_0286D0_FRONT_FACE_ALL_BITS(x) (((x) >> 11) & 0x1) +#define C_0286D0_FRONT_FACE_ALL_BITS 0xFFFFF7FF +#define S_0286D0_FRONT_FACE_ADDR(x) (((x) & 0x1F) << 12) +#define G_0286D0_FRONT_FACE_ADDR(x) (((x) >> 12) & 0x1F) +#define C_0286D0_FRONT_FACE_ADDR 0xFFFE0FFF +#define S_0286D0_FOG_ADDR(x) (((x) & 0x7F) << 17) +#define G_0286D0_FOG_ADDR(x) (((x) >> 17) & 0x7F) +#define C_0286D0_FOG_ADDR 0xFF01FFFF +#define S_0286D0_FIXED_PT_POSITION_ENA(x) (((x) & 0x1) << 24) +#define G_0286D0_FIXED_PT_POSITION_ENA(x) (((x) >> 24) & 0x1) +#define C_0286D0_FIXED_PT_POSITION_ENA 0xFEFFFFFF +#define S_0286D0_FIXED_PT_POSITION_ADDR(x) (((x) & 0x1F) << 25) +#define G_0286D0_FIXED_PT_POSITION_ADDR(x) (((x) >> 25) & 0x1F) +#define C_0286D0_FIXED_PT_POSITION_ADDR 0xC1FFFFFF +#define R_0286C4_SPI_VS_OUT_CONFIG 0x0286C4 +#define S_0286C4_VS_PER_COMPONENT(x) (((x) & 0x1) << 0) +#define G_0286C4_VS_PER_COMPONENT(x) (((x) >> 0) & 0x1) +#define C_0286C4_VS_PER_COMPONENT 0xFFFFFFFE +#define S_0286C4_VS_EXPORT_COUNT(x) (((x) & 0x1F) << 1) +#define G_0286C4_VS_EXPORT_COUNT(x) (((x) >> 1) & 0x1F) +#define C_0286C4_VS_EXPORT_COUNT 0xFFFFFFC1 +#define S_0286C4_VS_EXPORTS_FOG(x) (((x) & 0x1) << 8) +#define G_0286C4_VS_EXPORTS_FOG(x) (((x) >> 8) & 0x1) +#define C_0286C4_VS_EXPORTS_FOG 0xFFFFFEFF +#define S_0286C4_VS_OUT_FOG_VEC_ADDR(x) (((x) & 0x1F) << 9) +#define G_0286C4_VS_OUT_FOG_VEC_ADDR(x) (((x) >> 9) & 0x1F) +#define C_0286C4_VS_OUT_FOG_VEC_ADDR 0xFFFFC1FF +#define R_028240_PA_SC_GENERIC_SCISSOR_TL 0x028240 +#define S_028240_TL_X(x) (((x) & 0x3FFF) << 0) +#define G_028240_TL_X(x) (((x) >> 0) & 0x3FFF) +#define C_028240_TL_X 0xFFFFC000 +#define S_028240_TL_Y(x) (((x) & 0x3FFF) << 16) +#define G_028240_TL_Y(x) (((x) >> 16) & 0x3FFF) +#define C_028240_TL_Y 0xC000FFFF +#define S_028240_WINDOW_OFFSET_DISABLE(x) (((x) & 0x1) << 31) +#define G_028240_WINDOW_OFFSET_DISABLE(x) (((x) >> 31) & 0x1) +#define C_028240_WINDOW_OFFSET_DISABLE 0x7FFFFFFF +#define R_028244_PA_SC_GENERIC_SCISSOR_BR 0x028244 +#define S_028244_BR_X(x) (((x) & 0x3FFF) << 0) +#define G_028244_BR_X(x) (((x) >> 0) & 0x3FFF) +#define C_028244_BR_X 0xFFFFC000 +#define S_028244_BR_Y(x) (((x) & 0x3FFF) << 16) +#define G_028244_BR_Y(x) (((x) >> 16) & 0x3FFF) +#define C_028244_BR_Y 0xC000FFFF +#define R_028030_PA_SC_SCREEN_SCISSOR_TL 0x028030 +#define S_028030_TL_X(x) (((x) & 0x7FFF) << 0) +#define G_028030_TL_X(x) (((x) >> 0) & 0x7FFF) +#define C_028030_TL_X 0xFFFF8000 +#define S_028030_TL_Y(x) (((x) & 0x7FFF) << 16) +#define G_028030_TL_Y(x) (((x) >> 16) & 0x7FFF) +#define C_028030_TL_Y 0x8000FFFF +#define R_028034_PA_SC_SCREEN_SCISSOR_BR 0x028034 +#define S_028034_BR_X(x) (((x) & 0x7FFF) << 0) +#define G_028034_BR_X(x) (((x) >> 0) & 0x7FFF) +#define C_028034_BR_X 0xFFFF8000 +#define S_028034_BR_Y(x) (((x) & 0x7FFF) << 16) +#define G_028034_BR_Y(x) (((x) >> 16) & 0x7FFF) +#define C_028034_BR_Y 0x8000FFFF +#define R_028204_PA_SC_WINDOW_SCISSOR_TL 0x028204 +#define S_028204_TL_X(x) (((x) & 0x3FFF) << 0) +#define G_028204_TL_X(x) (((x) >> 0) & 0x3FFF) +#define C_028204_TL_X 0xFFFFC000 +#define S_028204_TL_Y(x) (((x) & 0x3FFF) << 16) +#define G_028204_TL_Y(x) (((x) >> 16) & 0x3FFF) +#define C_028204_TL_Y 0xC000FFFF +#define S_028204_WINDOW_OFFSET_DISABLE(x) (((x) & 0x1) << 31) +#define G_028204_WINDOW_OFFSET_DISABLE(x) (((x) >> 31) & 0x1) +#define C_028204_WINDOW_OFFSET_DISABLE 0x7FFFFFFF +#define R_028208_PA_SC_WINDOW_SCISSOR_BR 0x028208 +#define S_028208_BR_X(x) (((x) & 0x3FFF) << 0) +#define G_028208_BR_X(x) (((x) >> 0) & 0x3FFF) +#define C_028208_BR_X 0xFFFFC000 +#define S_028208_BR_Y(x) (((x) & 0x3FFF) << 16) +#define G_028208_BR_Y(x) (((x) >> 16) & 0x3FFF) +#define C_028208_BR_Y 0xC000FFFF +#define R_0287F0_VGT_DRAW_INITIATOR 0x0287F0 +#define S_0287F0_SOURCE_SELECT(x) (((x) & 0x3) << 0) +#define G_0287F0_SOURCE_SELECT(x) (((x) >> 0) & 0x3) +#define C_0287F0_SOURCE_SELECT 0xFFFFFFFC +#define S_0287F0_MAJOR_MODE(x) (((x) & 0x3) << 2) +#define G_0287F0_MAJOR_MODE(x) (((x) >> 2) & 0x3) +#define C_0287F0_MAJOR_MODE 0xFFFFFFF3 +#define S_0287F0_SPRITE_EN(x) (((x) & 0x1) << 4) +#define G_0287F0_SPRITE_EN(x) (((x) >> 4) & 0x1) +#define C_0287F0_SPRITE_EN 0xFFFFFFEF +#define S_0287F0_NOT_EOP(x) (((x) & 0x1) << 5) +#define G_0287F0_NOT_EOP(x) (((x) >> 5) & 0x1) +#define C_0287F0_NOT_EOP 0xFFFFFFDF +#define S_0287F0_USE_OPAQUE(x) (((x) & 0x1) << 6) +#define G_0287F0_USE_OPAQUE(x) (((x) >> 6) & 0x1) +#define C_0287F0_USE_OPAQUE 0xFFFFFFBF +#define R_038008_SQ_VTX_CONSTANT_WORD2_0 0x038008 +#define S_038008_BASE_ADDRESS_HI(x) (((x) & 0xFF) << 0) +#define G_038008_BASE_ADDRESS_HI(x) (((x) >> 0) & 0xFF) +#define C_038008_BASE_ADDRESS_HI 0xFFFFFF00 +#define S_038008_STRIDE(x) (((x) & 0x7FF) << 8) +#define G_038008_STRIDE(x) (((x) >> 8) & 0x7FF) +#define C_038008_STRIDE 0xFFF800FF +#define S_038008_CLAMP_X(x) (((x) & 0x1) << 19) +#define G_038008_CLAMP_X(x) (((x) >> 19) & 0x1) +#define C_038008_CLAMP_X 0xFFF7FFFF +#define S_038008_DATA_FORMAT(x) (((x) & 0x3F) << 20) +#define G_038008_DATA_FORMAT(x) (((x) >> 20) & 0x3F) +#define C_038008_DATA_FORMAT 0xFC0FFFFF +#define V_038008_COLOR_INVALID 0x00000000 +#define V_038008_COLOR_8 0x00000001 +#define V_038008_COLOR_4_4 0x00000002 +#define V_038008_COLOR_3_3_2 0x00000003 +#define V_038008_COLOR_16 0x00000005 +#define V_038008_COLOR_16_FLOAT 0x00000006 +#define V_038008_COLOR_8_8 0x00000007 +#define V_038008_COLOR_5_6_5 0x00000008 +#define V_038008_COLOR_6_5_5 0x00000009 +#define V_038008_COLOR_1_5_5_5 0x0000000A +#define V_038008_COLOR_4_4_4_4 0x0000000B +#define V_038008_COLOR_5_5_5_1 0x0000000C +#define V_038008_COLOR_32 0x0000000D +#define V_038008_COLOR_32_FLOAT 0x0000000E +#define V_038008_COLOR_16_16 0x0000000F +#define V_038008_COLOR_16_16_FLOAT 0x00000010 +#define V_038008_COLOR_8_24 0x00000011 +#define V_038008_COLOR_8_24_FLOAT 0x00000012 +#define V_038008_COLOR_24_8 0x00000013 +#define V_038008_COLOR_24_8_FLOAT 0x00000014 +#define V_038008_COLOR_10_11_11 0x00000015 +#define V_038008_COLOR_10_11_11_FLOAT 0x00000016 +#define V_038008_COLOR_11_11_10 0x00000017 +#define V_038008_COLOR_11_11_10_FLOAT 0x00000018 +#define V_038008_COLOR_2_10_10_10 0x00000019 +#define V_038008_COLOR_8_8_8_8 0x0000001A +#define V_038008_COLOR_10_10_10_2 0x0000001B +#define V_038008_COLOR_X24_8_32_FLOAT 0x0000001C +#define V_038008_COLOR_32_32 0x0000001D +#define V_038008_COLOR_32_32_FLOAT 0x0000001E +#define V_038008_COLOR_16_16_16_16 0x0000001F +#define V_038008_COLOR_16_16_16_16_FLOAT 0x00000020 +#define V_038008_COLOR_32_32_32_32 0x00000022 +#define V_038008_COLOR_32_32_32_32_FLOAT 0x00000023 +#define S_038008_NUM_FORMAT_ALL(x) (((x) & 0x3) << 26) +#define G_038008_NUM_FORMAT_ALL(x) (((x) >> 26) & 0x3) +#define C_038008_NUM_FORMAT_ALL 0xF3FFFFFF +#define S_038008_FORMAT_COMP_ALL(x) (((x) & 0x1) << 28) +#define G_038008_FORMAT_COMP_ALL(x) (((x) >> 28) & 0x1) +#define C_038008_FORMAT_COMP_ALL 0xEFFFFFFF +#define S_038008_SRF_MODE_ALL(x) (((x) & 0x1) << 29) +#define G_038008_SRF_MODE_ALL(x) (((x) >> 29) & 0x1) +#define C_038008_SRF_MODE_ALL 0xDFFFFFFF +#define S_038008_ENDIAN_SWAP(x) (((x) & 0x3) << 30) +#define G_038008_ENDIAN_SWAP(x) (((x) >> 30) & 0x3) +#define C_038008_ENDIAN_SWAP 0x3FFFFFFF +#define R_008958_VGT_PRIMITIVE_TYPE 0x008958 +#define S_008958_PRIM_TYPE(x) (((x) & 0x3F) << 0) +#define G_008958_PRIM_TYPE(x) (((x) >> 0) & 0x3F) +#define C_008958_PRIM_TYPE 0xFFFFFFC0 +#define V_008958_DI_PT_NONE 0x00000000 +#define V_008958_DI_PT_POINTLIST 0x00000001 +#define V_008958_DI_PT_LINELIST 0x00000002 +#define V_008958_DI_PT_LINESTRIP 0x00000003 +#define V_008958_DI_PT_TRILIST 0x00000004 +#define V_008958_DI_PT_TRIFAN 0x00000005 +#define V_008958_DI_PT_TRISTRIP 0x00000006 +#define V_008958_DI_PT_UNUSED_0 0x00000007 +#define V_008958_DI_PT_UNUSED_1 0x00000008 +#define V_008958_DI_PT_UNUSED_2 0x00000009 +#define V_008958_DI_PT_LINELIST_ADJ 0x0000000A +#define V_008958_DI_PT_LINESTRIP_ADJ 0x0000000B +#define V_008958_DI_PT_TRILIST_ADJ 0x0000000C +#define V_008958_DI_PT_TRISTRIP_ADJ 0x0000000D +#define V_008958_DI_PT_UNUSED_3 0x0000000E +#define V_008958_DI_PT_UNUSED_4 0x0000000F +#define V_008958_DI_PT_TRI_WITH_WFLAGS 0x00000010 +#define V_008958_DI_PT_RECTLIST 0x00000011 +#define V_008958_DI_PT_LINELOOP 0x00000012 +#define V_008958_DI_PT_QUADLIST 0x00000013 +#define V_008958_DI_PT_QUADSTRIP 0x00000014 +#define V_008958_DI_PT_POLYGON 0x00000015 +#define V_008958_DI_PT_2D_COPY_RECT_LIST_V0 0x00000016 +#define V_008958_DI_PT_2D_COPY_RECT_LIST_V1 0x00000017 +#define V_008958_DI_PT_2D_COPY_RECT_LIST_V2 0x00000018 +#define V_008958_DI_PT_2D_COPY_RECT_LIST_V3 0x00000019 +#define V_008958_DI_PT_2D_FILL_RECT_LIST 0x0000001A +#define V_008958_DI_PT_2D_LINE_STRIP 0x0000001B +#define V_008958_DI_PT_2D_TRI_STRIP 0x0000001C +#define R_028868_SQ_PGM_RESOURCES_VS 0x028868 +#define S_028868_NUM_GPRS(x) (((x) & 0xFF) << 0) +#define G_028868_NUM_GPRS(x) (((x) >> 0) & 0xFF) +#define C_028868_NUM_GPRS 0xFFFFFF00 +#define S_028868_STACK_SIZE(x) (((x) & 0xFF) << 8) +#define G_028868_STACK_SIZE(x) (((x) >> 8) & 0xFF) +#define C_028868_STACK_SIZE 0xFFFF00FF +#define S_028868_DX10_CLAMP(x) (((x) & 0x1) << 21) +#define G_028868_DX10_CLAMP(x) (((x) >> 21) & 0x1) +#define C_028868_DX10_CLAMP 0xFFDFFFFF +#define S_028868_FETCH_CACHE_LINES(x) (((x) & 0x7) << 24) +#define G_028868_FETCH_CACHE_LINES(x) (((x) >> 24) & 0x7) +#define C_028868_FETCH_CACHE_LINES 0xF8FFFFFF +#define S_028868_UNCACHED_FIRST_INST(x) (((x) & 0x1) << 28) +#define G_028868_UNCACHED_FIRST_INST(x) (((x) >> 28) & 0x1) +#define C_028868_UNCACHED_FIRST_INST 0xEFFFFFFF +#define R_028850_SQ_PGM_RESOURCES_PS 0x028850 +#define S_028850_NUM_GPRS(x) (((x) & 0xFF) << 0) +#define G_028850_NUM_GPRS(x) (((x) >> 0) & 0xFF) +#define C_028850_NUM_GPRS 0xFFFFFF00 +#define S_028850_STACK_SIZE(x) (((x) & 0xFF) << 8) +#define G_028850_STACK_SIZE(x) (((x) >> 8) & 0xFF) +#define C_028850_STACK_SIZE 0xFFFF00FF +#define S_028850_DX10_CLAMP(x) (((x) & 0x1) << 21) +#define G_028850_DX10_CLAMP(x) (((x) >> 21) & 0x1) +#define C_028850_DX10_CLAMP 0xFFDFFFFF +#define S_028850_FETCH_CACHE_LINES(x) (((x) & 0x7) << 24) +#define G_028850_FETCH_CACHE_LINES(x) (((x) >> 24) & 0x7) +#define C_028850_FETCH_CACHE_LINES 0xF8FFFFFF +#define S_028850_UNCACHED_FIRST_INST(x) (((x) & 0x1) << 28) +#define G_028850_UNCACHED_FIRST_INST(x) (((x) >> 28) & 0x1) +#define C_028850_UNCACHED_FIRST_INST 0xEFFFFFFF +#define S_028850_CLAMP_CONSTS(x) (((x) & 0x1) << 31) +#define G_028850_CLAMP_CONSTS(x) (((x) >> 31) & 0x1) +#define C_028850_CLAMP_CONSTS 0x7FFFFFFF +#define R_028644_SPI_PS_INPUT_CNTL_0 0x028644 +#define S_028644_SEMANTIC(x) (((x) & 0xFF) << 0) +#define G_028644_SEMANTIC(x) (((x) >> 0) & 0xFF) +#define C_028644_SEMANTIC 0xFFFFFF00 +#define S_028644_DEFAULT_VAL(x) (((x) & 0x3) << 8) +#define G_028644_DEFAULT_VAL(x) (((x) >> 8) & 0x3) +#define C_028644_DEFAULT_VAL 0xFFFFFCFF +#define S_028644_FLAT_SHADE(x) (((x) & 0x1) << 10) +#define G_028644_FLAT_SHADE(x) (((x) >> 10) & 0x1) +#define C_028644_FLAT_SHADE 0xFFFFFBFF +#define S_028644_SEL_CENTROID(x) (((x) & 0x1) << 11) +#define G_028644_SEL_CENTROID(x) (((x) >> 11) & 0x1) +#define C_028644_SEL_CENTROID 0xFFFFF7FF +#define S_028644_SEL_LINEAR(x) (((x) & 0x1) << 12) +#define G_028644_SEL_LINEAR(x) (((x) >> 12) & 0x1) +#define C_028644_SEL_LINEAR 0xFFFFEFFF +#define S_028644_CYL_WRAP(x) (((x) & 0xF) << 13) +#define G_028644_CYL_WRAP(x) (((x) >> 13) & 0xF) +#define C_028644_CYL_WRAP 0xFFFE1FFF +#define S_028644_PT_SPRITE_TEX(x) (((x) & 0x1) << 17) +#define G_028644_PT_SPRITE_TEX(x) (((x) >> 17) & 0x1) +#define C_028644_PT_SPRITE_TEX 0xFFFDFFFF +#define S_028644_SEL_SAMPLE(x) (((x) & 0x1) << 18) +#define G_028644_SEL_SAMPLE(x) (((x) >> 18) & 0x1) +#define C_028644_SEL_SAMPLE 0xFFFBFFFF +#define R_0286D4_SPI_INTERP_CONTROL_0 0x0286D4 +#define S_0286D4_FLAT_SHADE_ENA(x) (((x) & 0x1) << 0) +#define G_0286D4_FLAT_SHADE_ENA(x) (((x) >> 0) & 0x1) +#define C_0286D4_FLAT_SHADE_ENA 0xFFFFFFFE +#define S_0286D4_PNT_SPRITE_ENA(x) (((x) & 0x1) << 1) +#define G_0286D4_PNT_SPRITE_ENA(x) (((x) >> 1) & 0x1) +#define C_0286D4_PNT_SPRITE_ENA 0xFFFFFFFD +#define S_0286D4_PNT_SPRITE_OVRD_X(x) (((x) & 0x7) << 2) +#define G_0286D4_PNT_SPRITE_OVRD_X(x) (((x) >> 2) & 0x7) +#define C_0286D4_PNT_SPRITE_OVRD_X 0xFFFFFFE3 +#define S_0286D4_PNT_SPRITE_OVRD_Y(x) (((x) & 0x7) << 5) +#define G_0286D4_PNT_SPRITE_OVRD_Y(x) (((x) >> 5) & 0x7) +#define C_0286D4_PNT_SPRITE_OVRD_Y 0xFFFFFF1F +#define S_0286D4_PNT_SPRITE_OVRD_Z(x) (((x) & 0x7) << 8) +#define G_0286D4_PNT_SPRITE_OVRD_Z(x) (((x) >> 8) & 0x7) +#define C_0286D4_PNT_SPRITE_OVRD_Z 0xFFFFF8FF +#define S_0286D4_PNT_SPRITE_OVRD_W(x) (((x) & 0x7) << 11) +#define G_0286D4_PNT_SPRITE_OVRD_W(x) (((x) >> 11) & 0x7) +#define C_0286D4_PNT_SPRITE_OVRD_W 0xFFFFC7FF +#define S_0286D4_PNT_SPRITE_TOP_1(x) (((x) & 0x1) << 14) +#define G_0286D4_PNT_SPRITE_TOP_1(x) (((x) >> 14) & 0x1) +#define C_0286D4_PNT_SPRITE_TOP_1 0xFFFFBFFF + +#endif diff --git a/src/gallium/drivers/r600/r700_sq.h b/src/gallium/drivers/r600/r700_sq.h new file mode 100644 index 00000000000..8266af6d1fc --- /dev/null +++ b/src/gallium/drivers/r600/r700_sq.h @@ -0,0 +1,609 @@ +/* + * Copyright 2010 Jerome Glisse <[email protected]> + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Jerome Glisse + */ +#ifndef R700_SQ_H +#define R700_SQ_H + +#define P_SQ_CF_WORD0 +#define S_SQ_CF_WORD0_ADDR(x) (((x) & 0xFFFFFFFF) << 0) +#define G_SQ_CF_WORD0_ADDR(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_SQ_CF_WORD0_ADDR 0x00000000 +#define P_SQ_CF_WORD1 +#define S_SQ_CF_WORD1_POP_COUNT(x) (((x) & 0x7) << 0) +#define G_SQ_CF_WORD1_POP_COUNT(x) (((x) >> 0) & 0x7) +#define C_SQ_CF_WORD1_POP_COUNT 0xFFFFFFF8 +#define S_SQ_CF_WORD1_CF_CONST(x) (((x) & 0x1F) << 3) +#define G_SQ_CF_WORD1_CF_CONST(x) (((x) >> 3) & 0x1F) +#define C_SQ_CF_WORD1_CF_CONST 0xFFFFFF07 +#define S_SQ_CF_WORD1_COND(x) (((x) & 0x3) << 8) +#define G_SQ_CF_WORD1_COND(x) (((x) >> 8) & 0x3) +#define C_SQ_CF_WORD1_COND 0xFFFFFCFF +#define S_SQ_CF_WORD1_COUNT(x) (((x) & 0x7) << 10) +#define G_SQ_CF_WORD1_COUNT(x) (((x) >> 10) & 0x7) +#define C_SQ_CF_WORD1_COUNT 0xFFFFE3FF +#define S_SQ_CF_WORD1_CALL_COUNT(x) (((x) & 0x3F) << 13) +#define G_SQ_CF_WORD1_CALL_COUNT(x) (((x) >> 13) & 0x3F) +#define C_SQ_CF_WORD1_CALL_COUNT 0xFFF81FFF +#define S_SQ_CF_WORD1_END_OF_PROGRAM(x) (((x) & 0x1) << 21) +#define G_SQ_CF_WORD1_END_OF_PROGRAM(x) (((x) >> 21) & 0x1) +#define C_SQ_CF_WORD1_END_OF_PROGRAM 0xFFDFFFFF +#define S_SQ_CF_WORD1_VALID_PIXEL_MODE(x) (((x) & 0x1) << 22) +#define G_SQ_CF_WORD1_VALID_PIXEL_MODE(x) (((x) >> 22) & 0x1) +#define C_SQ_CF_WORD1_VALID_PIXEL_MODE 0xFFBFFFFF +#define S_SQ_CF_WORD1_CF_INST(x) (((x) & 0x7F) << 23) +#define G_SQ_CF_WORD1_CF_INST(x) (((x) >> 23) & 0x7F) +#define C_SQ_CF_WORD1_CF_INST 0xC07FFFFF +#define V_SQ_CF_WORD1_SQ_CF_INST_NOP 0x00000000 +#define V_SQ_CF_WORD1_SQ_CF_INST_TEX 0x00000001 +#define V_SQ_CF_WORD1_SQ_CF_INST_VTX 0x00000002 +#define V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC 0x00000003 +#define V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START 0x00000004 +#define V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END 0x00000005 +#define V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_DX10 0x00000006 +#define V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL 0x00000007 +#define V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE 0x00000008 +#define V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK 0x00000009 +#define V_SQ_CF_WORD1_SQ_CF_INST_JUMP 0x0000000A +#define V_SQ_CF_WORD1_SQ_CF_INST_PUSH 0x0000000B +#define V_SQ_CF_WORD1_SQ_CF_INST_PUSH_ELSE 0x0000000C +#define V_SQ_CF_WORD1_SQ_CF_INST_ELSE 0x0000000D +#define V_SQ_CF_WORD1_SQ_CF_INST_POP 0x0000000E +#define V_SQ_CF_WORD1_SQ_CF_INST_POP_JUMP 0x0000000F +#define V_SQ_CF_WORD1_SQ_CF_INST_POP_PUSH 0x00000010 +#define V_SQ_CF_WORD1_SQ_CF_INST_POP_PUSH_ELSE 0x00000011 +#define V_SQ_CF_WORD1_SQ_CF_INST_CALL 0x00000012 +#define V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS 0x00000013 +#define V_SQ_CF_WORD1_SQ_CF_INST_RETURN 0x00000014 +#define V_SQ_CF_WORD1_SQ_CF_INST_EMIT_VERTEX 0x00000015 +#define V_SQ_CF_WORD1_SQ_CF_INST_EMIT_CUT_VERTEX 0x00000016 +#define V_SQ_CF_WORD1_SQ_CF_INST_CUT_VERTEX 0x00000017 +#define V_SQ_CF_WORD1_SQ_CF_INST_KILL 0x00000018 +#define S_SQ_CF_WORD1_WHOLE_QUAD_MODE(x) (((x) & 0x1) << 30) +#define G_SQ_CF_WORD1_WHOLE_QUAD_MODE(x) (((x) >> 30) & 0x1) +#define C_SQ_CF_WORD1_WHOLE_QUAD_MODE 0xBFFFFFFF +#define S_SQ_CF_WORD1_BARRIER(x) (((x) & 0x1) << 31) +#define G_SQ_CF_WORD1_BARRIER(x) (((x) >> 31) & 0x1) +#define C_SQ_CF_WORD1_BARRIER 0x7FFFFFFF +#define S_SQ_CF_WORD1_COUNT_3(x) (((x) & 0x1) << 19) +#define G_SQ_CF_WORD1_COUNT_3(x) (((x) >> 19) & 0x1) +#define C_SQ_CF_WORD1_COUNT_3 0xFFF7FFFF +#define P_SQ_CF_ALU_WORD0 +#define S_SQ_CF_ALU_WORD0_ADDR(x) (((x) & 0x3FFFFF) << 0) +#define G_SQ_CF_ALU_WORD0_ADDR(x) (((x) >> 0) & 0x3FFFFF) +#define C_SQ_CF_ALU_WORD0_ADDR 0xFFC00000 +#define S_SQ_CF_ALU_WORD0_KCACHE_BANK0(x) (((x) & 0xF) << 22) +#define G_SQ_CF_ALU_WORD0_KCACHE_BANK0(x) (((x) >> 22) & 0xF) +#define C_SQ_CF_ALU_WORD0_KCACHE_BANK0 0xFC3FFFFF +#define S_SQ_CF_ALU_WORD0_KCACHE_BANK1(x) (((x) & 0xF) << 26) +#define G_SQ_CF_ALU_WORD0_KCACHE_BANK1(x) (((x) >> 26) & 0xF) +#define C_SQ_CF_ALU_WORD0_KCACHE_BANK1 0xC3FFFFFF +#define S_SQ_CF_ALU_WORD0_KCACHE_MODE0(x) (((x) & 0x3) << 30) +#define G_SQ_CF_ALU_WORD0_KCACHE_MODE0(x) (((x) >> 30) & 0x3) +#define C_SQ_CF_ALU_WORD0_KCACHE_MODE0 0x3FFFFFFF +#define P_SQ_CF_ALU_WORD1 +#define S_SQ_CF_ALU_WORD1_KCACHE_MODE1(x) (((x) & 0x3) << 0) +#define G_SQ_CF_ALU_WORD1_KCACHE_MODE1(x) (((x) >> 0) & 0x3) +#define C_SQ_CF_ALU_WORD1_KCACHE_MODE1 0xFFFFFFFC +#define S_SQ_CF_ALU_WORD1_KCACHE_ADDR0(x) (((x) & 0xFF) << 2) +#define G_SQ_CF_ALU_WORD1_KCACHE_ADDR0(x) (((x) >> 2) & 0xFF) +#define C_SQ_CF_ALU_WORD1_KCACHE_ADDR0 0xFFFFFC03 +#define S_SQ_CF_ALU_WORD1_KCACHE_ADDR1(x) (((x) & 0xFF) << 10) +#define G_SQ_CF_ALU_WORD1_KCACHE_ADDR1(x) (((x) >> 10) & 0xFF) +#define C_SQ_CF_ALU_WORD1_KCACHE_ADDR1 0xFFFC03FF +#define S_SQ_CF_ALU_WORD1_COUNT(x) (((x) & 0x7F) << 18) +#define G_SQ_CF_ALU_WORD1_COUNT(x) (((x) >> 18) & 0x7F) +#define C_SQ_CF_ALU_WORD1_COUNT 0xFE03FFFF +#define S_SQ_CF_ALU_WORD1_USES_WATERFALL(x) (((x) & 0x1) << 25) +#define G_SQ_CF_ALU_WORD1_USES_WATERFALL(x) (((x) >> 25) & 0x1) +#define C_SQ_CF_ALU_WORD1_USES_WATERFALL 0xFDFFFFFF +#define S_SQ_CF_ALU_WORD1_CF_INST(x) (((x) & 0xF) << 26) +#define G_SQ_CF_ALU_WORD1_CF_INST(x) (((x) >> 26) & 0xF) +#define C_SQ_CF_ALU_WORD1_CF_INST 0xC3FFFFFF +#define V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU 0x00000008 +#define V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE 0x00000009 +#define V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER 0x0000000A +#define V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER 0x0000000B +#define V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_CONTINUE 0x0000000D +#define V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_BREAK 0x0000000E +#define V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_ELSE_AFTER 0x0000000F +#define S_SQ_CF_ALU_WORD1_WHOLE_QUAD_MODE(x) (((x) & 0x1) << 30) +#define G_SQ_CF_ALU_WORD1_WHOLE_QUAD_MODE(x) (((x) >> 30) & 0x1) +#define C_SQ_CF_ALU_WORD1_WHOLE_QUAD_MODE 0xBFFFFFFF +#define S_SQ_CF_ALU_WORD1_BARRIER(x) (((x) & 0x1) << 31) +#define G_SQ_CF_ALU_WORD1_BARRIER(x) (((x) >> 31) & 0x1) +#define C_SQ_CF_ALU_WORD1_BARRIER 0x7FFFFFFF +#define S_SQ_CF_ALU_WORD1_ALT_CONST(x) (((x) & 0x1) << 25) +#define G_SQ_CF_ALU_WORD1_ALT_CONST(x) (((x) >> 25) & 0x1) +#define C_SQ_CF_ALU_WORD1_ALT_CONST 0xFDFFFFFF +#define P_SQ_CF_ALLOC_EXPORT_WORD0 +#define S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(x) (((x) & 0x1FFF) << 0) +#define G_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(x) (((x) >> 0) & 0x1FFF) +#define C_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE 0xFFFFE000 +#define S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(x) (((x) & 0x3) << 13) +#define G_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(x) (((x) >> 13) & 0x3) +#define C_SQ_CF_ALLOC_EXPORT_WORD0_TYPE 0xFFFF9FFF +#define V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL 0x00000000 +#define V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS 0x00000001 +#define V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM 0x00000002 +#define V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_SX 0x00000003 +#define S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(x) (((x) & 0x7F) << 15) +#define G_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(x) (((x) >> 15) & 0x7F) +#define C_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR 0xFFC07FFF +#define S_SQ_CF_ALLOC_EXPORT_WORD0_RW_REL(x) (((x) & 0x1) << 22) +#define G_SQ_CF_ALLOC_EXPORT_WORD0_RW_REL(x) (((x) >> 22) & 0x1) +#define C_SQ_CF_ALLOC_EXPORT_WORD0_RW_REL 0xFFBFFFFF +#define S_SQ_CF_ALLOC_EXPORT_WORD0_INDEX_GPR(x) (((x) & 0x7F) << 23) +#define G_SQ_CF_ALLOC_EXPORT_WORD0_INDEX_GPR(x) (((x) >> 23) & 0x7F) +#define C_SQ_CF_ALLOC_EXPORT_WORD0_INDEX_GPR 0xC07FFFFF +#define S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(x) (((x) & 0x3) << 30) +#define G_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(x) (((x) >> 30) & 0x3) +#define C_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE 0x3FFFFFFF +#define P_SQ_CF_ALLOC_EXPORT_WORD1 +#define S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(x) (((x) & 0xF) << 17) +#define G_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(x) (((x) >> 17) & 0xF) +#define C_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT 0xFFE1FFFF +#define S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(x) (((x) & 0x1) << 21) +#define G_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(x) (((x) >> 21) & 0x1) +#define C_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM 0xFFDFFFFF +#define S_SQ_CF_ALLOC_EXPORT_WORD1_VALID_PIXEL_MODE(x) (((x) & 0x1) << 22) +#define G_SQ_CF_ALLOC_EXPORT_WORD1_VALID_PIXEL_MODE(x) (((x) >> 22) & 0x1) +#define C_SQ_CF_ALLOC_EXPORT_WORD1_VALID_PIXEL_MODE 0xFFBFFFFF +#define S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(x) (((x) & 0x7F) << 23) +#define G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(x) (((x) >> 23) & 0x7F) +#define C_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST 0xC07FFFFF +#define V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0 0x00000020 +#define V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1 0x00000021 +#define V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2 0x00000022 +#define V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3 0x00000023 +#define V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_SCRATCH 0x00000024 +#define V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_REDUCTION 0x00000025 +#define V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_RING 0x00000026 +#define V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT 0x00000027 +#define V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE 0x00000028 +#define S_SQ_CF_ALLOC_EXPORT_WORD1_WHOLE_QUAD_MODE(x) (((x) & 0x1) << 30) +#define G_SQ_CF_ALLOC_EXPORT_WORD1_WHOLE_QUAD_MODE(x) (((x) >> 30) & 0x1) +#define C_SQ_CF_ALLOC_EXPORT_WORD1_WHOLE_QUAD_MODE 0xBFFFFFFF +#define S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(x) (((x) & 0x1) << 31) +#define G_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(x) (((x) >> 31) & 0x1) +#define C_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER 0x7FFFFFFF +#define P_SQ_CF_ALLOC_EXPORT_WORD1_BUF +#define S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE(x) (((x) & 0xFFF) << 0) +#define G_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE(x) (((x) >> 0) & 0xFFF) +#define C_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE 0xFFFFF000 +#define S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(x) (((x) & 0xF) << 12) +#define G_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(x) (((x) >> 12) & 0xF) +#define C_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK 0xFFFF0FFF +#define P_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ +#define S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(x) (((x) & 0x7) << 0) +#define G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(x) (((x) >> 0) & 0x7) +#define C_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X 0xFFFFFFF8 +#define S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(x) (((x) & 0x7) << 3) +#define G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(x) (((x) >> 3) & 0x7) +#define C_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y 0xFFFFFFC7 +#define S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(x) (((x) & 0x7) << 6) +#define G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(x) (((x) >> 6) & 0x7) +#define C_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z 0xFFFFFE3F +#define S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(x) (((x) & 0x7) << 9) +#define G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(x) (((x) >> 9) & 0x7) +#define C_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W 0xFFFFF1FF +#define P_SQ_ALU_WORD0 +#define S_SQ_ALU_WORD0_SRC0_SEL(x) (((x) & 0x1FF) << 0) +#define G_SQ_ALU_WORD0_SRC0_SEL(x) (((x) >> 0) & 0x1FF) +#define C_SQ_ALU_WORD0_SRC0_SEL 0xFFFFFE00 +#define S_SQ_ALU_WORD0_SRC0_REL(x) (((x) & 0x1) << 9) +#define G_SQ_ALU_WORD0_SRC0_REL(x) (((x) >> 9) & 0x1) +#define C_SQ_ALU_WORD0_SRC0_REL 0xFFFFFDFF +#define S_SQ_ALU_WORD0_SRC0_CHAN(x) (((x) & 0x3) << 10) +#define G_SQ_ALU_WORD0_SRC0_CHAN(x) (((x) >> 10) & 0x3) +#define C_SQ_ALU_WORD0_SRC0_CHAN 0xFFFFF3FF +#define S_SQ_ALU_WORD0_SRC0_NEG(x) (((x) & 0x1) << 12) +#define G_SQ_ALU_WORD0_SRC0_NEG(x) (((x) >> 12) & 0x1) +#define C_SQ_ALU_WORD0_SRC0_NEG 0xFFFFEFFF +#define S_SQ_ALU_WORD0_SRC1_SEL(x) (((x) & 0x1FF) << 13) +#define G_SQ_ALU_WORD0_SRC1_SEL(x) (((x) >> 13) & 0x1FF) +#define C_SQ_ALU_WORD0_SRC1_SEL 0xFFC01FFF +#define S_SQ_ALU_WORD0_SRC1_REL(x) (((x) & 0x1) << 22) +#define G_SQ_ALU_WORD0_SRC1_REL(x) (((x) >> 22) & 0x1) +#define C_SQ_ALU_WORD0_SRC1_REL 0xFFBFFFFF +#define S_SQ_ALU_WORD0_SRC1_CHAN(x) (((x) & 0x3) << 23) +#define G_SQ_ALU_WORD0_SRC1_CHAN(x) (((x) >> 23) & 0x3) +#define C_SQ_ALU_WORD0_SRC1_CHAN 0xFE7FFFFF +#define S_SQ_ALU_WORD0_SRC1_NEG(x) (((x) & 0x1) << 25) +#define G_SQ_ALU_WORD0_SRC1_NEG(x) (((x) >> 25) & 0x1) +#define C_SQ_ALU_WORD0_SRC1_NEG 0xFDFFFFFF +#define S_SQ_ALU_WORD0_INDEX_MODE(x) (((x) & 0x7) << 26) +#define G_SQ_ALU_WORD0_INDEX_MODE(x) (((x) >> 26) & 0x7) +#define C_SQ_ALU_WORD0_INDEX_MODE 0xE3FFFFFF +#define S_SQ_ALU_WORD0_PRED_SEL(x) (((x) & 0x3) << 29) +#define G_SQ_ALU_WORD0_PRED_SEL(x) (((x) >> 29) & 0x3) +#define C_SQ_ALU_WORD0_PRED_SEL 0x9FFFFFFF +#define S_SQ_ALU_WORD0_LAST(x) (((x) & 0x1) << 31) +#define G_SQ_ALU_WORD0_LAST(x) (((x) >> 31) & 0x1) +#define C_SQ_ALU_WORD0_LAST 0x7FFFFFFF +#define P_SQ_ALU_WORD1 +#define S_SQ_ALU_WORD1_ENCODING(x) (((x) & 0x7) << 15) +#define G_SQ_ALU_WORD1_ENCODING(x) (((x) >> 15) & 0x7) +#define C_SQ_ALU_WORD1_ENCODING 0xFFFC7FFF +#define S_SQ_ALU_WORD1_BANK_SWIZZLE(x) (((x) & 0x7) << 18) +#define G_SQ_ALU_WORD1_BANK_SWIZZLE(x) (((x) >> 18) & 0x7) +#define C_SQ_ALU_WORD1_BANK_SWIZZLE 0xFFE3FFFF +#define S_SQ_ALU_WORD1_DST_GPR(x) (((x) & 0x7F) << 21) +#define G_SQ_ALU_WORD1_DST_GPR(x) (((x) >> 21) & 0x7F) +#define C_SQ_ALU_WORD1_DST_GPR 0xF01FFFFF +#define S_SQ_ALU_WORD1_DST_REL(x) (((x) & 0x1) << 28) +#define G_SQ_ALU_WORD1_DST_REL(x) (((x) >> 28) & 0x1) +#define C_SQ_ALU_WORD1_DST_REL 0xEFFFFFFF +#define S_SQ_ALU_WORD1_DST_CHAN(x) (((x) & 0x3) << 29) +#define G_SQ_ALU_WORD1_DST_CHAN(x) (((x) >> 29) & 0x3) +#define C_SQ_ALU_WORD1_DST_CHAN 0x9FFFFFFF +#define S_SQ_ALU_WORD1_CLAMP(x) (((x) & 0x1) << 31) +#define G_SQ_ALU_WORD1_CLAMP(x) (((x) >> 31) & 0x1) +#define C_SQ_ALU_WORD1_CLAMP 0x7FFFFFFF +#define P_SQ_ALU_WORD1_OP2 +#define S_SQ_ALU_WORD1_OP2_SRC0_ABS(x) (((x) & 0x1) << 0) +#define G_SQ_ALU_WORD1_OP2_SRC0_ABS(x) (((x) >> 0) & 0x1) +#define C_SQ_ALU_WORD1_OP2_SRC0_ABS 0xFFFFFFFE +#define S_SQ_ALU_WORD1_OP2_SRC1_ABS(x) (((x) & 0x1) << 1) +#define G_SQ_ALU_WORD1_OP2_SRC1_ABS(x) (((x) >> 1) & 0x1) +#define C_SQ_ALU_WORD1_OP2_SRC1_ABS 0xFFFFFFFD +#define S_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(x) (((x) & 0x1) << 2) +#define G_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(x) (((x) >> 2) & 0x1) +#define C_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK 0xFFFFFFFB +#define S_SQ_ALU_WORD1_OP2_UPDATE_PRED(x) (((x) & 0x1) << 3) +#define G_SQ_ALU_WORD1_OP2_UPDATE_PRED(x) (((x) >> 3) & 0x1) +#define C_SQ_ALU_WORD1_OP2_UPDATE_PRED 0xFFFFFFF7 +#define S_SQ_ALU_WORD1_OP2_WRITE_MASK(x) (((x) & 0x1) << 4) +#define G_SQ_ALU_WORD1_OP2_WRITE_MASK(x) (((x) >> 4) & 0x1) +#define C_SQ_ALU_WORD1_OP2_WRITE_MASK 0xFFFFFFEF +#define S_SQ_ALU_WORD1_OP2_OMOD(x) (((x) & 0x3) << 5) +#define G_SQ_ALU_WORD1_OP2_OMOD(x) (((x) >> 5) & 0x3) +#define C_SQ_ALU_WORD1_OP2_OMOD 0xFFFFFF9F +#define S_SQ_ALU_WORD1_OP2_ALU_INST(x) (((x) & 0x7FF) << 7) +#define G_SQ_ALU_WORD1_OP2_ALU_INST(x) (((x) >> 7) & 0x7FF) +#define C_SQ_ALU_WORD1_OP2_ALU_INST 0xFFFC007F +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD 0x00000000 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL 0x00000001 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL_IEEE 0x00000002 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX 0x00000003 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN 0x00000004 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_DX10 0x00000005 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_DX10 0x00000006 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE 0x00000008 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT 0x00000009 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE 0x0000000A +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE 0x0000000B +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE_DX10 0x0000000C +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_DX10 0x0000000D +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_DX10 0x0000000E +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE_DX10 0x0000000F +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT 0x00000010 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC 0x00000011 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CEIL 0x00000012 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RNDNE 0x00000013 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR 0x00000014 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA 0x00000015 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR 0x00000016 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT 0x00000018 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV 0x00000019 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP 0x0000001A +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_UINT 0x0000001E +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_UINT 0x0000001F +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE 0x00000020 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT 0x00000021 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE 0x00000022 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE 0x00000023 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_INV 0x00000024 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_POP 0x00000025 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_CLR 0x00000026 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_RESTORE 0x00000027 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH 0x00000028 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH 0x00000029 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH 0x0000002A +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH 0x0000002B +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE 0x0000002C +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT 0x0000002D +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE 0x0000002E +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE 0x0000002F +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_AND_INT 0x00000030 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_OR_INT 0x00000031 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT 0x00000032 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOT_INT 0x00000033 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT 0x00000034 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT 0x00000035 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_INT 0x00000036 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_INT 0x00000037 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_UINT 0x00000038 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_UINT 0x00000039 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE_INT 0x0000003A +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_INT 0x0000003B +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_INT 0x0000003C +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE_INT 0x0000003D +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_UINT 0x0000003E +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT 0x0000003F +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_UINT 0x00000040 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_UINT 0x00000041 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT 0x00000042 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_INT 0x00000043 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_INT 0x00000044 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT 0x00000045 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE_INT 0x00000046 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_INT 0x00000047 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_INT 0x00000048 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE_INT 0x00000049 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH_INT 0x0000004A +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH_INT 0x0000004B +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH_INT 0x0000004C +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH_INT 0x0000004D +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLT_PUSH_INT 0x0000004E +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLE_PUSH_INT 0x0000004F +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4 0x00000050 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE 0x00000051 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE 0x00000052 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX4 0x00000053 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_GPR_INT 0x00000060 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE 0x00000061 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED 0x00000062 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE 0x00000063 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED 0x00000064 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_FF 0x00000065 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE 0x00000066 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED 0x00000067 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_FF 0x00000068 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE 0x00000069 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SQRT_IEEE 0x0000006A +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT 0x0000006B +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT 0x0000006C +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT 0x0000006D +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN 0x0000006E +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS 0x0000006F +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT 0x00000070 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT 0x00000071 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT 0x00000072 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT 0x00000073 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_INT 0x00000074 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT 0x00000075 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT 0x00000076 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_INT 0x00000077 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_UINT 0x00000078 +#define V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT 0x00000079 +#define P_SQ_ALU_WORD1_OP3 +#define S_SQ_ALU_WORD1_OP3_SRC2_SEL(x) (((x) & 0x1FF) << 0) +#define G_SQ_ALU_WORD1_OP3_SRC2_SEL(x) (((x) >> 0) & 0x1FF) +#define C_SQ_ALU_WORD1_OP3_SRC2_SEL 0xFFFFFE00 +#define S_SQ_ALU_WORD1_OP3_SRC2_REL(x) (((x) & 0x1) << 9) +#define G_SQ_ALU_WORD1_OP3_SRC2_REL(x) (((x) >> 9) & 0x1) +#define C_SQ_ALU_WORD1_OP3_SRC2_REL 0xFFFFFDFF +#define S_SQ_ALU_WORD1_OP3_SRC2_CHAN(x) (((x) & 0x3) << 10) +#define G_SQ_ALU_WORD1_OP3_SRC2_CHAN(x) (((x) >> 10) & 0x3) +#define C_SQ_ALU_WORD1_OP3_SRC2_CHAN 0xFFFFF3FF +#define S_SQ_ALU_WORD1_OP3_SRC2_NEG(x) (((x) & 0x1) << 12) +#define G_SQ_ALU_WORD1_OP3_SRC2_NEG(x) (((x) >> 12) & 0x1) +#define C_SQ_ALU_WORD1_OP3_SRC2_NEG 0xFFFFEFFF +#define S_SQ_ALU_WORD1_OP3_ALU_INST(x) (((x) & 0x1F) << 13) +#define G_SQ_ALU_WORD1_OP3_ALU_INST(x) (((x) >> 13) & 0x1F) +#define C_SQ_ALU_WORD1_OP3_ALU_INST 0xFFFC1FFF +#define V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT 0x0000000C +#define V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT_M2 0x0000000D +#define V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT_M4 0x0000000E +#define V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT_D2 0x0000000F +#define V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD 0x00000010 +#define V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD_M2 0x00000011 +#define V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD_M4 0x00000012 +#define V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD_D2 0x00000013 +#define V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD_IEEE 0x00000014 +#define V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD_IEEE_M2 0x00000015 +#define V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD_IEEE_M4 0x00000016 +#define V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD_IEEE_D2 0x00000017 +#define V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDE 0x00000018 +#define V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT 0x00000019 +#define V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE 0x0000001A +#define V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDE_INT 0x0000001C +#define V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT_INT 0x0000001D +#define V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE_INT 0x0000001E +#define P_SQ_VTX_WORD0 +#define S_SQ_VTX_WORD0_VTX_INST(x) (((x) & 0x1F) << 0) +#define G_SQ_VTX_WORD0_VTX_INST(x) (((x) >> 0) & 0x1F) +#define C_SQ_VTX_WORD0_VTX_INST 0xFFFFFFE0 +#define S_SQ_VTX_WORD0_FETCH_TYPE(x) (((x) & 0x3) << 5) +#define G_SQ_VTX_WORD0_FETCH_TYPE(x) (((x) >> 5) & 0x3) +#define C_SQ_VTX_WORD0_FETCH_TYPE 0xFFFFFF9F +#define S_SQ_VTX_WORD0_FETCH_WHOLE_QUAD(x) (((x) & 0x1) << 7) +#define G_SQ_VTX_WORD0_FETCH_WHOLE_QUAD(x) (((x) >> 7) & 0x1) +#define C_SQ_VTX_WORD0_FETCH_WHOLE_QUAD 0xFFFFFF7F +#define S_SQ_VTX_WORD0_BUFFER_ID(x) (((x) & 0xFF) << 8) +#define G_SQ_VTX_WORD0_BUFFER_ID(x) (((x) >> 8) & 0xFF) +#define C_SQ_VTX_WORD0_BUFFER_ID 0xFFFF00FF +#define S_SQ_VTX_WORD0_SRC_GPR(x) (((x) & 0x7F) << 16) +#define G_SQ_VTX_WORD0_SRC_GPR(x) (((x) >> 16) & 0x7F) +#define C_SQ_VTX_WORD0_SRC_GPR 0xFF80FFFF +#define S_SQ_VTX_WORD0_SRC_REL(x) (((x) & 0x1) << 23) +#define G_SQ_VTX_WORD0_SRC_REL(x) (((x) >> 23) & 0x1) +#define C_SQ_VTX_WORD0_SRC_REL 0xFF7FFFFF +#define S_SQ_VTX_WORD0_SRC_SEL_X(x) (((x) & 0x3) << 24) +#define G_SQ_VTX_WORD0_SRC_SEL_X(x) (((x) >> 24) & 0x3) +#define C_SQ_VTX_WORD0_SRC_SEL_X 0xFCFFFFFF +#define S_SQ_VTX_WORD0_MEGA_FETCH_COUNT(x) (((x) & 0x3F) << 26) +#define G_SQ_VTX_WORD0_MEGA_FETCH_COUNT(x) (((x) >> 26) & 0x3F) +#define C_SQ_VTX_WORD0_MEGA_FETCH_COUNT 0x03FFFFFF +#define P_SQ_VTX_WORD1 +#define S_SQ_VTX_WORD1_DST_SEL_X(x) (((x) & 0x7) << 9) +#define G_SQ_VTX_WORD1_DST_SEL_X(x) (((x) >> 9) & 0x7) +#define C_SQ_VTX_WORD1_DST_SEL_X 0xFFFFF1FF +#define S_SQ_VTX_WORD1_DST_SEL_Y(x) (((x) & 0x7) << 12) +#define G_SQ_VTX_WORD1_DST_SEL_Y(x) (((x) >> 12) & 0x7) +#define C_SQ_VTX_WORD1_DST_SEL_Y 0xFFFF8FFF +#define S_SQ_VTX_WORD1_DST_SEL_Z(x) (((x) & 0x7) << 15) +#define G_SQ_VTX_WORD1_DST_SEL_Z(x) (((x) >> 15) & 0x7) +#define C_SQ_VTX_WORD1_DST_SEL_Z 0xFFFC7FFF +#define S_SQ_VTX_WORD1_DST_SEL_W(x) (((x) & 0x7) << 18) +#define G_SQ_VTX_WORD1_DST_SEL_W(x) (((x) >> 18) & 0x7) +#define C_SQ_VTX_WORD1_DST_SEL_W 0xFFE3FFFF +#define S_SQ_VTX_WORD1_USE_CONST_FIELDS(x) (((x) & 0x1) << 21) +#define G_SQ_VTX_WORD1_USE_CONST_FIELDS(x) (((x) >> 21) & 0x1) +#define C_SQ_VTX_WORD1_USE_CONST_FIELDS 0xFFDFFFFF +#define S_SQ_VTX_WORD1_DATA_FORMAT(x) (((x) & 0x3F) << 22) +#define G_SQ_VTX_WORD1_DATA_FORMAT(x) (((x) >> 22) & 0x3F) +#define C_SQ_VTX_WORD1_DATA_FORMAT 0xF03FFFFF +#define S_SQ_VTX_WORD1_NUM_FORMAT_ALL(x) (((x) & 0x3) << 28) +#define G_SQ_VTX_WORD1_NUM_FORMAT_ALL(x) (((x) >> 28) & 0x3) +#define C_SQ_VTX_WORD1_NUM_FORMAT_ALL 0xCFFFFFFF +#define S_SQ_VTX_WORD1_FORMAT_COMP_ALL(x) (((x) & 0x1) << 30) +#define G_SQ_VTX_WORD1_FORMAT_COMP_ALL(x) (((x) >> 30) & 0x1) +#define C_SQ_VTX_WORD1_FORMAT_COMP_ALL 0xBFFFFFFF +#define S_SQ_VTX_WORD1_SRF_MODE_ALL(x) (((x) & 0x1) << 31) +#define G_SQ_VTX_WORD1_SRF_MODE_ALL(x) (((x) >> 31) & 0x1) +#define C_SQ_VTX_WORD1_SRF_MODE_ALL 0x7FFFFFFF +#define P_SQ_VTX_WORD1_GPR +#define S_SQ_VTX_WORD1_GPR_DST_GPR(x) (((x) & 0x7F) << 0) +#define G_SQ_VTX_WORD1_GPR_DST_GPR(x) (((x) >> 0) & 0x7F) +#define C_SQ_VTX_WORD1_GPR_DST_GPR 0xFFFFFF80 +#define S_SQ_VTX_WORD1_GPR_DST_REL(x) (((x) & 0x1) << 7) +#define G_SQ_VTX_WORD1_GPR_DST_REL(x) (((x) >> 7) & 0x1) +#define C_SQ_VTX_WORD1_GPR_DST_REL 0xFFFFFF7F +#define P_SQ_VTX_WORD1_SEM +#define S_SQ_VTX_WORD1_SEM_SEMANTIC_ID(x) (((x) & 0xFF) << 0) +#define G_SQ_VTX_WORD1_SEM_SEMANTIC_ID(x) (((x) >> 0) & 0xFF) +#define C_SQ_VTX_WORD1_SEM_SEMANTIC_ID 0xFFFFFF00 +#define P_SQ_VTX_WORD2 +#define S_SQ_VTX_WORD2_OFFSET(x) (((x) & 0xFFFF) << 0) +#define G_SQ_VTX_WORD2_OFFSET(x) (((x) >> 0) & 0xFFFF) +#define C_SQ_VTX_WORD2_OFFSET 0xFFFF0000 +#define S_SQ_VTX_WORD2_ENDIAN_SWAP(x) (((x) & 0x3) << 16) +#define G_SQ_VTX_WORD2_ENDIAN_SWAP(x) (((x) >> 16) & 0x3) +#define C_SQ_VTX_WORD2_ENDIAN_SWAP 0xFFFCFFFF +#define S_SQ_VTX_WORD2_CONST_BUF_NO_STRIDE(x) (((x) & 0x1) << 18) +#define G_SQ_VTX_WORD2_CONST_BUF_NO_STRIDE(x) (((x) >> 18) & 0x1) +#define C_SQ_VTX_WORD2_CONST_BUF_NO_STRIDE 0xFFFBFFFF +#define S_SQ_VTX_WORD2_MEGA_FETCH(x) (((x) & 0x1) << 19) +#define G_SQ_VTX_WORD2_MEGA_FETCH(x) (((x) >> 19) & 0x1) +#define C_SQ_VTX_WORD2_MEGA_FETCH 0xFFF7FFFF +#define S_SQ_VTX_WORD2_ALT_CONST(x) (((x) & 0x1) << 20) +#define G_SQ_VTX_WORD2_ALT_CONST(x) (((x) >> 20) & 0x1) +#define C_SQ_VTX_WORD2_ALT_CONST 0xFFEFFFFF +#define P_SQ_TEX_WORD0 +#define S_SQ_TEX_WORD0_TEX_INST(x) (((x) & 0x1F) << 0) +#define G_SQ_TEX_WORD0_TEX_INST(x) (((x) >> 0) & 0x1F) +#define C_SQ_TEX_WORD0_TEX_INST 0xFFFFFFE0 +#define S_SQ_TEX_WORD0_BC_FRAC_MODE(x) (((x) & 0x1) << 5) +#define G_SQ_TEX_WORD0_BC_FRAC_MODE(x) (((x) >> 5) & 0x1) +#define C_SQ_TEX_WORD0_BC_FRAC_MODE 0xFFFFFFDF +#define S_SQ_TEX_WORD0_FETCH_WHOLE_QUAD(x) (((x) & 0x1) << 7) +#define G_SQ_TEX_WORD0_FETCH_WHOLE_QUAD(x) (((x) >> 7) & 0x1) +#define C_SQ_TEX_WORD0_FETCH_WHOLE_QUAD 0xFFFFFF7F +#define S_SQ_TEX_WORD0_RESOURCE_ID(x) (((x) & 0xFF) << 8) +#define G_SQ_TEX_WORD0_RESOURCE_ID(x) (((x) >> 8) & 0xFF) +#define C_SQ_TEX_WORD0_RESOURCE_ID 0xFFFF00FF +#define S_SQ_TEX_WORD0_SRC_GPR(x) (((x) & 0x7F) << 16) +#define G_SQ_TEX_WORD0_SRC_GPR(x) (((x) >> 16) & 0x7F) +#define C_SQ_TEX_WORD0_SRC_GPR 0xFF80FFFF +#define S_SQ_TEX_WORD0_SRC_REL(x) (((x) & 0x1) << 23) +#define G_SQ_TEX_WORD0_SRC_REL(x) (((x) >> 23) & 0x1) +#define C_SQ_TEX_WORD0_SRC_REL 0xFF7FFFFF +#define S_SQ_TEX_WORD0_ALT_CONST(x) (((x) & 0x1) << 24) +#define G_SQ_TEX_WORD0_ALT_CONST(x) (((x) >> 24) & 0x1) +#define C_SQ_TEX_WORD0_ALT_CONST 0xFEFFFFFF +#define P_SQ_TEX_WORD1 +#define S_SQ_TEX_WORD1_DST_GPR(x) (((x) & 0x7F) << 0) +#define G_SQ_TEX_WORD1_DST_GPR(x) (((x) >> 0) & 0x7F) +#define C_SQ_TEX_WORD1_DST_GPR 0xFFFFFF80 +#define S_SQ_TEX_WORD1_DST_REL(x) (((x) & 0x1) << 7) +#define G_SQ_TEX_WORD1_DST_REL(x) (((x) >> 7) & 0x1) +#define C_SQ_TEX_WORD1_DST_REL 0xFFFFFF7F +#define S_SQ_TEX_WORD1_DST_SEL_X(x) (((x) & 0x7) << 9) +#define G_SQ_TEX_WORD1_DST_SEL_X(x) (((x) >> 9) & 0x7) +#define C_SQ_TEX_WORD1_DST_SEL_X 0xFFFFF1FF +#define S_SQ_TEX_WORD1_DST_SEL_Y(x) (((x) & 0x7) << 12) +#define G_SQ_TEX_WORD1_DST_SEL_Y(x) (((x) >> 12) & 0x7) +#define C_SQ_TEX_WORD1_DST_SEL_Y 0xFFFF8FFF +#define S_SQ_TEX_WORD1_DST_SEL_Z(x) (((x) & 0x7) << 15) +#define G_SQ_TEX_WORD1_DST_SEL_Z(x) (((x) >> 15) & 0x7) +#define C_SQ_TEX_WORD1_DST_SEL_Z 0xFFFC7FFF +#define S_SQ_TEX_WORD1_DST_SEL_W(x) (((x) & 0x7) << 18) +#define G_SQ_TEX_WORD1_DST_SEL_W(x) (((x) >> 18) & 0x7) +#define C_SQ_TEX_WORD1_DST_SEL_W 0xFFE3FFFF +#define S_SQ_TEX_WORD1_LOD_BIAS(x) (((x) & 0x7F) << 21) +#define G_SQ_TEX_WORD1_LOD_BIAS(x) (((x) >> 21) & 0x7F) +#define C_SQ_TEX_WORD1_LOD_BIAS 0xF01FFFFF +#define S_SQ_TEX_WORD1_COORD_TYPE_X(x) (((x) & 0x1) << 28) +#define G_SQ_TEX_WORD1_COORD_TYPE_X(x) (((x) >> 28) & 0x1) +#define C_SQ_TEX_WORD1_COORD_TYPE_X 0xEFFFFFFF +#define S_SQ_TEX_WORD1_COORD_TYPE_Y(x) (((x) & 0x1) << 29) +#define G_SQ_TEX_WORD1_COORD_TYPE_Y(x) (((x) >> 29) & 0x1) +#define C_SQ_TEX_WORD1_COORD_TYPE_Y 0xDFFFFFFF +#define S_SQ_TEX_WORD1_COORD_TYPE_Z(x) (((x) & 0x1) << 30) +#define G_SQ_TEX_WORD1_COORD_TYPE_Z(x) (((x) >> 30) & 0x1) +#define C_SQ_TEX_WORD1_COORD_TYPE_Z 0xBFFFFFFF +#define S_SQ_TEX_WORD1_COORD_TYPE_W(x) (((x) & 0x1) << 31) +#define G_SQ_TEX_WORD1_COORD_TYPE_W(x) (((x) >> 31) & 0x1) +#define C_SQ_TEX_WORD1_COORD_TYPE_W 0x7FFFFFFF +#define P_SQ_TEX_WORD2 +#define S_SQ_TEX_WORD2_OFFSET_X(x) (((x) & 0x1F) << 0) +#define G_SQ_TEX_WORD2_OFFSET_X(x) (((x) >> 0) & 0x1F) +#define C_SQ_TEX_WORD2_OFFSET_X 0xFFFFFFE0 +#define S_SQ_TEX_WORD2_OFFSET_Y(x) (((x) & 0x1F) << 5) +#define G_SQ_TEX_WORD2_OFFSET_Y(x) (((x) >> 5) & 0x1F) +#define C_SQ_TEX_WORD2_OFFSET_Y 0xFFFFFC1F +#define S_SQ_TEX_WORD2_OFFSET_Z(x) (((x) & 0x1F) << 10) +#define G_SQ_TEX_WORD2_OFFSET_Z(x) (((x) >> 10) & 0x1F) +#define C_SQ_TEX_WORD2_OFFSET_Z 0xFFFF83FF +#define S_SQ_TEX_WORD2_SAMPLER_ID(x) (((x) & 0x1F) << 15) +#define G_SQ_TEX_WORD2_SAMPLER_ID(x) (((x) >> 15) & 0x1F) +#define C_SQ_TEX_WORD2_SAMPLER_ID 0xFFF07FFF +#define S_SQ_TEX_WORD2_SRC_SEL_X(x) (((x) & 0x7) << 20) +#define G_SQ_TEX_WORD2_SRC_SEL_X(x) (((x) >> 20) & 0x7) +#define C_SQ_TEX_WORD2_SRC_SEL_X 0xFF8FFFFF +#define S_SQ_TEX_WORD2_SRC_SEL_Y(x) (((x) & 0x7) << 23) +#define G_SQ_TEX_WORD2_SRC_SEL_Y(x) (((x) >> 23) & 0x7) +#define C_SQ_TEX_WORD2_SRC_SEL_Y 0xFC7FFFFF +#define S_SQ_TEX_WORD2_SRC_SEL_Z(x) (((x) & 0x7) << 26) +#define G_SQ_TEX_WORD2_SRC_SEL_Z(x) (((x) >> 26) & 0x7) +#define C_SQ_TEX_WORD2_SRC_SEL_Z 0xE3FFFFFF +#define S_SQ_TEX_WORD2_SRC_SEL_W(x) (((x) & 0x7) << 29) +#define G_SQ_TEX_WORD2_SRC_SEL_W(x) (((x) >> 29) & 0x7) +#define C_SQ_TEX_WORD2_SRC_SEL_W 0x1FFFFFFF +#define P_SQ_ALU_WORD1_OP2_V2 +#define S_SQ_ALU_WORD1_OP2_V2_SRC0_ABS(x) (((x) & 0x1) << 0) +#define G_SQ_ALU_WORD1_OP2_V2_SRC0_ABS(x) (((x) >> 0) & 0x1) +#define C_SQ_ALU_WORD1_OP2_V2_SRC0_ABS 0xFFFFFFFE +#define S_SQ_ALU_WORD1_OP2_V2_SRC1_ABS(x) (((x) & 0x1) << 1) +#define G_SQ_ALU_WORD1_OP2_V2_SRC1_ABS(x) (((x) >> 1) & 0x1) +#define C_SQ_ALU_WORD1_OP2_V2_SRC1_ABS 0xFFFFFFFD +#define S_SQ_ALU_WORD1_OP2_V2_UPDATE_EXECUTE_MASK(x) (((x) & 0x1) << 2) +#define G_SQ_ALU_WORD1_OP2_V2_UPDATE_EXECUTE_MASK(x) (((x) >> 2) & 0x1) +#define C_SQ_ALU_WORD1_OP2_V2_UPDATE_EXECUTE_MASK 0xFFFFFFFB +#define S_SQ_ALU_WORD1_OP2_V2_UPDATE_PRED(x) (((x) & 0x1) << 3) +#define G_SQ_ALU_WORD1_OP2_V2_UPDATE_PRED(x) (((x) >> 3) & 0x1) +#define C_SQ_ALU_WORD1_OP2_V2_UPDATE_PRED 0xFFFFFFF7 +#define S_SQ_ALU_WORD1_OP2_V2_WRITE_MASK(x) (((x) & 0x1) << 4) +#define G_SQ_ALU_WORD1_OP2_V2_WRITE_MASK(x) (((x) >> 4) & 0x1) +#define C_SQ_ALU_WORD1_OP2_V2_WRITE_MASK 0xFFFFFFEF +#define S_SQ_ALU_WORD1_OP2_V2_OMOD(x) (((x) & 0x3) << 5) +#define G_SQ_ALU_WORD1_OP2_V2_OMOD(x) (((x) >> 5) & 0x3) +#define C_SQ_ALU_WORD1_OP2_V2_OMOD 0xFFFFFF9F +#define S_SQ_ALU_WORD1_OP2_V2_ALU_INST(x) (((x) & 0x7FF) << 7) +#define G_SQ_ALU_WORD1_OP2_V2_ALU_INST(x) (((x) >> 7) & 0x7FF) +#define C_SQ_ALU_WORD1_OP2_V2_ALU_INST 0xFFFC007F + +#endif diff --git a/src/gallium/drivers/r600/radeon.h b/src/gallium/drivers/r600/radeon.h new file mode 100644 index 00000000000..ec94b112d69 --- /dev/null +++ b/src/gallium/drivers/r600/radeon.h @@ -0,0 +1,602 @@ +/* + * Copyright © 2009 Jerome Glisse <[email protected]> + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License + * as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software Foundation, + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. + */ +#ifndef RADEON_H +#define RADEON_H + +#define RADEON_CTX_MAX_PM4 (64 * 1024 / 4) + +#include <stdint.h> + +typedef uint64_t u64; +typedef uint32_t u32; +typedef uint16_t u16; +typedef uint8_t u8; + +struct radeon; + +struct pipe_screen *radeon_create_screen(struct radeon *rw); + +enum radeon_family { + CHIP_UNKNOWN, + CHIP_R100, + CHIP_RV100, + CHIP_RS100, + CHIP_RV200, + CHIP_RS200, + CHIP_R200, + CHIP_RV250, + CHIP_RS300, + CHIP_RV280, + CHIP_R300, + CHIP_R350, + CHIP_RV350, + CHIP_RV380, + CHIP_R420, + CHIP_R423, + CHIP_RV410, + CHIP_RS400, + CHIP_RS480, + CHIP_RS600, + CHIP_RS690, + CHIP_RS740, + CHIP_RV515, + CHIP_R520, + CHIP_RV530, + CHIP_RV560, + CHIP_RV570, + CHIP_R580, + CHIP_R600, + CHIP_RV610, + CHIP_RV630, + CHIP_RV670, + CHIP_RV620, + CHIP_RV635, + CHIP_RS780, + CHIP_RS880, + CHIP_RV770, + CHIP_RV730, + CHIP_RV710, + CHIP_RV740, + CHIP_CEDAR, + CHIP_REDWOOD, + CHIP_JUNIPER, + CHIP_CYPRESS, + CHIP_HEMLOCK, + CHIP_LAST, +}; + +/* + * radeon object functions + */ +struct radeon_bo { + unsigned refcount; + unsigned handle; + unsigned size; + unsigned alignment; + unsigned map_count; + void *data; +}; +struct radeon_bo *radeon_bo(struct radeon *radeon, unsigned handle, + unsigned size, unsigned alignment, void *ptr); +int radeon_bo_map(struct radeon *radeon, struct radeon_bo *bo); +void radeon_bo_unmap(struct radeon *radeon, struct radeon_bo *bo); +struct radeon_bo *radeon_bo_incref(struct radeon *radeon, struct radeon_bo *bo); +struct radeon_bo *radeon_bo_decref(struct radeon *radeon, struct radeon_bo *bo); +int radeon_bo_wait(struct radeon *radeon, struct radeon_bo *bo); + +/* + * states functions + */ +struct radeon_state { + struct radeon *radeon; + unsigned refcount; + unsigned type; + unsigned id; + unsigned nstates; + u32 *states; + unsigned npm4; + unsigned cpm4; + u32 pm4_crc; + u32 *pm4; + u32 nimmd; + u32 *immd; + unsigned nbo; + struct radeon_bo *bo[4]; + unsigned nreloc; + unsigned reloc_pm4_id[8]; + unsigned reloc_bo_id[8]; + u32 placement[8]; + unsigned bo_dirty[4]; +}; + +struct radeon_state *radeon_state(struct radeon *radeon, u32 type, u32 id); +struct radeon_state *radeon_state_incref(struct radeon_state *state); +struct radeon_state *radeon_state_decref(struct radeon_state *state); +int radeon_state_pm4(struct radeon_state *state); + +/* + * draw functions + */ +struct radeon_draw { + unsigned refcount; + struct radeon *radeon; + unsigned nstate; + struct radeon_state **state; + unsigned cpm4; +}; + +struct radeon_draw *radeon_draw(struct radeon *radeon); +struct radeon_draw *radeon_draw_duplicate(struct radeon_draw *draw); +struct radeon_draw *radeon_draw_incref(struct radeon_draw *draw); +struct radeon_draw *radeon_draw_decref(struct radeon_draw *draw); +int radeon_draw_set(struct radeon_draw *draw, struct radeon_state *state); +int radeon_draw_set_new(struct radeon_draw *draw, struct radeon_state *state); +int radeon_draw_check(struct radeon_draw *draw); + +struct radeon_ctx *radeon_ctx(struct radeon *radeon); +struct radeon_ctx *radeon_ctx_decref(struct radeon_ctx *ctx); +struct radeon_ctx *radeon_ctx_incref(struct radeon_ctx *ctx); +int radeon_ctx_set_draw(struct radeon_ctx *ctx, struct radeon_draw *draw); +int radeon_ctx_set_draw_new(struct radeon_ctx *ctx, struct radeon_draw *draw); +int radeon_ctx_pm4(struct radeon_ctx *ctx); +int radeon_ctx_submit(struct radeon_ctx *ctx); +void radeon_ctx_dump_bof(struct radeon_ctx *ctx, const char *file); + +/* + * R600/R700 + */ + +#define R600_NSTATE 1273 +#define R600_NTYPE 25 + +#define R600_CONFIG 0 +#define R600_CONFIG_TYPE 0 +#define R600_CB_CNTL 1 +#define R600_CB_CNTL_TYPE 1 +#define R600_RASTERIZER 2 +#define R600_RASTERIZER_TYPE 2 +#define R600_VIEWPORT 3 +#define R600_VIEWPORT_TYPE 3 +#define R600_SCISSOR 4 +#define R600_SCISSOR_TYPE 4 +#define R600_BLEND 5 +#define R600_BLEND_TYPE 5 +#define R600_DSA 6 +#define R600_DSA_TYPE 6 +#define R600_VS_SHADER 7 +#define R600_VS_SHADER_TYPE 7 +#define R600_PS_SHADER 8 +#define R600_PS_SHADER_TYPE 8 +#define R600_PS_CONSTANT 9 +#define R600_PS_CONSTANT_TYPE 9 +#define R600_VS_CONSTANT 265 +#define R600_VS_CONSTANT_TYPE 10 +#define R600_PS_RESOURCE 521 +#define R600_PS_RESOURCE_TYPE 11 +#define R600_VS_RESOURCE 681 +#define R600_VS_RESOURCE_TYPE 12 +#define R600_FS_RESOURCE 841 +#define R600_FS_RESOURCE_TYPE 13 +#define R600_GS_RESOURCE 1001 +#define R600_GS_RESOURCE_TYPE 14 +#define R600_PS_SAMPLER 1161 +#define R600_PS_SAMPLER_TYPE 15 +#define R600_VS_SAMPLER 1179 +#define R600_VS_SAMPLER_TYPE 16 +#define R600_GS_SAMPLER 1197 +#define R600_GS_SAMPLER_TYPE 17 +#define R600_PS_SAMPLER_BORDER 1215 +#define R600_PS_SAMPLER_BORDER_TYPE 18 +#define R600_VS_SAMPLER_BORDER 1233 +#define R600_VS_SAMPLER_BORDER_TYPE 19 +#define R600_GS_SAMPLER_BORDER 1251 +#define R600_GS_SAMPLER_BORDER_TYPE 20 +#define R600_CB0 1269 +#define R600_CB0_TYPE 21 +#define R600_DB 1270 +#define R600_DB_TYPE 22 +#define R600_VGT 1271 +#define R600_VGT_TYPE 23 +#define R600_DRAW 1272 +#define R600_DRAW_TYPE 24 +/* R600_CONFIG */ +#define R600_CONFIG__SQ_CONFIG 0 +#define R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1 1 +#define R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2 2 +#define R600_CONFIG__SQ_THREAD_RESOURCE_MGMT 3 +#define R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1 4 +#define R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2 5 +#define R600_CONFIG__SQ_DYN_GPR_CNTL_PS_FLUSH_REQ 6 +#define R600_CONFIG__TA_CNTL_AUX 7 +#define R600_CONFIG__VC_ENHANCE 8 +#define R600_CONFIG__DB_DEBUG 9 +#define R600_CONFIG__DB_WATERMARKS 10 +#define R600_CONFIG__SX_MISC 11 +#define R600_CONFIG__SPI_THREAD_GROUPING 12 +#define R600_CONFIG__CB_SHADER_CONTROL 13 +#define R600_CONFIG__SQ_ESGS_RING_ITEMSIZE 14 +#define R600_CONFIG__SQ_GSVS_RING_ITEMSIZE 15 +#define R600_CONFIG__SQ_ESTMP_RING_ITEMSIZE 16 +#define R600_CONFIG__SQ_GSTMP_RING_ITEMSIZE 17 +#define R600_CONFIG__SQ_VSTMP_RING_ITEMSIZE 18 +#define R600_CONFIG__SQ_PSTMP_RING_ITEMSIZE 19 +#define R600_CONFIG__SQ_FBUF_RING_ITEMSIZE 20 +#define R600_CONFIG__SQ_REDUC_RING_ITEMSIZE 21 +#define R600_CONFIG__SQ_GS_VERT_ITEMSIZE 22 +#define R600_CONFIG__VGT_OUTPUT_PATH_CNTL 23 +#define R600_CONFIG__VGT_HOS_CNTL 24 +#define R600_CONFIG__VGT_HOS_MAX_TESS_LEVEL 25 +#define R600_CONFIG__VGT_HOS_MIN_TESS_LEVEL 26 +#define R600_CONFIG__VGT_HOS_REUSE_DEPTH 27 +#define R600_CONFIG__VGT_GROUP_PRIM_TYPE 28 +#define R600_CONFIG__VGT_GROUP_FIRST_DECR 29 +#define R600_CONFIG__VGT_GROUP_DECR 30 +#define R600_CONFIG__VGT_GROUP_VECT_0_CNTL 31 +#define R600_CONFIG__VGT_GROUP_VECT_1_CNTL 32 +#define R600_CONFIG__VGT_GROUP_VECT_0_FMT_CNTL 33 +#define R600_CONFIG__VGT_GROUP_VECT_1_FMT_CNTL 34 +#define R600_CONFIG__VGT_GS_MODE 35 +#define R600_CONFIG__PA_SC_MODE_CNTL 36 +#define R600_CONFIG__VGT_STRMOUT_EN 37 +#define R600_CONFIG__VGT_REUSE_OFF 38 +#define R600_CONFIG__VGT_VTX_CNT_EN 39 +#define R600_CONFIG__VGT_STRMOUT_BUFFER_EN 40 +#define R600_CONFIG_SIZE 41 +#define R600_CONFIG_PM4 128 +/* R600_CB_CNTL */ +#define R600_CB_CNTL__CB_CLEAR_RED 0 +#define R600_CB_CNTL__CB_CLEAR_GREEN 1 +#define R600_CB_CNTL__CB_CLEAR_BLUE 2 +#define R600_CB_CNTL__CB_CLEAR_ALPHA 3 +#define R600_CB_CNTL__CB_SHADER_MASK 4 +#define R600_CB_CNTL__CB_TARGET_MASK 5 +#define R600_CB_CNTL__CB_FOG_RED 6 +#define R600_CB_CNTL__CB_FOG_GREEN 7 +#define R600_CB_CNTL__CB_FOG_BLUE 8 +#define R600_CB_CNTL__CB_COLOR_CONTROL 9 +#define R600_CB_CNTL__PA_SC_AA_CONFIG 10 +#define R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_MCTX 11 +#define R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX 12 +#define R600_CB_CNTL__CB_CLRCMP_CONTROL 13 +#define R600_CB_CNTL__CB_CLRCMP_SRC 14 +#define R600_CB_CNTL__CB_CLRCMP_DST 15 +#define R600_CB_CNTL__CB_CLRCMP_MSK 16 +#define R600_CB_CNTL__PA_SC_AA_MASK 17 +#define R600_CB_CNTL_SIZE 18 +#define R600_CB_CNTL_PM4 128 +/* R600_RASTERIZER */ +#define R600_RASTERIZER__SPI_INTERP_CONTROL_0 0 +#define R600_RASTERIZER__PA_CL_CLIP_CNTL 1 +#define R600_RASTERIZER__PA_SU_SC_MODE_CNTL 2 +#define R600_RASTERIZER__PA_CL_VS_OUT_CNTL 3 +#define R600_RASTERIZER__PA_CL_NANINF_CNTL 4 +#define R600_RASTERIZER__PA_SU_POINT_SIZE 5 +#define R600_RASTERIZER__PA_SU_POINT_MINMAX 6 +#define R600_RASTERIZER__PA_SU_LINE_CNTL 7 +#define R600_RASTERIZER__PA_SC_LINE_STIPPLE 8 +#define R600_RASTERIZER__PA_SC_MPASS_PS_CNTL 9 +#define R600_RASTERIZER__PA_SC_LINE_CNTL 10 +#define R600_RASTERIZER__PA_CL_GB_VERT_CLIP_ADJ 11 +#define R600_RASTERIZER__PA_CL_GB_VERT_DISC_ADJ 12 +#define R600_RASTERIZER__PA_CL_GB_HORZ_CLIP_ADJ 13 +#define R600_RASTERIZER__PA_CL_GB_HORZ_DISC_ADJ 14 +#define R600_RASTERIZER__PA_SU_POLY_OFFSET_DB_FMT_CNTL 15 +#define R600_RASTERIZER__PA_SU_POLY_OFFSET_CLAMP 16 +#define R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_SCALE 17 +#define R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_OFFSET 18 +#define R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_SCALE 19 +#define R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_OFFSET 20 +#define R600_RASTERIZER_SIZE 21 +#define R600_RASTERIZER_PM4 128 +/* R600_VIEWPORT */ +#define R600_VIEWPORT__PA_SC_VPORT_ZMIN_0 0 +#define R600_VIEWPORT__PA_SC_VPORT_ZMAX_0 1 +#define R600_VIEWPORT__PA_CL_VPORT_XSCALE_0 2 +#define R600_VIEWPORT__PA_CL_VPORT_YSCALE_0 3 +#define R600_VIEWPORT__PA_CL_VPORT_ZSCALE_0 4 +#define R600_VIEWPORT__PA_CL_VPORT_XOFFSET_0 5 +#define R600_VIEWPORT__PA_CL_VPORT_YOFFSET_0 6 +#define R600_VIEWPORT__PA_CL_VPORT_ZOFFSET_0 7 +#define R600_VIEWPORT__PA_CL_VTE_CNTL 8 +#define R600_VIEWPORT_SIZE 9 +#define R600_VIEWPORT_PM4 128 +/* R600_SCISSOR */ +#define R600_SCISSOR__PA_SC_SCREEN_SCISSOR_TL 0 +#define R600_SCISSOR__PA_SC_SCREEN_SCISSOR_BR 1 +#define R600_SCISSOR__PA_SC_WINDOW_OFFSET 2 +#define R600_SCISSOR__PA_SC_WINDOW_SCISSOR_TL 3 +#define R600_SCISSOR__PA_SC_WINDOW_SCISSOR_BR 4 +#define R600_SCISSOR__PA_SC_CLIPRECT_RULE 5 +#define R600_SCISSOR__PA_SC_CLIPRECT_0_TL 6 +#define R600_SCISSOR__PA_SC_CLIPRECT_0_BR 7 +#define R600_SCISSOR__PA_SC_CLIPRECT_1_TL 8 +#define R600_SCISSOR__PA_SC_CLIPRECT_1_BR 9 +#define R600_SCISSOR__PA_SC_CLIPRECT_2_TL 10 +#define R600_SCISSOR__PA_SC_CLIPRECT_2_BR 11 +#define R600_SCISSOR__PA_SC_CLIPRECT_3_TL 12 +#define R600_SCISSOR__PA_SC_CLIPRECT_3_BR 13 +#define R600_SCISSOR__PA_SC_EDGERULE 14 +#define R600_SCISSOR__PA_SC_GENERIC_SCISSOR_TL 15 +#define R600_SCISSOR__PA_SC_GENERIC_SCISSOR_BR 16 +#define R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL 17 +#define R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR 18 +#define R600_SCISSOR_SIZE 19 +#define R600_SCISSOR_PM4 128 +/* R600_BLEND */ +#define R600_BLEND__CB_BLEND_RED 0 +#define R600_BLEND__CB_BLEND_GREEN 1 +#define R600_BLEND__CB_BLEND_BLUE 2 +#define R600_BLEND__CB_BLEND_ALPHA 3 +#define R600_BLEND__CB_BLEND0_CONTROL 4 +#define R600_BLEND__CB_BLEND1_CONTROL 5 +#define R600_BLEND__CB_BLEND2_CONTROL 6 +#define R600_BLEND__CB_BLEND3_CONTROL 7 +#define R600_BLEND__CB_BLEND4_CONTROL 8 +#define R600_BLEND__CB_BLEND5_CONTROL 9 +#define R600_BLEND__CB_BLEND6_CONTROL 10 +#define R600_BLEND__CB_BLEND7_CONTROL 11 +#define R600_BLEND__CB_BLEND_CONTROL 12 +#define R600_BLEND_SIZE 13 +#define R600_BLEND_PM4 128 +/* R600_DSA */ +#define R600_DSA__DB_STENCIL_CLEAR 0 +#define R600_DSA__DB_DEPTH_CLEAR 1 +#define R600_DSA__SX_ALPHA_TEST_CONTROL 2 +#define R600_DSA__DB_STENCILREFMASK 3 +#define R600_DSA__DB_STENCILREFMASK_BF 4 +#define R600_DSA__SX_ALPHA_REF 5 +#define R600_DSA__SPI_FOG_FUNC_SCALE 6 +#define R600_DSA__SPI_FOG_FUNC_BIAS 7 +#define R600_DSA__SPI_FOG_CNTL 8 +#define R600_DSA__DB_DEPTH_CONTROL 9 +#define R600_DSA__DB_SHADER_CONTROL 10 +#define R600_DSA__DB_RENDER_CONTROL 11 +#define R600_DSA__DB_RENDER_OVERRIDE 12 +#define R600_DSA__DB_SRESULTS_COMPARE_STATE1 13 +#define R600_DSA__DB_PRELOAD_CONTROL 14 +#define R600_DSA__DB_ALPHA_TO_MASK 15 +#define R600_DSA_SIZE 16 +#define R600_DSA_PM4 128 +/* R600_VS_SHADER */ +#define R600_VS_SHADER__SQ_VTX_SEMANTIC_0 0 +#define R600_VS_SHADER__SQ_VTX_SEMANTIC_1 1 +#define R600_VS_SHADER__SQ_VTX_SEMANTIC_2 2 +#define R600_VS_SHADER__SQ_VTX_SEMANTIC_3 3 +#define R600_VS_SHADER__SQ_VTX_SEMANTIC_4 4 +#define R600_VS_SHADER__SQ_VTX_SEMANTIC_5 5 +#define R600_VS_SHADER__SQ_VTX_SEMANTIC_6 6 +#define R600_VS_SHADER__SQ_VTX_SEMANTIC_7 7 +#define R600_VS_SHADER__SQ_VTX_SEMANTIC_8 8 +#define R600_VS_SHADER__SQ_VTX_SEMANTIC_9 9 +#define R600_VS_SHADER__SQ_VTX_SEMANTIC_10 10 +#define R600_VS_SHADER__SQ_VTX_SEMANTIC_11 11 +#define R600_VS_SHADER__SQ_VTX_SEMANTIC_12 12 +#define R600_VS_SHADER__SQ_VTX_SEMANTIC_13 13 +#define R600_VS_SHADER__SQ_VTX_SEMANTIC_14 14 +#define R600_VS_SHADER__SQ_VTX_SEMANTIC_15 15 +#define R600_VS_SHADER__SQ_VTX_SEMANTIC_16 16 +#define R600_VS_SHADER__SQ_VTX_SEMANTIC_17 17 +#define R600_VS_SHADER__SQ_VTX_SEMANTIC_18 18 +#define R600_VS_SHADER__SQ_VTX_SEMANTIC_19 19 +#define R600_VS_SHADER__SQ_VTX_SEMANTIC_20 20 +#define R600_VS_SHADER__SQ_VTX_SEMANTIC_21 21 +#define R600_VS_SHADER__SQ_VTX_SEMANTIC_22 22 +#define R600_VS_SHADER__SQ_VTX_SEMANTIC_23 23 +#define R600_VS_SHADER__SQ_VTX_SEMANTIC_24 24 +#define R600_VS_SHADER__SQ_VTX_SEMANTIC_25 25 +#define R600_VS_SHADER__SQ_VTX_SEMANTIC_26 26 +#define R600_VS_SHADER__SQ_VTX_SEMANTIC_27 27 +#define R600_VS_SHADER__SQ_VTX_SEMANTIC_28 28 +#define R600_VS_SHADER__SQ_VTX_SEMANTIC_29 29 +#define R600_VS_SHADER__SQ_VTX_SEMANTIC_30 30 +#define R600_VS_SHADER__SQ_VTX_SEMANTIC_31 31 +#define R600_VS_SHADER__SPI_VS_OUT_ID_0 32 +#define R600_VS_SHADER__SPI_VS_OUT_ID_1 33 +#define R600_VS_SHADER__SPI_VS_OUT_ID_2 34 +#define R600_VS_SHADER__SPI_VS_OUT_ID_3 35 +#define R600_VS_SHADER__SPI_VS_OUT_ID_4 36 +#define R600_VS_SHADER__SPI_VS_OUT_ID_5 37 +#define R600_VS_SHADER__SPI_VS_OUT_ID_6 38 +#define R600_VS_SHADER__SPI_VS_OUT_ID_7 39 +#define R600_VS_SHADER__SPI_VS_OUT_ID_8 40 +#define R600_VS_SHADER__SPI_VS_OUT_ID_9 41 +#define R600_VS_SHADER__SPI_VS_OUT_CONFIG 42 +#define R600_VS_SHADER__SQ_PGM_START_VS 43 +#define R600_VS_SHADER__SQ_PGM_RESOURCES_VS 44 +#define R600_VS_SHADER__SQ_PGM_START_FS 45 +#define R600_VS_SHADER__SQ_PGM_RESOURCES_FS 46 +#define R600_VS_SHADER__SQ_PGM_CF_OFFSET_VS 47 +#define R600_VS_SHADER__SQ_PGM_CF_OFFSET_FS 48 +#define R600_VS_SHADER_SIZE 49 +#define R600_VS_SHADER_PM4 128 +/* R600_PS_SHADER */ +#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_0 0 +#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_1 1 +#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_2 2 +#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_3 3 +#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_4 4 +#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_5 5 +#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_6 6 +#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_7 7 +#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_8 8 +#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_9 9 +#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_10 10 +#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_11 11 +#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_12 12 +#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_13 13 +#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_14 14 +#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_15 15 +#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_16 16 +#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_17 17 +#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_18 18 +#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_19 19 +#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_20 20 +#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_21 21 +#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_22 22 +#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_23 23 +#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_24 24 +#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_25 25 +#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_26 26 +#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_27 27 +#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_28 28 +#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_29 29 +#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_30 30 +#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_31 31 +#define R600_PS_SHADER__SPI_PS_IN_CONTROL_0 32 +#define R600_PS_SHADER__SPI_PS_IN_CONTROL_1 33 +#define R600_PS_SHADER__SPI_INPUT_Z 34 +#define R600_PS_SHADER__SQ_PGM_START_PS 35 +#define R600_PS_SHADER__SQ_PGM_RESOURCES_PS 36 +#define R600_PS_SHADER__SQ_PGM_EXPORTS_PS 37 +#define R600_PS_SHADER__SQ_PGM_CF_OFFSET_PS 38 +#define R600_PS_SHADER_SIZE 39 +#define R600_PS_SHADER_PM4 128 +/* R600_PS_CONSTANT */ +#define R600_PS_CONSTANT__SQ_ALU_CONSTANT0_0 0 +#define R600_PS_CONSTANT__SQ_ALU_CONSTANT1_0 1 +#define R600_PS_CONSTANT__SQ_ALU_CONSTANT2_0 2 +#define R600_PS_CONSTANT__SQ_ALU_CONSTANT3_0 3 +#define R600_PS_CONSTANT_SIZE 4 +#define R600_PS_CONSTANT_PM4 128 +/* R600_VS_CONSTANT */ +#define R600_VS_CONSTANT__SQ_ALU_CONSTANT0_256 0 +#define R600_VS_CONSTANT__SQ_ALU_CONSTANT1_256 1 +#define R600_VS_CONSTANT__SQ_ALU_CONSTANT2_256 2 +#define R600_VS_CONSTANT__SQ_ALU_CONSTANT3_256 3 +#define R600_VS_CONSTANT_SIZE 4 +#define R600_VS_CONSTANT_PM4 128 +/* R600_PS_RESOURCE */ +#define R600_PS_RESOURCE__RESOURCE0_WORD0 0 +#define R600_PS_RESOURCE__RESOURCE0_WORD1 1 +#define R600_PS_RESOURCE__RESOURCE0_WORD2 2 +#define R600_PS_RESOURCE__RESOURCE0_WORD3 3 +#define R600_PS_RESOURCE__RESOURCE0_WORD4 4 +#define R600_PS_RESOURCE__RESOURCE0_WORD5 5 +#define R600_PS_RESOURCE__RESOURCE0_WORD6 6 +#define R600_PS_RESOURCE_SIZE 7 +#define R600_PS_RESOURCE_PM4 128 +/* R600_VS_RESOURCE */ +#define R600_VS_RESOURCE__RESOURCE160_WORD0 0 +#define R600_VS_RESOURCE__RESOURCE160_WORD1 1 +#define R600_VS_RESOURCE__RESOURCE160_WORD2 2 +#define R600_VS_RESOURCE__RESOURCE160_WORD3 3 +#define R600_VS_RESOURCE__RESOURCE160_WORD4 4 +#define R600_VS_RESOURCE__RESOURCE160_WORD5 5 +#define R600_VS_RESOURCE__RESOURCE160_WORD6 6 +#define R600_VS_RESOURCE_SIZE 7 +#define R600_VS_RESOURCE_PM4 128 +/* R600_FS_RESOURCE */ +#define R600_FS_RESOURCE__RESOURCE320_WORD0 0 +#define R600_FS_RESOURCE__RESOURCE320_WORD1 1 +#define R600_FS_RESOURCE__RESOURCE320_WORD2 2 +#define R600_FS_RESOURCE__RESOURCE320_WORD3 3 +#define R600_FS_RESOURCE__RESOURCE320_WORD4 4 +#define R600_FS_RESOURCE__RESOURCE320_WORD5 5 +#define R600_FS_RESOURCE__RESOURCE320_WORD6 6 +#define R600_FS_RESOURCE_SIZE 7 +#define R600_FS_RESOURCE_PM4 128 +/* R600_GS_RESOURCE */ +#define R600_GS_RESOURCE__RESOURCE336_WORD0 0 +#define R600_GS_RESOURCE__RESOURCE336_WORD1 1 +#define R600_GS_RESOURCE__RESOURCE336_WORD2 2 +#define R600_GS_RESOURCE__RESOURCE336_WORD3 3 +#define R600_GS_RESOURCE__RESOURCE336_WORD4 4 +#define R600_GS_RESOURCE__RESOURCE336_WORD5 5 +#define R600_GS_RESOURCE__RESOURCE336_WORD6 6 +#define R600_GS_RESOURCE_SIZE 7 +#define R600_GS_RESOURCE_PM4 128 +/* R600_PS_SAMPLER */ +#define R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD0_0 0 +#define R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD1_0 1 +#define R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD2_0 2 +#define R600_PS_SAMPLER_SIZE 3 +#define R600_PS_SAMPLER_PM4 128 +/* R600_VS_SAMPLER */ +#define R600_VS_SAMPLER__SQ_TEX_SAMPLER_WORD0_18 0 +#define R600_VS_SAMPLER__SQ_TEX_SAMPLER_WORD1_18 1 +#define R600_VS_SAMPLER__SQ_TEX_SAMPLER_WORD2_18 2 +#define R600_VS_SAMPLER_SIZE 3 +#define R600_VS_SAMPLER_PM4 128 +/* R600_GS_SAMPLER */ +#define R600_GS_SAMPLER__SQ_TEX_SAMPLER_WORD0_36 0 +#define R600_GS_SAMPLER__SQ_TEX_SAMPLER_WORD1_36 1 +#define R600_GS_SAMPLER__SQ_TEX_SAMPLER_WORD2_36 2 +#define R600_GS_SAMPLER_SIZE 3 +#define R600_GS_SAMPLER_PM4 128 +/* R600_PS_SAMPLER_BORDER */ +#define R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_RED 0 +#define R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_GREEN 1 +#define R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_BLUE 2 +#define R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_ALPHA 3 +#define R600_PS_SAMPLER_BORDER_SIZE 4 +#define R600_PS_SAMPLER_BORDER_PM4 128 +/* R600_VS_SAMPLER_BORDER */ +#define R600_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_RED 0 +#define R600_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_GREEN 1 +#define R600_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_BLUE 2 +#define R600_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_ALPHA 3 +#define R600_VS_SAMPLER_BORDER_SIZE 4 +#define R600_VS_SAMPLER_BORDER_PM4 128 +/* R600_GS_SAMPLER_BORDER */ +#define R600_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_RED 0 +#define R600_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_GREEN 1 +#define R600_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_BLUE 2 +#define R600_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_ALPHA 3 +#define R600_GS_SAMPLER_BORDER_SIZE 4 +#define R600_GS_SAMPLER_BORDER_PM4 128 +/* R600_CB0 */ +#define R600_CB0__CB_COLOR0_BASE 0 +#define R600_CB0__CB_COLOR0_INFO 1 +#define R600_CB0__CB_COLOR0_SIZE 2 +#define R600_CB0__CB_COLOR0_VIEW 3 +#define R600_CB0__CB_COLOR0_FRAG 4 +#define R600_CB0__CB_COLOR0_TILE 5 +#define R600_CB0__CB_COLOR0_MASK 6 +#define R600_CB0_SIZE 7 +#define R600_CB0_PM4 128 +/* R600_DB */ +#define R600_DB__DB_DEPTH_BASE 0 +#define R600_DB__DB_DEPTH_SIZE 1 +#define R600_DB__DB_DEPTH_VIEW 2 +#define R600_DB__DB_DEPTH_INFO 3 +#define R600_DB__DB_HTILE_SURFACE 4 +#define R600_DB__DB_PREFETCH_LIMIT 5 +#define R600_DB_SIZE 6 +#define R600_DB_PM4 128 +/* R600_VGT */ +#define R600_VGT__VGT_PRIMITIVE_TYPE 0 +#define R600_VGT__VGT_MAX_VTX_INDX 1 +#define R600_VGT__VGT_MIN_VTX_INDX 2 +#define R600_VGT__VGT_INDX_OFFSET 3 +#define R600_VGT__VGT_MULTI_PRIM_IB_RESET_INDX 4 +#define R600_VGT__VGT_DMA_INDEX_TYPE 5 +#define R600_VGT__VGT_PRIMITIVEID_EN 6 +#define R600_VGT__VGT_DMA_NUM_INSTANCES 7 +#define R600_VGT__VGT_MULTI_PRIM_IB_RESET_EN 8 +#define R600_VGT__VGT_INSTANCE_STEP_RATE_0 9 +#define R600_VGT__VGT_INSTANCE_STEP_RATE_1 10 +#define R600_VGT_SIZE 11 +#define R600_VGT_PM4 128 +/* R600_DRAW */ +#define R600_DRAW__VGT_NUM_INDICES 0 +#define R600_DRAW__VGT_DMA_BASE_HI 1 +#define R600_DRAW__VGT_DMA_BASE 2 +#define R600_DRAW__VGT_DRAW_INITIATOR 3 +#define R600_DRAW_SIZE 4 +#define R600_DRAW_PM4 128 + +#endif diff --git a/src/gallium/winsys/drm/r600/Makefile b/src/gallium/winsys/drm/r600/Makefile new file mode 100644 index 00000000000..bacdf3de28a --- /dev/null +++ b/src/gallium/winsys/drm/r600/Makefile @@ -0,0 +1,12 @@ +# src/gallium/winsys/drm/radeon/Makefile +TOP = ../../../../.. +include $(TOP)/configs/current + +SUBDIRS = core $(GALLIUM_STATE_TRACKERS_DIRS) + +default install clean: + @for dir in $(SUBDIRS) ; do \ + if [ -d $$dir ] ; then \ + (cd $$dir && $(MAKE) $@) || exit 1; \ + fi \ + done diff --git a/src/gallium/winsys/drm/r600/SConscript b/src/gallium/winsys/drm/r600/SConscript new file mode 100644 index 00000000000..b2dfd504d42 --- /dev/null +++ b/src/gallium/winsys/drm/r600/SConscript @@ -0,0 +1,7 @@ +Import('*') + +SConscript(['core/SConscript',]) + +if 'mesa' in env['statetrackers']: + + SConscript(['dri/SConscript']) diff --git a/src/gallium/winsys/drm/r600/core/Makefile b/src/gallium/winsys/drm/r600/core/Makefile new file mode 100644 index 00000000000..0a8d9872148 --- /dev/null +++ b/src/gallium/winsys/drm/r600/core/Makefile @@ -0,0 +1,22 @@ +TOP = ../../../../../.. +include $(TOP)/configs/current + +LIBNAME = r600winsys + +C_SOURCES = \ + bof.c \ + r600_state.c \ + radeon_ctx.c \ + radeon_draw.c \ + radeon_state.c \ + radeon_bo.c \ + radeon_pciid.c \ + radeon.c \ + r600_drm.c + +LIBRARY_INCLUDES = -I$(TOP)/src/gallium/drivers/r600 \ + $(shell pkg-config libdrm --cflags-only-I) + +LIBRARY_DEFINES = $(shell pkg-config libdrm --cflags-only-other) + +include ../../../../Makefile.template diff --git a/src/gallium/winsys/drm/r600/core/bof.c b/src/gallium/winsys/drm/r600/core/bof.c new file mode 100644 index 00000000000..0598cc6bc0f --- /dev/null +++ b/src/gallium/winsys/drm/r600/core/bof.c @@ -0,0 +1,477 @@ +/* + * Copyright 2010 Jerome Glisse <[email protected]> + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Jerome Glisse + */ +#include <errno.h> +#include <stdlib.h> +#include <string.h> +#include "bof.h" + +/* + * helpers + */ +static int bof_entry_grow(bof_t *bof) +{ + bof_t **array; + + if (bof->array_size < bof->nentry) + return 0; + array = realloc(bof->array, (bof->nentry + 16) * sizeof(void*)); + if (array == NULL) + return -ENOMEM; + bof->array = array; + bof->nentry += 16; + return 0; +} + +/* + * object + */ +bof_t *bof_object(void) +{ + bof_t *object; + + object = calloc(1, sizeof(bof_t)); + if (object == NULL) + return NULL; + object->refcount = 1; + object->type = BOF_TYPE_OBJECT; + object->size = 12; + return object; +} + +bof_t *bof_object_get(bof_t *object, const char *keyname) +{ + unsigned i; + + for (i = 0; i < object->array_size; i += 2) { + if (!strcmp(object->array[i]->value, keyname)) { + return object->array[i + 1]; + } + } + return NULL; +} + +int bof_object_set(bof_t *object, const char *keyname, bof_t *value) +{ + bof_t *key; + int r; + + if (object->type != BOF_TYPE_OBJECT) + return -EINVAL; + r = bof_entry_grow(object); + if (r) + return r; + key = bof_string(keyname); + if (key == NULL) + return -ENOMEM; + object->array[object->array_size++] = key; + object->array[object->array_size++] = value; + object->size += value->size; + object->size += key->size; + bof_incref(value); + return 0; +} + +/* + * array + */ +bof_t *bof_array(void) +{ + bof_t *array = bof_object(); + + if (array == NULL) + return NULL; + array->type = BOF_TYPE_ARRAY; + array->size = 12; + return array; +} + +int bof_array_append(bof_t *array, bof_t *value) +{ + int r; + if (array->type != BOF_TYPE_ARRAY) + return -EINVAL; + r = bof_entry_grow(array); + if (r) + return r; + array->array[array->array_size++] = value; + array->size += value->size; + bof_incref(value); + return 0; +} + +bof_t *bof_array_get(bof_t *bof, unsigned i) +{ + if (!bof_is_array(bof) || i >= bof->array_size) + return NULL; + return bof->array[i]; +} + +unsigned bof_array_size(bof_t *bof) +{ + if (!bof_is_array(bof)) + return 0; + return bof->array_size; +} + +/* + * blob + */ +bof_t *bof_blob(unsigned size, void *value) +{ + bof_t *blob = bof_object(); + + if (blob == NULL) + return NULL; + blob->type = BOF_TYPE_BLOB; + blob->value = calloc(1, size); + if (blob->value == NULL) { + bof_decref(blob); + return NULL; + } + blob->size = size; + memcpy(blob->value, value, size); + blob->size += 12; + return blob; +} + +unsigned bof_blob_size(bof_t *bof) +{ + if (!bof_is_blob(bof)) + return 0; + return bof->size - 12; +} + +void *bof_blob_value(bof_t *bof) +{ + if (!bof_is_blob(bof)) + return NULL; + return bof->value; +} + +/* + * string + */ +bof_t *bof_string(const char *value) +{ + bof_t *string = bof_object(); + + if (string == NULL) + return NULL; + string->type = BOF_TYPE_STRING; + string->size = strlen(value) + 1; + string->value = calloc(1, string->size); + if (string->value == NULL) { + bof_decref(string); + return NULL; + } + strcpy(string->value, value); + string->size += 12; + return string; +} + +/* + * int32 + */ +bof_t *bof_int32(int32_t value) +{ + bof_t *int32 = bof_object(); + + if (int32 == NULL) + return NULL; + int32->type = BOF_TYPE_INT32; + int32->size = 4; + int32->value = calloc(1, int32->size); + if (int32->value == NULL) { + bof_decref(int32); + return NULL; + } + memcpy(int32->value, &value, 4); + int32->size += 12; + return int32; +} + +int32_t bof_int32_value(bof_t *bof) +{ + return *((uint32_t*)bof->value); +} + +/* + * common + */ +static void bof_indent(int level) +{ + int i; + + for (i = 0; i < level; i++) + fprintf(stderr, " "); +} + +static void bof_print_bof(bof_t *bof, int level, int entry) +{ + bof_indent(level); + if (bof == NULL) { + fprintf(stderr, "--NULL-- for entry %d\n", entry); + return; + } + switch (bof->type) { + case BOF_TYPE_STRING: + fprintf(stderr, "%p string [%s %d]\n", bof, (char*)bof->value, bof->size); + break; + case BOF_TYPE_INT32: + fprintf(stderr, "%p int32 [%d %d]\n", bof, *(int*)bof->value, bof->size); + break; + case BOF_TYPE_BLOB: + fprintf(stderr, "%p blob [%d]\n", bof, bof->size); + break; + case BOF_TYPE_NULL: + fprintf(stderr, "%p null [%d]\n", bof, bof->size); + break; + case BOF_TYPE_OBJECT: + fprintf(stderr, "%p object [%d %d]\n", bof, bof->array_size / 2, bof->size); + break; + case BOF_TYPE_ARRAY: + fprintf(stderr, "%p array [%d %d]\n", bof, bof->array_size, bof->size); + break; + default: + fprintf(stderr, "%p unknown [%d]\n", bof, bof->type); + return; + } +} + +static void bof_print_rec(bof_t *bof, int level, int entry) +{ + unsigned i; + + bof_print_bof(bof, level, entry); + for (i = 0; i < bof->array_size; i++) { + bof_print_rec(bof->array[i], level + 2, i); + } +} + +void bof_print(bof_t *bof) +{ + bof_print_rec(bof, 0, 0); +} + +static int bof_read(bof_t *root, FILE *file, long end, int level) +{ + bof_t *bof = NULL; + int r; + + if (ftell(file) >= end) { + return 0; + } + r = bof_entry_grow(root); + if (r) + return r; + bof = bof_object(); + if (bof == NULL) + return -ENOMEM; + bof->offset = ftell(file); + r = fread(&bof->type, 4, 1, file); + if (r != 1) + goto out_err; + r = fread(&bof->size, 4, 1, file); + if (r != 1) + goto out_err; + r = fread(&bof->array_size, 4, 1, file); + if (r != 1) + goto out_err; + switch (bof->type) { + case BOF_TYPE_STRING: + case BOF_TYPE_INT32: + case BOF_TYPE_BLOB: + bof->value = calloc(1, bof->size - 12); + if (bof->value == NULL) { + goto out_err; + } + r = fread(bof->value, bof->size - 12, 1, file); + if (r != 1) { + fprintf(stderr, "error reading %d\n", bof->size - 12); + goto out_err; + } + break; + case BOF_TYPE_NULL: + return 0; + case BOF_TYPE_OBJECT: + case BOF_TYPE_ARRAY: + r = bof_read(bof, file, bof->offset + bof->size, level + 2); + if (r) + goto out_err; + break; + default: + fprintf(stderr, "invalid type %d\n", bof->type); + goto out_err; + } + root->array[root->centry++] = bof; + return bof_read(root, file, end, level); +out_err: + bof_decref(bof); + return -EINVAL; +} + +bof_t *bof_load_file(const char *filename) +{ + bof_t *root = bof_object(); + int r; + + if (root == NULL) { + fprintf(stderr, "%s failed to create root object\n", __func__); + return NULL; + } + root->file = fopen(filename, "r"); + if (root->file == NULL) + goto out_err; + r = fseek(root->file, 0L, SEEK_SET); + if (r) { + fprintf(stderr, "%s failed to seek into file %s\n", __func__, filename); + goto out_err; + } + root->offset = ftell(root->file); + r = fread(&root->type, 4, 1, root->file); + if (r != 1) + goto out_err; + r = fread(&root->size, 4, 1, root->file); + if (r != 1) + goto out_err; + r = fread(&root->array_size, 4, 1, root->file); + if (r != 1) + goto out_err; + r = bof_read(root, root->file, root->offset + root->size, 2); + if (r) + goto out_err; + return root; +out_err: + bof_decref(root); + return NULL; +} + +void bof_incref(bof_t *bof) +{ + bof->refcount++; +} + +void bof_decref(bof_t *bof) +{ + unsigned i; + + if (bof == NULL) + return; + if (--bof->refcount > 0) + return; + for (i = 0; i < bof->array_size; i++) { + bof_decref(bof->array[i]); + bof->array[i] = NULL; + } + bof->array_size = 0; + if (bof->file) { + fclose(bof->file); + bof->file = NULL; + } + free(bof->array); + free(bof->value); + free(bof); +} + +static int bof_file_write(bof_t *bof, FILE *file) +{ + unsigned i; + int r; + + r = fwrite(&bof->type, 4, 1, file); + if (r != 1) + return -EINVAL; + r = fwrite(&bof->size, 4, 1, file); + if (r != 1) + return -EINVAL; + r = fwrite(&bof->array_size, 4, 1, file); + if (r != 1) + return -EINVAL; + switch (bof->type) { + case BOF_TYPE_NULL: + if (bof->size) + return -EINVAL; + break; + case BOF_TYPE_STRING: + case BOF_TYPE_INT32: + case BOF_TYPE_BLOB: + r = fwrite(bof->value, bof->size - 12, 1, file); + if (r != 1) + return -EINVAL; + break; + case BOF_TYPE_OBJECT: + case BOF_TYPE_ARRAY: + for (i = 0; i < bof->array_size; i++) { + r = bof_file_write(bof->array[i], file); + if (r) + return r; + } + break; + default: + return -EINVAL; + } + return 0; +} + +int bof_dump_file(bof_t *bof, const char *filename) +{ + unsigned i; + int r = 0; + + if (bof->file) { + fclose(bof->file); + bof->file = NULL; + } + bof->file = fopen(filename, "w"); + if (bof->file == NULL) { + fprintf(stderr, "%s failed to open file %s\n", __func__, filename); + r = -EINVAL; + goto out_err; + } + r = fseek(bof->file, 0L, SEEK_SET); + if (r) { + fprintf(stderr, "%s failed to seek into file %s\n", __func__, filename); + goto out_err; + } + r = fwrite(&bof->type, 4, 1, bof->file); + if (r != 1) + goto out_err; + r = fwrite(&bof->size, 4, 1, bof->file); + if (r != 1) + goto out_err; + r = fwrite(&bof->array_size, 4, 1, bof->file); + if (r != 1) + goto out_err; + for (i = 0; i < bof->array_size; i++) { + r = bof_file_write(bof->array[i], bof->file); + if (r) + return r; + } +out_err: + fclose(bof->file); + bof->file = NULL; + return r; +} diff --git a/src/gallium/winsys/drm/r600/core/bof.h b/src/gallium/winsys/drm/r600/core/bof.h new file mode 100644 index 00000000000..014affb74f1 --- /dev/null +++ b/src/gallium/winsys/drm/r600/core/bof.h @@ -0,0 +1,90 @@ +/* + * Copyright 2010 Jerome Glisse <[email protected]> + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Jerome Glisse + */ +#ifndef BOF_H +#define BOF_H + +#include <stdio.h> +#include <stdint.h> + +#define BOF_TYPE_STRING 0 +#define BOF_TYPE_NULL 1 +#define BOF_TYPE_BLOB 2 +#define BOF_TYPE_OBJECT 3 +#define BOF_TYPE_ARRAY 4 +#define BOF_TYPE_INT32 5 + +struct bof; + +typedef struct bof { + struct bof **array; + unsigned centry; + unsigned nentry; + unsigned refcount; + FILE *file; + uint32_t type; + uint32_t size; + uint32_t array_size; + void *value; + long offset; +} bof_t; + +extern int bof_file_flush(bof_t *root); +extern bof_t *bof_file_new(const char *filename); +extern int bof_object_dump(bof_t *object, const char *filename); + +/* object */ +extern bof_t *bof_object(void); +extern bof_t *bof_object_get(bof_t *object, const char *keyname); +extern int bof_object_set(bof_t *object, const char *keyname, bof_t *value); +/* array */ +extern bof_t *bof_array(void); +extern int bof_array_append(bof_t *array, bof_t *value); +extern bof_t *bof_array_get(bof_t *bof, unsigned i); +extern unsigned bof_array_size(bof_t *bof); +/* blob */ +extern bof_t *bof_blob(unsigned size, void *value); +extern unsigned bof_blob_size(bof_t *bof); +extern void *bof_blob_value(bof_t *bof); +/* string */ +extern bof_t *bof_string(const char *value); +/* int32 */ +extern bof_t *bof_int32(int32_t value); +extern int32_t bof_int32_value(bof_t *bof); +/* common functions */ +extern void bof_decref(bof_t *bof); +extern void bof_incref(bof_t *bof); +extern bof_t *bof_load_file(const char *filename); +extern int bof_dump_file(bof_t *bof, const char *filename); +extern void bof_print(bof_t *bof); + +static inline int bof_is_object(bof_t *bof){return (bof->type == BOF_TYPE_OBJECT);} +static inline int bof_is_blob(bof_t *bof){return (bof->type == BOF_TYPE_BLOB);} +static inline int bof_is_null(bof_t *bof){return (bof->type == BOF_TYPE_NULL);} +static inline int bof_is_int32(bof_t *bof){return (bof->type == BOF_TYPE_INT32);} +static inline int bof_is_array(bof_t *bof){return (bof->type == BOF_TYPE_ARRAY);} +static inline int bof_is_string(bof_t *bof){return (bof->type == BOF_TYPE_STRING);} + +#endif diff --git a/src/gallium/winsys/drm/r600/core/r600_drm.c b/src/gallium/winsys/drm/r600/core/r600_drm.c new file mode 100644 index 00000000000..028f4439449 --- /dev/null +++ b/src/gallium/winsys/drm/r600/core/r600_drm.c @@ -0,0 +1,170 @@ +/* + * Copyright 2010 Jerome Glisse <[email protected]> + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Jerome Glisse + * Corbin Simpson <[email protected]> + * Joakim Sindholt <[email protected]> + */ +#include <sys/ioctl.h> +#include "trace/tr_drm.h" +#include "util/u_inlines.h" +#include "util/u_debug.h" +#include "state_tracker/drm_api.h" +#include "radeon_priv.h" +#include "r600_screen.h" +#include "r600_texture.h" + +static struct pipe_screen *r600_drm_create_screen(struct drm_api* api, int drmfd, + struct drm_create_screen_arg *arg) +{ + struct radeon *rw = radeon_new(drmfd, 0); + + if (rw == NULL) + return NULL; + return radeon_create_screen(rw); +} + +static boolean r600_buffer_from_texture(struct drm_api *api, + struct pipe_screen *screen, + struct pipe_texture *texture, + struct pipe_buffer **buffer, + unsigned *stride) +{ + return r600_get_texture_buffer(screen, texture, buffer, stride); +} + +static struct pipe_buffer *r600_buffer_from_handle(struct drm_api *api, + struct pipe_screen *screen, + const char *name, + unsigned handle) +{ + struct radeon *rw = (struct radeon*)screen->winsys; + struct r600_pipe_buffer *rbuffer; + struct radeon_bo *bo = NULL; + + bo = radeon_bo(rw, handle, 0, 0, NULL); + if (bo == NULL) { + return NULL; + } + + rbuffer = calloc(1, sizeof(struct r600_pipe_buffer)); + if (rbuffer == NULL) { + radeon_bo_decref(rw, bo); + return NULL; + } + + pipe_reference_init(&rbuffer->base.reference, 1); + rbuffer->base.screen = screen; + rbuffer->base.usage = PIPE_BUFFER_USAGE_PIXEL; + rbuffer->bo = bo; + return &rbuffer->base; +} + +static struct pipe_texture *r600_texture_from_shared_handle(struct drm_api *api, + struct pipe_screen *screen, + struct pipe_texture *templ, + const char *name, + unsigned stride, + unsigned handle) +{ + struct pipe_buffer *buffer; + struct pipe_texture *blanket; + + + buffer = r600_buffer_from_handle(api, screen, name, handle); + if (buffer == NULL) { + return NULL; + } + blanket = screen->texture_blanket(screen, templ, &stride, buffer); + pipe_buffer_reference(&buffer, NULL); + return blanket; +} + +static boolean r600_shared_handle_from_texture(struct drm_api *api, + struct pipe_screen *screen, + struct pipe_texture *texture, + unsigned *stride, + unsigned *handle) +{ + struct radeon *rw = (struct radeon*)screen->winsys; + struct drm_gem_flink flink; + struct r600_pipe_buffer* rbuffer; + struct pipe_buffer *buffer = NULL; + int r; + + if (!r600_buffer_from_texture(api, screen, texture, &buffer, stride)) { + return FALSE; + } + + rbuffer = (struct r600_pipe_buffer*)buffer; + if (!rbuffer->flink) { + flink.handle = rbuffer->bo->handle; + r = ioctl(rw->fd, DRM_IOCTL_GEM_FLINK, &flink); + if (r) { + return FALSE; + } + rbuffer->flink = flink.name; + } + *handle = rbuffer->flink; + return TRUE; +} + +static boolean r600_local_handle_from_texture(struct drm_api *api, + struct pipe_screen *screen, + struct pipe_texture *texture, + unsigned *stride, + unsigned *handle) +{ + struct pipe_buffer *buffer = NULL; + + if (!r600_buffer_from_texture(api, screen, texture, &buffer, stride)) { + return FALSE; + } + *handle = ((struct r600_pipe_buffer*)buffer)->bo->handle; + pipe_buffer_reference(&buffer, NULL); + return TRUE; +} + +static void r600_drm_api_destroy(struct drm_api *api) +{ + return; +} + +struct drm_api drm_api_hooks = { + .name = "r600", + .driver_name = "r600", + .create_screen = r600_drm_create_screen, + .texture_from_shared_handle = r600_texture_from_shared_handle, + .shared_handle_from_texture = r600_shared_handle_from_texture, + .local_handle_from_texture = r600_local_handle_from_texture, + .destroy = r600_drm_api_destroy, +}; + +struct drm_api* drm_api_create() +{ +#ifdef DEBUG + return trace_drm_create(&drm_api_hooks); +#else + return &drm_api_hooks; +#endif +} diff --git a/src/gallium/winsys/drm/r600/core/r600_state.c b/src/gallium/winsys/drm/r600/core/r600_state.c new file mode 100644 index 00000000000..c93783b4b03 --- /dev/null +++ b/src/gallium/winsys/drm/r600/core/r600_state.c @@ -0,0 +1,399 @@ +/* + * Copyright 2010 Jerome Glisse <[email protected]> + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Jerome Glisse + */ +#include <stdio.h> +#include <stdlib.h> +#include <string.h> +#include <errno.h> +#include "radeon_priv.h" +#include "r600d.h" + +static int r600_state_pm4_resource(struct radeon_state *state); +static int r600_state_pm4_cb0(struct radeon_state *state); +static int r600_state_pm4_vgt(struct radeon_state *state); +static int r600_state_pm4_db(struct radeon_state *state); +static int r600_state_pm4_shader(struct radeon_state *state); +static int r600_state_pm4_draw(struct radeon_state *state); +static int r600_state_pm4_config(struct radeon_state *state); +static int r600_state_pm4_generic(struct radeon_state *state); +static int r700_state_pm4_config(struct radeon_state *state); +static int r700_state_pm4_cb0(struct radeon_state *state); +static int r700_state_pm4_db(struct radeon_state *state); + +#include "r600_states.h" + +/* + * r600/r700 state functions + */ +static int r600_state_pm4_bytecode(struct radeon_state *state, unsigned offset, unsigned id, unsigned nreg) +{ + const struct radeon_register *regs = state->radeon->type[state->type].regs; + unsigned i; + int r; + + if (!offset) { + fprintf(stderr, "%s invalid register for state %d %d\n", + __func__, state->type, id); + return -EINVAL; + } + if (offset >= R600_CONFIG_REG_OFFSET && offset < R600_CONFIG_REG_END) { + state->pm4[state->cpm4++] = PKT3(PKT3_SET_CONFIG_REG, nreg); + state->pm4[state->cpm4++] = (offset - R600_CONFIG_REG_OFFSET) >> 2; + for (i = 0; i < nreg; i++) { + state->pm4[state->cpm4++] = state->states[id + i]; + } + for (i = 0; i < nreg; i++) { + if (regs[id + i].need_reloc) { + state->pm4[state->cpm4++] = PKT3(PKT3_NOP, 0); + r = radeon_state_reloc(state, state->cpm4, regs[id + i].bo_id); + if (r) + return r; + state->pm4[state->cpm4++] = state->bo[regs[id + i].bo_id]->handle; + } + } + return 0; + } + if (offset >= R600_CONTEXT_REG_OFFSET && offset < R600_CONTEXT_REG_END) { + state->pm4[state->cpm4++] = PKT3(PKT3_SET_CONTEXT_REG, nreg); + state->pm4[state->cpm4++] = (offset - R600_CONTEXT_REG_OFFSET) >> 2; + for (i = 0; i < nreg; i++) { + state->pm4[state->cpm4++] = state->states[id + i]; + } + for (i = 0; i < nreg; i++) { + if (regs[id + i].need_reloc) { + state->pm4[state->cpm4++] = PKT3(PKT3_NOP, 0); + r = radeon_state_reloc(state, state->cpm4, regs[id + i].bo_id); + if (r) + return r; + state->pm4[state->cpm4++] = state->bo[regs[id + i].bo_id]->handle; + } + } + return 0; + } + if (offset >= R600_ALU_CONST_OFFSET && offset < R600_ALU_CONST_END) { + state->pm4[state->cpm4++] = PKT3(PKT3_SET_ALU_CONST, nreg); + state->pm4[state->cpm4++] = (offset - R600_ALU_CONST_OFFSET) >> 2; + for (i = 0; i < nreg; i++) { + state->pm4[state->cpm4++] = state->states[id + i]; + } + return 0; + } + if (offset >= R600_SAMPLER_OFFSET && offset < R600_SAMPLER_END) { + state->pm4[state->cpm4++] = PKT3(PKT3_SET_SAMPLER, nreg); + state->pm4[state->cpm4++] = (offset - R600_SAMPLER_OFFSET) >> 2; + for (i = 0; i < nreg; i++) { + state->pm4[state->cpm4++] = state->states[id + i]; + } + return 0; + } + fprintf(stderr, "%s unsupported offset 0x%08X\n", __func__, offset); + return -EINVAL; +} + +static int r600_state_pm4_generic(struct radeon_state *state) +{ + struct radeon *radeon = state->radeon; + unsigned i, offset, nreg, type, coffset, loffset, soffset; + unsigned start; + int r; + + if (!state->nstates) + return 0; + type = state->type; + soffset = (state->id - radeon->type[type].id) * radeon->type[type].stride; + offset = loffset = radeon->type[type].regs[0].offset + soffset; + start = 0; + for (i = 1, nreg = 1; i < state->nstates; i++) { + coffset = radeon->type[type].regs[i].offset + soffset; + if (coffset == (loffset + 4)) { + nreg++; + loffset = coffset; + } else { + r = r600_state_pm4_bytecode(state, offset, start, nreg); + if (r) { + fprintf(stderr, "%s invalid 0x%08X %d\n", __func__, start, nreg); + return r; + } + offset = loffset = coffset; + nreg = 1; + start = i; + } + } + return r600_state_pm4_bytecode(state, offset, start, nreg); +} + +static void r600_state_pm4_with_flush(struct radeon_state *state, u32 flags) +{ + unsigned i, j, add, size; + + state->nreloc = 0; + for (i = 0; i < state->nbo; i++) { + for (j = 0, add = 1; j < state->nreloc; j++) { + if (state->bo[state->reloc_bo_id[j]] == state->bo[i]) { + add = 0; + break; + } + } + if (add) { + state->reloc_bo_id[state->nreloc++] = i; + } + } + for (i = 0; i < state->nreloc; i++) { + size = (state->bo[state->reloc_bo_id[i]]->size + 255) >> 8; + state->pm4[state->cpm4++] = PKT3(PKT3_SURFACE_SYNC, 3); + state->pm4[state->cpm4++] = flags; + state->pm4[state->cpm4++] = size; + state->pm4[state->cpm4++] = 0x00000000; + state->pm4[state->cpm4++] = 0x0000000A; + state->pm4[state->cpm4++] = PKT3(PKT3_NOP, 0); + state->reloc_pm4_id[i] = state->cpm4; + state->pm4[state->cpm4++] = state->bo[state->reloc_bo_id[i]]->handle; + } +} + +static int r600_state_pm4_cb0(struct radeon_state *state) +{ + int r; + + r600_state_pm4_with_flush(state, S_0085F0_CB_ACTION_ENA(1) | + S_0085F0_CB0_DEST_BASE_ENA(1)); + r = r600_state_pm4_generic(state); + if (r) + return r; + state->pm4[state->cpm4++] = PKT3(PKT3_SURFACE_BASE_UPDATE, 0); + state->pm4[state->cpm4++] = 0x00000002; + return 0; +} + +static int r700_state_pm4_cb0(struct radeon_state *state) +{ + int r; + + r600_state_pm4_with_flush(state, S_0085F0_CB_ACTION_ENA(1) | + S_0085F0_CB0_DEST_BASE_ENA(1)); + r = r600_state_pm4_generic(state); + if (r) + return r; + return 0; +} + +static int r600_state_pm4_db(struct radeon_state *state) +{ + int r; + + r600_state_pm4_with_flush(state, S_0085F0_DB_ACTION_ENA(1) | + S_0085F0_DB_DEST_BASE_ENA(1)); + r = r600_state_pm4_generic(state); + if (r) + return r; + state->pm4[state->cpm4++] = PKT3(PKT3_SURFACE_BASE_UPDATE, 0); + state->pm4[state->cpm4++] = 0x00000001; + return 0; +} + +static int r700_state_pm4_db(struct radeon_state *state) +{ + int r; + + r600_state_pm4_with_flush(state, S_0085F0_DB_ACTION_ENA(1) | + S_0085F0_DB_DEST_BASE_ENA(1)); + r = r600_state_pm4_generic(state); + if (r) + return r; + return 0; +} + +static int r600_state_pm4_config(struct radeon_state *state) +{ + state->pm4[state->cpm4++] = PKT3(PKT3_START_3D_CMDBUF, 0); + state->pm4[state->cpm4++] = 0x00000000; + state->pm4[state->cpm4++] = PKT3(PKT3_CONTEXT_CONTROL, 1); + state->pm4[state->cpm4++] = 0x80000000; + state->pm4[state->cpm4++] = 0x80000000; + state->pm4[state->cpm4++] = PKT3(PKT3_EVENT_WRITE, 0); + state->pm4[state->cpm4++] = 0x00000016; + state->pm4[state->cpm4++] = PKT3(PKT3_SET_CONFIG_REG, 1); + state->pm4[state->cpm4++] = 0x00000010; + state->pm4[state->cpm4++] = 0x00028000; + return r600_state_pm4_generic(state); +} + +static int r700_state_pm4_config(struct radeon_state *state) +{ + state->pm4[state->cpm4++] = PKT3(PKT3_CONTEXT_CONTROL, 1); + state->pm4[state->cpm4++] = 0x80000000; + state->pm4[state->cpm4++] = 0x80000000; + state->pm4[state->cpm4++] = PKT3(PKT3_EVENT_WRITE, 0); + state->pm4[state->cpm4++] = 0x00000016; + state->pm4[state->cpm4++] = PKT3(PKT3_SET_CONFIG_REG, 1); + state->pm4[state->cpm4++] = 0x00000010; + state->pm4[state->cpm4++] = 0x00028000; + return r600_state_pm4_generic(state); +} + +static int r600_state_pm4_shader(struct radeon_state *state) +{ + r600_state_pm4_with_flush(state, S_0085F0_SH_ACTION_ENA(1)); + return r600_state_pm4_generic(state); +} + +static int r600_state_pm4_vgt(struct radeon_state *state) +{ + int r; + + r = r600_state_pm4_bytecode(state, R_028400_VGT_MAX_VTX_INDX, R600_VGT__VGT_MAX_VTX_INDX, 1); + if (r) + return r; + r = r600_state_pm4_bytecode(state, R_028404_VGT_MIN_VTX_INDX, R600_VGT__VGT_MIN_VTX_INDX, 1); + if (r) + return r; + r = r600_state_pm4_bytecode(state, R_028408_VGT_INDX_OFFSET, R600_VGT__VGT_INDX_OFFSET, 1); + if (r) + return r; + r = r600_state_pm4_bytecode(state, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, R600_VGT__VGT_MULTI_PRIM_IB_RESET_INDX, 1); + if (r) + return r; + r = r600_state_pm4_bytecode(state, R_008958_VGT_PRIMITIVE_TYPE, R600_VGT__VGT_PRIMITIVE_TYPE, 1); + if (r) + return r; + state->pm4[state->cpm4++] = PKT3(PKT3_INDEX_TYPE, 0); + state->pm4[state->cpm4++] = state->states[R600_VGT__VGT_DMA_INDEX_TYPE]; + state->pm4[state->cpm4++] = PKT3(PKT3_NUM_INSTANCES, 0); + state->pm4[state->cpm4++] = state->states[R600_VGT__VGT_DMA_NUM_INSTANCES]; + return 0; +} + +static int r600_state_pm4_draw(struct radeon_state *state) +{ + unsigned i; + int r; + + if (state->nbo) { + state->pm4[state->cpm4++] = PKT3(PKT3_DRAW_INDEX, 3); + state->pm4[state->cpm4++] = state->states[R600_DRAW__VGT_DMA_BASE]; + state->pm4[state->cpm4++] = state->states[R600_DRAW__VGT_DMA_BASE_HI]; + state->pm4[state->cpm4++] = state->states[R600_DRAW__VGT_NUM_INDICES]; + state->pm4[state->cpm4++] = state->states[R600_DRAW__VGT_DRAW_INITIATOR]; + state->pm4[state->cpm4++] = PKT3(PKT3_NOP, 0); + r = radeon_state_reloc(state, state->cpm4, 0); + if (r) + return r; + state->pm4[state->cpm4++] = state->bo[0]->handle; + } else if (state->nimmd) { + state->pm4[state->cpm4++] = PKT3(PKT3_DRAW_INDEX_IMMD, state->nimmd + 1); + state->pm4[state->cpm4++] = state->states[R600_DRAW__VGT_NUM_INDICES]; + state->pm4[state->cpm4++] = state->states[R600_DRAW__VGT_DRAW_INITIATOR]; + for (i = 0; i < state->nimmd; i++) { + state->pm4[state->cpm4++] = state->immd[i]; + } + } else { + state->pm4[state->cpm4++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1); + state->pm4[state->cpm4++] = state->states[R600_DRAW__VGT_NUM_INDICES]; + state->pm4[state->cpm4++] = state->states[R600_DRAW__VGT_DRAW_INITIATOR]; + } + state->pm4[state->cpm4++] = PKT3(PKT3_EVENT_WRITE, 0); + state->pm4[state->cpm4++] = 0x00000016; + return 0; +} + +static int r600_state_pm4_resource(struct radeon_state *state) +{ + u32 flags, type, nbo, offset, soffset; + int r; + + soffset = (state->id - state->radeon->type[state->type].id) * state->radeon->type[state->type].stride; + type = G_038018_TYPE(state->states[6]); + switch (type) { + case 2: + flags = S_0085F0_TC_ACTION_ENA(1); + nbo = 2; + break; + case 3: + flags = S_0085F0_VC_ACTION_ENA(1); + nbo = 1; + break; + default: + return 0; + } + if (state->nbo != nbo) { + fprintf(stderr, "%s need %d bo got %d\n", __func__, nbo, state->nbo); + return -EINVAL; + } + r600_state_pm4_with_flush(state, flags); + offset = state->radeon->type[state->type].regs[0].offset + soffset; + state->pm4[state->cpm4++] = PKT3(PKT3_SET_RESOURCE, 7); + state->pm4[state->cpm4++] = (offset - R_038000_SQ_TEX_RESOURCE_WORD0_0) >> 2; + state->pm4[state->cpm4++] = state->states[0]; + state->pm4[state->cpm4++] = state->states[1]; + state->pm4[state->cpm4++] = state->states[2]; + state->pm4[state->cpm4++] = state->states[3]; + state->pm4[state->cpm4++] = state->states[4]; + state->pm4[state->cpm4++] = state->states[5]; + state->pm4[state->cpm4++] = state->states[6]; + state->pm4[state->cpm4++] = PKT3(PKT3_NOP, 0); + r = radeon_state_reloc(state, state->cpm4, 0); + if (r) + return r; + state->pm4[state->cpm4++] = state->bo[0]->handle; + if (type == 2) { + state->pm4[state->cpm4++] = PKT3(PKT3_NOP, 0); + r = radeon_state_reloc(state, state->cpm4, 1); + if (r) + return r; + state->pm4[state->cpm4++] = state->bo[1]->handle; + } + return 0; +} + +int r600_init(struct radeon *radeon) +{ + switch (radeon->family) { + case CHIP_R600: + case CHIP_RV610: + case CHIP_RV630: + case CHIP_RV670: + case CHIP_RV620: + case CHIP_RV635: + case CHIP_RS780: + radeon->ntype = R600_NTYPE; + radeon->nstate = R600_NSTATE; + radeon->type = R600_types; + break; + case CHIP_RS880: + case CHIP_RV770: + case CHIP_RV730: + case CHIP_RV710: + case CHIP_RV740: + radeon->ntype = R600_NTYPE; + radeon->nstate = R600_NSTATE; + radeon->type = R700_types; + break; + default: + fprintf(stderr, "%s unknown or unsupported chipset 0x%04X\n", + __func__, radeon->device); + return -EINVAL; + } + return 0; +} diff --git a/src/gallium/winsys/drm/r600/core/r600_states.h b/src/gallium/winsys/drm/r600/core/r600_states.h new file mode 100644 index 00000000000..5896df21b21 --- /dev/null +++ b/src/gallium/winsys/drm/r600/core/r600_states.h @@ -0,0 +1,461 @@ +/* + * Copyright © 2009 Jerome Glisse <[email protected]> + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License + * as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software Foundation, + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. + */ +#ifndef R600_STATES_H +#define R600_STATES_H + +static const struct radeon_register R600_CONFIG_names[] = { + {0x00008C00, 0, 0, "SQ_CONFIG"}, + {0x00008C04, 0, 0, "SQ_GPR_RESOURCE_MGMT_1"}, + {0x00008C08, 0, 0, "SQ_GPR_RESOURCE_MGMT_2"}, + {0x00008C0C, 0, 0, "SQ_THREAD_RESOURCE_MGMT"}, + {0x00008C10, 0, 0, "SQ_STACK_RESOURCE_MGMT_1"}, + {0x00008C14, 0, 0, "SQ_STACK_RESOURCE_MGMT_2"}, + {0x00008D8C, 0, 0, "SQ_DYN_GPR_CNTL_PS_FLUSH_REQ"}, + {0x00009508, 0, 0, "TA_CNTL_AUX"}, + {0x00009714, 0, 0, "VC_ENHANCE"}, + {0x00009830, 0, 0, "DB_DEBUG"}, + {0x00009838, 0, 0, "DB_WATERMARKS"}, + {0x00028350, 0, 0, "SX_MISC"}, + {0x000286C8, 0, 0, "SPI_THREAD_GROUPING"}, + {0x000287A0, 0, 0, "CB_SHADER_CONTROL"}, + {0x000288A8, 0, 0, "SQ_ESGS_RING_ITEMSIZE"}, + {0x000288AC, 0, 0, "SQ_GSVS_RING_ITEMSIZE"}, + {0x000288B0, 0, 0, "SQ_ESTMP_RING_ITEMSIZE"}, + {0x000288B4, 0, 0, "SQ_GSTMP_RING_ITEMSIZE"}, + {0x000288B8, 0, 0, "SQ_VSTMP_RING_ITEMSIZE"}, + {0x000288BC, 0, 0, "SQ_PSTMP_RING_ITEMSIZE"}, + {0x000288C0, 0, 0, "SQ_FBUF_RING_ITEMSIZE"}, + {0x000288C4, 0, 0, "SQ_REDUC_RING_ITEMSIZE"}, + {0x000288C8, 0, 0, "SQ_GS_VERT_ITEMSIZE"}, + {0x00028A10, 0, 0, "VGT_OUTPUT_PATH_CNTL"}, + {0x00028A14, 0, 0, "VGT_HOS_CNTL"}, + {0x00028A18, 0, 0, "VGT_HOS_MAX_TESS_LEVEL"}, + {0x00028A1C, 0, 0, "VGT_HOS_MIN_TESS_LEVEL"}, + {0x00028A20, 0, 0, "VGT_HOS_REUSE_DEPTH"}, + {0x00028A24, 0, 0, "VGT_GROUP_PRIM_TYPE"}, + {0x00028A28, 0, 0, "VGT_GROUP_FIRST_DECR"}, + {0x00028A2C, 0, 0, "VGT_GROUP_DECR"}, + {0x00028A30, 0, 0, "VGT_GROUP_VECT_0_CNTL"}, + {0x00028A34, 0, 0, "VGT_GROUP_VECT_1_CNTL"}, + {0x00028A38, 0, 0, "VGT_GROUP_VECT_0_FMT_CNTL"}, + {0x00028A3C, 0, 0, "VGT_GROUP_VECT_1_FMT_CNTL"}, + {0x00028A40, 0, 0, "VGT_GS_MODE"}, + {0x00028A4C, 0, 0, "PA_SC_MODE_CNTL"}, + {0x00028AB0, 0, 0, "VGT_STRMOUT_EN"}, + {0x00028AB4, 0, 0, "VGT_REUSE_OFF"}, + {0x00028AB8, 0, 0, "VGT_VTX_CNT_EN"}, + {0x00028B20, 0, 0, "VGT_STRMOUT_BUFFER_EN"}, +}; + +static const struct radeon_register R600_CB_CNTL_names[] = { + {0x00028120, 0, 0, "CB_CLEAR_RED"}, + {0x00028124, 0, 0, "CB_CLEAR_GREEN"}, + {0x00028128, 0, 0, "CB_CLEAR_BLUE"}, + {0x0002812C, 0, 0, "CB_CLEAR_ALPHA"}, + {0x0002823C, 0, 0, "CB_SHADER_MASK"}, + {0x00028238, 0, 0, "CB_TARGET_MASK"}, + {0x00028424, 0, 0, "CB_FOG_RED"}, + {0x00028428, 0, 0, "CB_FOG_GREEN"}, + {0x0002842C, 0, 0, "CB_FOG_BLUE"}, + {0x00028808, 0, 0, "CB_COLOR_CONTROL"}, + {0x00028C04, 0, 0, "PA_SC_AA_CONFIG"}, + {0x00028C1C, 0, 0, "PA_SC_AA_SAMPLE_LOCS_MCTX"}, + {0x00028C20, 0, 0, "PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX"}, + {0x00028C30, 0, 0, "CB_CLRCMP_CONTROL"}, + {0x00028C34, 0, 0, "CB_CLRCMP_SRC"}, + {0x00028C38, 0, 0, "CB_CLRCMP_DST"}, + {0x00028C3C, 0, 0, "CB_CLRCMP_MSK"}, + {0x00028C48, 0, 0, "PA_SC_AA_MASK"}, +}; + +static const struct radeon_register R600_RASTERIZER_names[] = { + {0x000286D4, 0, 0, "SPI_INTERP_CONTROL_0"}, + {0x00028810, 0, 0, "PA_CL_CLIP_CNTL"}, + {0x00028814, 0, 0, "PA_SU_SC_MODE_CNTL"}, + {0x0002881C, 0, 0, "PA_CL_VS_OUT_CNTL"}, + {0x00028820, 0, 0, "PA_CL_NANINF_CNTL"}, + {0x00028A00, 0, 0, "PA_SU_POINT_SIZE"}, + {0x00028A04, 0, 0, "PA_SU_POINT_MINMAX"}, + {0x00028A08, 0, 0, "PA_SU_LINE_CNTL"}, + {0x00028A0C, 0, 0, "PA_SC_LINE_STIPPLE"}, + {0x00028A48, 0, 0, "PA_SC_MPASS_PS_CNTL"}, + {0x00028C00, 0, 0, "PA_SC_LINE_CNTL"}, + {0x00028C0C, 0, 0, "PA_CL_GB_VERT_CLIP_ADJ"}, + {0x00028C10, 0, 0, "PA_CL_GB_VERT_DISC_ADJ"}, + {0x00028C14, 0, 0, "PA_CL_GB_HORZ_CLIP_ADJ"}, + {0x00028C18, 0, 0, "PA_CL_GB_HORZ_DISC_ADJ"}, + {0x00028DF8, 0, 0, "PA_SU_POLY_OFFSET_DB_FMT_CNTL"}, + {0x00028DFC, 0, 0, "PA_SU_POLY_OFFSET_CLAMP"}, + {0x00028E00, 0, 0, "PA_SU_POLY_OFFSET_FRONT_SCALE"}, + {0x00028E04, 0, 0, "PA_SU_POLY_OFFSET_FRONT_OFFSET"}, + {0x00028E08, 0, 0, "PA_SU_POLY_OFFSET_BACK_SCALE"}, + {0x00028E0C, 0, 0, "PA_SU_POLY_OFFSET_BACK_OFFSET"}, +}; + +static const struct radeon_register R600_VIEWPORT_names[] = { + {0x000282D0, 0, 0, "PA_SC_VPORT_ZMIN_0"}, + {0x000282D4, 0, 0, "PA_SC_VPORT_ZMAX_0"}, + {0x0002843C, 0, 0, "PA_CL_VPORT_XSCALE_0"}, + {0x00028444, 0, 0, "PA_CL_VPORT_YSCALE_0"}, + {0x0002844C, 0, 0, "PA_CL_VPORT_ZSCALE_0"}, + {0x00028440, 0, 0, "PA_CL_VPORT_XOFFSET_0"}, + {0x00028448, 0, 0, "PA_CL_VPORT_YOFFSET_0"}, + {0x00028450, 0, 0, "PA_CL_VPORT_ZOFFSET_0"}, + {0x00028818, 0, 0, "PA_CL_VTE_CNTL"}, +}; + +static const struct radeon_register R600_SCISSOR_names[] = { + {0x00028030, 0, 0, "PA_SC_SCREEN_SCISSOR_TL"}, + {0x00028034, 0, 0, "PA_SC_SCREEN_SCISSOR_BR"}, + {0x00028200, 0, 0, "PA_SC_WINDOW_OFFSET"}, + {0x00028204, 0, 0, "PA_SC_WINDOW_SCISSOR_TL"}, + {0x00028208, 0, 0, "PA_SC_WINDOW_SCISSOR_BR"}, + {0x0002820C, 0, 0, "PA_SC_CLIPRECT_RULE"}, + {0x00028210, 0, 0, "PA_SC_CLIPRECT_0_TL"}, + {0x00028214, 0, 0, "PA_SC_CLIPRECT_0_BR"}, + {0x00028218, 0, 0, "PA_SC_CLIPRECT_1_TL"}, + {0x0002821C, 0, 0, "PA_SC_CLIPRECT_1_BR"}, + {0x00028220, 0, 0, "PA_SC_CLIPRECT_2_TL"}, + {0x00028224, 0, 0, "PA_SC_CLIPRECT_2_BR"}, + {0x00028228, 0, 0, "PA_SC_CLIPRECT_3_TL"}, + {0x0002822C, 0, 0, "PA_SC_CLIPRECT_3_BR"}, + {0x00028230, 0, 0, "PA_SC_EDGERULE"}, + {0x00028240, 0, 0, "PA_SC_GENERIC_SCISSOR_TL"}, + {0x00028244, 0, 0, "PA_SC_GENERIC_SCISSOR_BR"}, + {0x00028250, 0, 0, "PA_SC_VPORT_SCISSOR_0_TL"}, + {0x00028254, 0, 0, "PA_SC_VPORT_SCISSOR_0_BR"}, +}; + +static const struct radeon_register R600_BLEND_names[] = { + {0x00028414, 0, 0, "CB_BLEND_RED"}, + {0x00028418, 0, 0, "CB_BLEND_GREEN"}, + {0x0002841C, 0, 0, "CB_BLEND_BLUE"}, + {0x00028420, 0, 0, "CB_BLEND_ALPHA"}, + {0x00028780, 0, 0, "CB_BLEND0_CONTROL"}, + {0x00028784, 0, 0, "CB_BLEND1_CONTROL"}, + {0x00028788, 0, 0, "CB_BLEND2_CONTROL"}, + {0x0002878C, 0, 0, "CB_BLEND3_CONTROL"}, + {0x00028790, 0, 0, "CB_BLEND4_CONTROL"}, + {0x00028794, 0, 0, "CB_BLEND5_CONTROL"}, + {0x00028798, 0, 0, "CB_BLEND6_CONTROL"}, + {0x0002879C, 0, 0, "CB_BLEND7_CONTROL"}, + {0x00028804, 0, 0, "CB_BLEND_CONTROL"}, +}; + +static const struct radeon_register R600_DSA_names[] = { + {0x00028028, 0, 0, "DB_STENCIL_CLEAR"}, + {0x0002802C, 0, 0, "DB_DEPTH_CLEAR"}, + {0x00028410, 0, 0, "SX_ALPHA_TEST_CONTROL"}, + {0x00028430, 0, 0, "DB_STENCILREFMASK"}, + {0x00028434, 0, 0, "DB_STENCILREFMASK_BF"}, + {0x00028438, 0, 0, "SX_ALPHA_REF"}, + {0x000286E0, 0, 0, "SPI_FOG_FUNC_SCALE"}, + {0x000286E4, 0, 0, "SPI_FOG_FUNC_BIAS"}, + {0x000286DC, 0, 0, "SPI_FOG_CNTL"}, + {0x00028800, 0, 0, "DB_DEPTH_CONTROL"}, + {0x0002880C, 0, 0, "DB_SHADER_CONTROL"}, + {0x00028D0C, 0, 0, "DB_RENDER_CONTROL"}, + {0x00028D10, 0, 0, "DB_RENDER_OVERRIDE"}, + {0x00028D2C, 0, 0, "DB_SRESULTS_COMPARE_STATE1"}, + {0x00028D30, 0, 0, "DB_PRELOAD_CONTROL"}, + {0x00028D44, 0, 0, "DB_ALPHA_TO_MASK"}, +}; + +static const struct radeon_register R600_VS_SHADER_names[] = { + {0x00028380, 0, 0, "SQ_VTX_SEMANTIC_0"}, + {0x00028384, 0, 0, "SQ_VTX_SEMANTIC_1"}, + {0x00028388, 0, 0, "SQ_VTX_SEMANTIC_2"}, + {0x0002838C, 0, 0, "SQ_VTX_SEMANTIC_3"}, + {0x00028390, 0, 0, "SQ_VTX_SEMANTIC_4"}, + {0x00028394, 0, 0, "SQ_VTX_SEMANTIC_5"}, + {0x00028398, 0, 0, "SQ_VTX_SEMANTIC_6"}, + {0x0002839C, 0, 0, "SQ_VTX_SEMANTIC_7"}, + {0x000283A0, 0, 0, "SQ_VTX_SEMANTIC_8"}, + {0x000283A4, 0, 0, "SQ_VTX_SEMANTIC_9"}, + {0x000283A8, 0, 0, "SQ_VTX_SEMANTIC_10"}, + {0x000283AC, 0, 0, "SQ_VTX_SEMANTIC_11"}, + {0x000283B0, 0, 0, "SQ_VTX_SEMANTIC_12"}, + {0x000283B4, 0, 0, "SQ_VTX_SEMANTIC_13"}, + {0x000283B8, 0, 0, "SQ_VTX_SEMANTIC_14"}, + {0x000283BC, 0, 0, "SQ_VTX_SEMANTIC_15"}, + {0x000283C0, 0, 0, "SQ_VTX_SEMANTIC_16"}, + {0x000283C4, 0, 0, "SQ_VTX_SEMANTIC_17"}, + {0x000283C8, 0, 0, "SQ_VTX_SEMANTIC_18"}, + {0x000283CC, 0, 0, "SQ_VTX_SEMANTIC_19"}, + {0x000283D0, 0, 0, "SQ_VTX_SEMANTIC_20"}, + {0x000283D4, 0, 0, "SQ_VTX_SEMANTIC_21"}, + {0x000283D8, 0, 0, "SQ_VTX_SEMANTIC_22"}, + {0x000283DC, 0, 0, "SQ_VTX_SEMANTIC_23"}, + {0x000283E0, 0, 0, "SQ_VTX_SEMANTIC_24"}, + {0x000283E4, 0, 0, "SQ_VTX_SEMANTIC_25"}, + {0x000283E8, 0, 0, "SQ_VTX_SEMANTIC_26"}, + {0x000283EC, 0, 0, "SQ_VTX_SEMANTIC_27"}, + {0x000283F0, 0, 0, "SQ_VTX_SEMANTIC_28"}, + {0x000283F4, 0, 0, "SQ_VTX_SEMANTIC_29"}, + {0x000283F8, 0, 0, "SQ_VTX_SEMANTIC_30"}, + {0x000283FC, 0, 0, "SQ_VTX_SEMANTIC_31"}, + {0x00028614, 0, 0, "SPI_VS_OUT_ID_0"}, + {0x00028618, 0, 0, "SPI_VS_OUT_ID_1"}, + {0x0002861C, 0, 0, "SPI_VS_OUT_ID_2"}, + {0x00028620, 0, 0, "SPI_VS_OUT_ID_3"}, + {0x00028624, 0, 0, "SPI_VS_OUT_ID_4"}, + {0x00028628, 0, 0, "SPI_VS_OUT_ID_5"}, + {0x0002862C, 0, 0, "SPI_VS_OUT_ID_6"}, + {0x00028630, 0, 0, "SPI_VS_OUT_ID_7"}, + {0x00028634, 0, 0, "SPI_VS_OUT_ID_8"}, + {0x00028638, 0, 0, "SPI_VS_OUT_ID_9"}, + {0x000286C4, 0, 0, "SPI_VS_OUT_CONFIG"}, + {0x00028858, 1, 0, "SQ_PGM_START_VS"}, + {0x00028868, 0, 0, "SQ_PGM_RESOURCES_VS"}, + {0x00028894, 1, 1, "SQ_PGM_START_FS"}, + {0x000288A4, 0, 0, "SQ_PGM_RESOURCES_FS"}, + {0x000288D0, 0, 0, "SQ_PGM_CF_OFFSET_VS"}, + {0x000288DC, 0, 0, "SQ_PGM_CF_OFFSET_FS"}, +}; + +static const struct radeon_register R600_PS_SHADER_names[] = { + {0x00028644, 0, 0, "SPI_PS_INPUT_CNTL_0"}, + {0x00028648, 0, 0, "SPI_PS_INPUT_CNTL_1"}, + {0x0002864C, 0, 0, "SPI_PS_INPUT_CNTL_2"}, + {0x00028650, 0, 0, "SPI_PS_INPUT_CNTL_3"}, + {0x00028654, 0, 0, "SPI_PS_INPUT_CNTL_4"}, + {0x00028658, 0, 0, "SPI_PS_INPUT_CNTL_5"}, + {0x0002865C, 0, 0, "SPI_PS_INPUT_CNTL_6"}, + {0x00028660, 0, 0, "SPI_PS_INPUT_CNTL_7"}, + {0x00028664, 0, 0, "SPI_PS_INPUT_CNTL_8"}, + {0x00028668, 0, 0, "SPI_PS_INPUT_CNTL_9"}, + {0x0002866C, 0, 0, "SPI_PS_INPUT_CNTL_10"}, + {0x00028670, 0, 0, "SPI_PS_INPUT_CNTL_11"}, + {0x00028674, 0, 0, "SPI_PS_INPUT_CNTL_12"}, + {0x00028678, 0, 0, "SPI_PS_INPUT_CNTL_13"}, + {0x0002867C, 0, 0, "SPI_PS_INPUT_CNTL_14"}, + {0x00028680, 0, 0, "SPI_PS_INPUT_CNTL_15"}, + {0x00028684, 0, 0, "SPI_PS_INPUT_CNTL_16"}, + {0x00028688, 0, 0, "SPI_PS_INPUT_CNTL_17"}, + {0x0002868C, 0, 0, "SPI_PS_INPUT_CNTL_18"}, + {0x00028690, 0, 0, "SPI_PS_INPUT_CNTL_19"}, + {0x00028694, 0, 0, "SPI_PS_INPUT_CNTL_20"}, + {0x00028698, 0, 0, "SPI_PS_INPUT_CNTL_21"}, + {0x0002869C, 0, 0, "SPI_PS_INPUT_CNTL_22"}, + {0x000286A0, 0, 0, "SPI_PS_INPUT_CNTL_23"}, + {0x000286A4, 0, 0, "SPI_PS_INPUT_CNTL_24"}, + {0x000286A8, 0, 0, "SPI_PS_INPUT_CNTL_25"}, + {0x000286AC, 0, 0, "SPI_PS_INPUT_CNTL_26"}, + {0x000286B0, 0, 0, "SPI_PS_INPUT_CNTL_27"}, + {0x000286B4, 0, 0, "SPI_PS_INPUT_CNTL_28"}, + {0x000286B8, 0, 0, "SPI_PS_INPUT_CNTL_29"}, + {0x000286BC, 0, 0, "SPI_PS_INPUT_CNTL_30"}, + {0x000286C0, 0, 0, "SPI_PS_INPUT_CNTL_31"}, + {0x000286CC, 0, 0, "SPI_PS_IN_CONTROL_0"}, + {0x000286D0, 0, 0, "SPI_PS_IN_CONTROL_1"}, + {0x000286D8, 0, 0, "SPI_INPUT_Z"}, + {0x00028840, 1, 0, "SQ_PGM_START_PS"}, + {0x00028850, 0, 0, "SQ_PGM_RESOURCES_PS"}, + {0x00028854, 0, 0, "SQ_PGM_EXPORTS_PS"}, + {0x000288CC, 0, 0, "SQ_PGM_CF_OFFSET_PS"}, +}; + +static const struct radeon_register R600_PS_CONSTANT_names[] = { + {0x00030000, 0, 0, "SQ_ALU_CONSTANT0_0"}, + {0x00030004, 0, 0, "SQ_ALU_CONSTANT1_0"}, + {0x00030008, 0, 0, "SQ_ALU_CONSTANT2_0"}, + {0x0003000C, 0, 0, "SQ_ALU_CONSTANT3_0"}, +}; + +static const struct radeon_register R600_VS_CONSTANT_names[] = { + {0x00031000, 0, 0, "SQ_ALU_CONSTANT0_256"}, + {0x00031004, 0, 0, "SQ_ALU_CONSTANT1_256"}, + {0x00031008, 0, 0, "SQ_ALU_CONSTANT2_256"}, + {0x0003100C, 0, 0, "SQ_ALU_CONSTANT3_256"}, +}; + +static const struct radeon_register R600_PS_RESOURCE_names[] = { + {0x00038000, 0, 0, "RESOURCE0_WORD0"}, + {0x00038004, 0, 0, "RESOURCE0_WORD1"}, + {0x00038008, 0, 0, "RESOURCE0_WORD2"}, + {0x0003800C, 0, 0, "RESOURCE0_WORD3"}, + {0x00038010, 0, 0, "RESOURCE0_WORD4"}, + {0x00038014, 0, 0, "RESOURCE0_WORD5"}, + {0x00038018, 0, 0, "RESOURCE0_WORD6"}, +}; + +static const struct radeon_register R600_VS_RESOURCE_names[] = { + {0x00039180, 0, 0, "RESOURCE160_WORD0"}, + {0x00039184, 0, 0, "RESOURCE160_WORD1"}, + {0x00039188, 0, 0, "RESOURCE160_WORD2"}, + {0x0003918C, 0, 0, "RESOURCE160_WORD3"}, + {0x00039190, 0, 0, "RESOURCE160_WORD4"}, + {0x00039194, 0, 0, "RESOURCE160_WORD5"}, + {0x00039198, 0, 0, "RESOURCE160_WORD6"}, +}; + +static const struct radeon_register R600_FS_RESOURCE_names[] = { + {0x0003A300, 0, 0, "RESOURCE320_WORD0"}, + {0x0003A304, 0, 0, "RESOURCE320_WORD1"}, + {0x0003A308, 0, 0, "RESOURCE320_WORD2"}, + {0x0003A30C, 0, 0, "RESOURCE320_WORD3"}, + {0x0003A310, 0, 0, "RESOURCE320_WORD4"}, + {0x0003A314, 0, 0, "RESOURCE320_WORD5"}, + {0x0003A318, 0, 0, "RESOURCE320_WORD6"}, +}; + +static const struct radeon_register R600_GS_RESOURCE_names[] = { + {0x0003A4C0, 0, 0, "RESOURCE336_WORD0"}, + {0x0003A4C4, 0, 0, "RESOURCE336_WORD1"}, + {0x0003A4C8, 0, 0, "RESOURCE336_WORD2"}, + {0x0003A4CC, 0, 0, "RESOURCE336_WORD3"}, + {0x0003A4D0, 0, 0, "RESOURCE336_WORD4"}, + {0x0003A4D4, 0, 0, "RESOURCE336_WORD5"}, + {0x0003A4D8, 0, 0, "RESOURCE336_WORD6"}, +}; + +static const struct radeon_register R600_PS_SAMPLER_names[] = { + {0x0003C000, 0, 0, "SQ_TEX_SAMPLER_WORD0_0"}, + {0x0003C004, 0, 0, "SQ_TEX_SAMPLER_WORD1_0"}, + {0x0003C008, 0, 0, "SQ_TEX_SAMPLER_WORD2_0"}, +}; + +static const struct radeon_register R600_VS_SAMPLER_names[] = { + {0x0003C0D8, 0, 0, "SQ_TEX_SAMPLER_WORD0_18"}, + {0x0003C0DC, 0, 0, "SQ_TEX_SAMPLER_WORD1_18"}, + {0x0003C0E0, 0, 0, "SQ_TEX_SAMPLER_WORD2_18"}, +}; + +static const struct radeon_register R600_GS_SAMPLER_names[] = { + {0x0003C1B0, 0, 0, "SQ_TEX_SAMPLER_WORD0_36"}, + {0x0003C1B4, 0, 0, "SQ_TEX_SAMPLER_WORD1_36"}, + {0x0003C1B8, 0, 0, "SQ_TEX_SAMPLER_WORD2_36"}, +}; + +static const struct radeon_register R600_PS_SAMPLER_BORDER_names[] = { + {0x0000A400, 0, 0, "TD_PS_SAMPLER0_BORDER_RED"}, + {0x0000A404, 0, 0, "TD_PS_SAMPLER0_BORDER_GREEN"}, + {0x0000A408, 0, 0, "TD_PS_SAMPLER0_BORDER_BLUE"}, + {0x0000A40C, 0, 0, "TD_PS_SAMPLER0_BORDER_ALPHA"}, +}; + +static const struct radeon_register R600_VS_SAMPLER_BORDER_names[] = { + {0x0000A600, 0, 0, "TD_VS_SAMPLER0_BORDER_RED"}, + {0x0000A604, 0, 0, "TD_VS_SAMPLER0_BORDER_GREEN"}, + {0x0000A608, 0, 0, "TD_VS_SAMPLER0_BORDER_BLUE"}, + {0x0000A60C, 0, 0, "TD_VS_SAMPLER0_BORDER_ALPHA"}, +}; + +static const struct radeon_register R600_GS_SAMPLER_BORDER_names[] = { + {0x0000A800, 0, 0, "TD_GS_SAMPLER0_BORDER_RED"}, + {0x0000A804, 0, 0, "TD_GS_SAMPLER0_BORDER_GREEN"}, + {0x0000A808, 0, 0, "TD_GS_SAMPLER0_BORDER_BLUE"}, + {0x0000A80C, 0, 0, "TD_GS_SAMPLER0_BORDER_ALPHA"}, +}; + +static const struct radeon_register R600_CB0_names[] = { + {0x00028040, 1, 0, "CB_COLOR0_BASE"}, + {0x000280A0, 0, 0, "CB_COLOR0_INFO"}, + {0x00028060, 0, 0, "CB_COLOR0_SIZE"}, + {0x00028080, 0, 0, "CB_COLOR0_VIEW"}, + {0x000280E0, 1, 1, "CB_COLOR0_FRAG"}, + {0x000280C0, 1, 2, "CB_COLOR0_TILE"}, + {0x00028100, 0, 0, "CB_COLOR0_MASK"}, +}; + +static const struct radeon_register R600_DB_names[] = { + {0x0002800C, 1, 0, "DB_DEPTH_BASE"}, + {0x00028000, 0, 0, "DB_DEPTH_SIZE"}, + {0x00028004, 0, 0, "DB_DEPTH_VIEW"}, + {0x00028010, 0, 0, "DB_DEPTH_INFO"}, + {0x00028D24, 0, 0, "DB_HTILE_SURFACE"}, + {0x00028D34, 0, 0, "DB_PREFETCH_LIMIT"}, +}; + +static const struct radeon_register R600_VGT_names[] = { + {0x00008958, 0, 0, "VGT_PRIMITIVE_TYPE"}, + {0x00028400, 0, 0, "VGT_MAX_VTX_INDX"}, + {0x00028404, 0, 0, "VGT_MIN_VTX_INDX"}, + {0x00028408, 0, 0, "VGT_INDX_OFFSET"}, + {0x0002840C, 0, 0, "VGT_MULTI_PRIM_IB_RESET_INDX"}, + {0x00028A7C, 0, 0, "VGT_DMA_INDEX_TYPE"}, + {0x00028A84, 0, 0, "VGT_PRIMITIVEID_EN"}, + {0x00028A88, 0, 0, "VGT_DMA_NUM_INSTANCES"}, + {0x00028A94, 0, 0, "VGT_MULTI_PRIM_IB_RESET_EN"}, + {0x00028AA0, 0, 0, "VGT_INSTANCE_STEP_RATE_0"}, + {0x00028AA4, 0, 0, "VGT_INSTANCE_STEP_RATE_1"}, +}; + +static const struct radeon_register R600_DRAW_names[] = { + {0x00008970, 0, 0, "VGT_NUM_INDICES"}, + {0x000287E4, 0, 0, "VGT_DMA_BASE_HI"}, + {0x000287E8, 1, 0, "VGT_DMA_BASE"}, + {0x000287F0, 0, 0, "VGT_DRAW_INITIATOR"}, +}; + +static struct radeon_type R600_types[] = { + { 128, 0, 0x00000000, 0x00000000, 0x0000, 0, "R600_CONFIG", 41, r600_state_pm4_config, R600_CONFIG_names}, + { 128, 1, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB_CNTL", 18, r600_state_pm4_generic, R600_CB_CNTL_names}, + { 128, 2, 0x00000000, 0x00000000, 0x0000, 0, "R600_RASTERIZER", 21, r600_state_pm4_generic, R600_RASTERIZER_names}, + { 128, 3, 0x00000000, 0x00000000, 0x0000, 0, "R600_VIEWPORT", 9, r600_state_pm4_generic, R600_VIEWPORT_names}, + { 128, 4, 0x00000000, 0x00000000, 0x0000, 0, "R600_SCISSOR", 19, r600_state_pm4_generic, R600_SCISSOR_names}, + { 128, 5, 0x00000000, 0x00000000, 0x0000, 0, "R600_BLEND", 13, r600_state_pm4_generic, R600_BLEND_names}, + { 128, 6, 0x00000000, 0x00000000, 0x0000, 0, "R600_DSA", 16, r600_state_pm4_generic, R600_DSA_names}, + { 128, 7, 0x00000000, 0x00000000, 0x0000, 0, "R600_VS_SHADER", 49, r600_state_pm4_shader, R600_VS_SHADER_names}, + { 128, 8, 0x00000000, 0x00000000, 0x0000, 0, "R600_PS_SHADER", 39, r600_state_pm4_shader, R600_PS_SHADER_names}, + { 128, 9, 0x00030000, 0x00031000, 0x0010, 0, "R600_PS_CONSTANT", 4, r600_state_pm4_generic, R600_PS_CONSTANT_names}, + { 128, 265, 0x00031000, 0x00032000, 0x0010, 0, "R600_VS_CONSTANT", 4, r600_state_pm4_generic, R600_VS_CONSTANT_names}, + { 128, 521, 0x00038000, 0x00039180, 0x001C, 0, "R600_PS_RESOURCE", 7, r600_state_pm4_resource, R600_PS_RESOURCE_names}, + { 128, 681, 0x00039180, 0x0003A300, 0x001C, 0, "R600_VS_RESOURCE", 7, r600_state_pm4_resource, R600_VS_RESOURCE_names}, + { 128, 841, 0x00039180, 0x0003A300, 0x001C, 0, "R600_FS_RESOURCE", 7, r600_state_pm4_resource, R600_FS_RESOURCE_names}, + { 128, 1001, 0x00039180, 0x0003A300, 0x001C, 0, "R600_GS_RESOURCE", 7, r600_state_pm4_resource, R600_GS_RESOURCE_names}, + { 128, 1161, 0x0003C000, 0x0003C0D8, 0x000C, 0, "R600_PS_SAMPLER", 3, r600_state_pm4_generic, R600_PS_SAMPLER_names}, + { 128, 1179, 0x0003C0D8, 0x0003C1B0, 0x000C, 0, "R600_VS_SAMPLER", 3, r600_state_pm4_generic, R600_VS_SAMPLER_names}, + { 128, 1197, 0x0003C1B0, 0x0003C288, 0x000C, 0, "R600_GS_SAMPLER", 3, r600_state_pm4_generic, R600_GS_SAMPLER_names}, + { 128, 1215, 0x0000A400, 0x0000A520, 0x0010, 0, "R600_PS_SAMPLER_BORDER", 4, r600_state_pm4_generic, R600_PS_SAMPLER_BORDER_names}, + { 128, 1233, 0x0000A600, 0x0000A720, 0x0010, 0, "R600_VS_SAMPLER_BORDER", 4, r600_state_pm4_generic, R600_VS_SAMPLER_BORDER_names}, + { 128, 1251, 0x0000A800, 0x0000A920, 0x0010, 0, "R600_GS_SAMPLER_BORDER", 4, r600_state_pm4_generic, R600_GS_SAMPLER_BORDER_names}, + { 128, 1269, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB0", 7, r600_state_pm4_cb0, R600_CB0_names}, + { 128, 1270, 0x00000000, 0x00000000, 0x0000, 0, "R600_DB", 6, r600_state_pm4_db, R600_DB_names}, + { 128, 1271, 0x00000000, 0x00000000, 0x0000, 0, "R600_VGT", 11, r600_state_pm4_vgt, R600_VGT_names}, + { 128, 1272, 0x00000000, 0x00000000, 0x0000, 0, "R600_DRAW", 4, r600_state_pm4_draw, R600_DRAW_names}, +}; + +static struct radeon_type R700_types[] = { + { 128, 0, 0x00000000, 0x00000000, 0x0000, 0, "R600_CONFIG", 41, r700_state_pm4_config, R600_CONFIG_names}, + { 128, 1, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB_CNTL", 18, r600_state_pm4_generic, R600_CB_CNTL_names}, + { 128, 2, 0x00000000, 0x00000000, 0x0000, 0, "R600_RASTERIZER", 21, r600_state_pm4_generic, R600_RASTERIZER_names}, + { 128, 3, 0x00000000, 0x00000000, 0x0000, 0, "R600_VIEWPORT", 9, r600_state_pm4_generic, R600_VIEWPORT_names}, + { 128, 4, 0x00000000, 0x00000000, 0x0000, 0, "R600_SCISSOR", 19, r600_state_pm4_generic, R600_SCISSOR_names}, + { 128, 5, 0x00000000, 0x00000000, 0x0000, 0, "R600_BLEND", 13, r600_state_pm4_generic, R600_BLEND_names}, + { 128, 6, 0x00000000, 0x00000000, 0x0000, 0, "R600_DSA", 16, r600_state_pm4_generic, R600_DSA_names}, + { 128, 7, 0x00000000, 0x00000000, 0x0000, 0, "R600_VS_SHADER", 49, r600_state_pm4_shader, R600_VS_SHADER_names}, + { 128, 8, 0x00000000, 0x00000000, 0x0000, 0, "R600_PS_SHADER", 39, r600_state_pm4_shader, R600_PS_SHADER_names}, + { 128, 9, 0x00030000, 0x00031000, 0x0010, 0, "R600_PS_CONSTANT", 4, r600_state_pm4_generic, R600_PS_CONSTANT_names}, + { 128, 265, 0x00031000, 0x00032000, 0x0010, 0, "R600_VS_CONSTANT", 4, r600_state_pm4_generic, R600_VS_CONSTANT_names}, + { 128, 521, 0x00038000, 0x00039180, 0x001C, 0, "R600_PS_RESOURCE", 7, r600_state_pm4_resource, R600_PS_RESOURCE_names}, + { 128, 681, 0x00039180, 0x0003A300, 0x001C, 0, "R600_VS_RESOURCE", 7, r600_state_pm4_resource, R600_VS_RESOURCE_names}, + { 128, 841, 0x00039180, 0x0003A300, 0x001C, 0, "R600_FS_RESOURCE", 7, r600_state_pm4_resource, R600_FS_RESOURCE_names}, + { 128, 1001, 0x00039180, 0x0003A300, 0x001C, 0, "R600_GS_RESOURCE", 7, r600_state_pm4_resource, R600_GS_RESOURCE_names}, + { 128, 1161, 0x0003C000, 0x0003C0D8, 0x000C, 0, "R600_PS_SAMPLER", 3, r600_state_pm4_generic, R600_PS_SAMPLER_names}, + { 128, 1179, 0x0003C0D8, 0x0003C1B0, 0x000C, 0, "R600_VS_SAMPLER", 3, r600_state_pm4_generic, R600_VS_SAMPLER_names}, + { 128, 1197, 0x0003C1B0, 0x0003C288, 0x000C, 0, "R600_GS_SAMPLER", 3, r600_state_pm4_generic, R600_GS_SAMPLER_names}, + { 128, 1215, 0x0000A400, 0x0000A520, 0x0010, 0, "R600_PS_SAMPLER_BORDER", 4, r600_state_pm4_generic, R600_PS_SAMPLER_BORDER_names}, + { 128, 1233, 0x0000A600, 0x0000A720, 0x0010, 0, "R600_VS_SAMPLER_BORDER", 4, r600_state_pm4_generic, R600_VS_SAMPLER_BORDER_names}, + { 128, 1251, 0x0000A800, 0x0000A920, 0x0010, 0, "R600_GS_SAMPLER_BORDER", 4, r600_state_pm4_generic, R600_GS_SAMPLER_BORDER_names}, + { 128, 1269, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB0", 7, r700_state_pm4_cb0, R600_CB0_names}, + { 128, 1270, 0x00000000, 0x00000000, 0x0000, 0, "R600_DB", 6, r700_state_pm4_db, R600_DB_names}, + { 128, 1271, 0x00000000, 0x00000000, 0x0000, 0, "R600_VGT", 11, r600_state_pm4_vgt, R600_VGT_names}, + { 128, 1272, 0x00000000, 0x00000000, 0x0000, 0, "R600_DRAW", 4, r600_state_pm4_draw, R600_DRAW_names}, +}; + +#endif diff --git a/src/gallium/winsys/drm/r600/core/r600d.h b/src/gallium/winsys/drm/r600/core/r600d.h new file mode 100644 index 00000000000..5d13378627e --- /dev/null +++ b/src/gallium/winsys/drm/r600/core/r600d.h @@ -0,0 +1,2122 @@ +/* + * Copyright 2010 Jerome Glisse <[email protected]> + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Jerome Glisse + */ +#ifndef R600D_H +#define R600D_H + +#define R600_CONFIG_REG_OFFSET 0X00008000 +#define R600_CONFIG_REG_END 0X0000AC00 +#define R600_CONTEXT_REG_OFFSET 0X00028000 +#define R600_CONTEXT_REG_END 0X00029000 +#define R600_ALU_CONST_OFFSET 0X00030000 +#define R600_ALU_CONST_END 0X00032000 +#define R600_RESOURCE_OFFSET 0X00038000 +#define R600_RESOURCE_END 0X0003C000 +#define R600_SAMPLER_OFFSET 0X0003C000 +#define R600_SAMPLER_END 0X0003CFF0 +#define R600_CTL_CONST_OFFSET 0X0003CFF0 +#define R600_CTL_CONST_END 0X0003E200 +#define R600_LOOP_CONST_OFFSET 0X0003E200 +#define R600_LOOP_CONST_END 0X0003E380 +#define R600_BOOL_CONST_OFFSET 0X0003E380 +#define R600_BOOL_CONST_END 0X00040000 + +#define PKT3_NOP 0x10 +#define PKT3_INDIRECT_BUFFER_END 0x17 +#define PKT3_SET_PREDICATION 0x20 +#define PKT3_REG_RMW 0x21 +#define PKT3_COND_EXEC 0x22 +#define PKT3_PRED_EXEC 0x23 +#define PKT3_START_3D_CMDBUF 0x24 +#define PKT3_DRAW_INDEX_2 0x27 +#define PKT3_CONTEXT_CONTROL 0x28 +#define PKT3_DRAW_INDEX_IMMD_BE 0x29 +#define PKT3_INDEX_TYPE 0x2A +#define PKT3_DRAW_INDEX 0x2B +#define PKT3_DRAW_INDEX_AUTO 0x2D +#define PKT3_DRAW_INDEX_IMMD 0x2E +#define PKT3_NUM_INSTANCES 0x2F +#define PKT3_STRMOUT_BUFFER_UPDATE 0x34 +#define PKT3_INDIRECT_BUFFER_MP 0x38 +#define PKT3_MEM_SEMAPHORE 0x39 +#define PKT3_MPEG_INDEX 0x3A +#define PKT3_WAIT_REG_MEM 0x3C +#define PKT3_MEM_WRITE 0x3D +#define PKT3_INDIRECT_BUFFER 0x32 +#define PKT3_CP_INTERRUPT 0x40 +#define PKT3_SURFACE_SYNC 0x43 +#define PKT3_ME_INITIALIZE 0x44 +#define PKT3_COND_WRITE 0x45 +#define PKT3_EVENT_WRITE 0x46 +#define PKT3_EVENT_WRITE_EOP 0x47 +#define PKT3_ONE_REG_WRITE 0x57 +#define PKT3_SET_CONFIG_REG 0x68 +#define PKT3_SET_CONTEXT_REG 0x69 +#define PKT3_SET_ALU_CONST 0x6A +#define PKT3_SET_BOOL_CONST 0x6B +#define PKT3_SET_LOOP_CONST 0x6C +#define PKT3_SET_RESOURCE 0x6D +#define PKT3_SET_SAMPLER 0x6E +#define PKT3_SET_CTL_CONST 0x6F +#define PKT3_SURFACE_BASE_UPDATE 0x73 + +#define PKT_TYPE_S(x) (((x) & 0x3) << 30) +#define PKT_TYPE_G(x) (((x) >> 30) & 0x3) +#define PKT_TYPE_C 0x3FFFFFFF +#define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16) +#define PKT_COUNT_G(x) (((x) >> 16) & 0x3FFF) +#define PKT_COUNT_C 0xC000FFFF +#define PKT0_BASE_INDEX_S(x) (((x) & 0xFFFF) << 0) +#define PKT0_BASE_INDEX_G(x) (((x) >> 0) & 0xFFFF) +#define PKT0_BASE_INDEX_C 0xFFFF0000 +#define PKT3_IT_OPCODE_S(x) (((x) & 0xFF) << 8) +#define PKT3_IT_OPCODE_G(x) (((x) >> 8) & 0xFF) +#define PKT3_IT_OPCODE_C 0xFFFF00FF +#define PKT0(index, count) (PKT_TYPE_S(0) | PKT0_BASE_INDEX_S(index) | PKT_COUNT_S(count)) +#define PKT3(op, count) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count)) + +/* Registers */ +#define R_0280A0_CB_COLOR0_INFO 0x0280A0 +#define S_0280A0_ENDIAN(x) (((x) & 0x3) << 0) +#define G_0280A0_ENDIAN(x) (((x) >> 0) & 0x3) +#define C_0280A0_ENDIAN 0xFFFFFFFC +#define S_0280A0_FORMAT(x) (((x) & 0x3F) << 2) +#define G_0280A0_FORMAT(x) (((x) >> 2) & 0x3F) +#define C_0280A0_FORMAT 0xFFFFFF03 +#define V_0280A0_COLOR_INVALID 0x00000000 +#define V_0280A0_COLOR_8 0x00000001 +#define V_0280A0_COLOR_4_4 0x00000002 +#define V_0280A0_COLOR_3_3_2 0x00000003 +#define V_0280A0_COLOR_16 0x00000005 +#define V_0280A0_COLOR_16_FLOAT 0x00000006 +#define V_0280A0_COLOR_8_8 0x00000007 +#define V_0280A0_COLOR_5_6_5 0x00000008 +#define V_0280A0_COLOR_6_5_5 0x00000009 +#define V_0280A0_COLOR_1_5_5_5 0x0000000A +#define V_0280A0_COLOR_4_4_4_4 0x0000000B +#define V_0280A0_COLOR_5_5_5_1 0x0000000C +#define V_0280A0_COLOR_32 0x0000000D +#define V_0280A0_COLOR_32_FLOAT 0x0000000E +#define V_0280A0_COLOR_16_16 0x0000000F +#define V_0280A0_COLOR_16_16_FLOAT 0x00000010 +#define V_0280A0_COLOR_8_24 0x00000011 +#define V_0280A0_COLOR_8_24_FLOAT 0x00000012 +#define V_0280A0_COLOR_24_8 0x00000013 +#define V_0280A0_COLOR_24_8_FLOAT 0x00000014 +#define V_0280A0_COLOR_10_11_11 0x00000015 +#define V_0280A0_COLOR_10_11_11_FLOAT 0x00000016 +#define V_0280A0_COLOR_11_11_10 0x00000017 +#define V_0280A0_COLOR_11_11_10_FLOAT 0x00000018 +#define V_0280A0_COLOR_2_10_10_10 0x00000019 +#define V_0280A0_COLOR_8_8_8_8 0x0000001A +#define V_0280A0_COLOR_10_10_10_2 0x0000001B +#define V_0280A0_COLOR_X24_8_32_FLOAT 0x0000001C +#define V_0280A0_COLOR_32_32 0x0000001D +#define V_0280A0_COLOR_32_32_FLOAT 0x0000001E +#define V_0280A0_COLOR_16_16_16_16 0x0000001F +#define V_0280A0_COLOR_16_16_16_16_FLOAT 0x00000020 +#define V_0280A0_COLOR_32_32_32_32 0x00000022 +#define V_0280A0_COLOR_32_32_32_32_FLOAT 0x00000023 +#define S_0280A0_ARRAY_MODE(x) (((x) & 0xF) << 8) +#define G_0280A0_ARRAY_MODE(x) (((x) >> 8) & 0xF) +#define C_0280A0_ARRAY_MODE 0xFFFFF0FF +#define V_0280A0_ARRAY_LINEAR_GENERAL 0x00000000 +#define V_0280A0_ARRAY_LINEAR_ALIGNED 0x00000001 +#define V_0280A0_ARRAY_1D_TILED_THIN1 0x00000002 +#define V_0280A0_ARRAY_2D_TILED_THIN1 0x00000004 +#define S_0280A0_NUMBER_TYPE(x) (((x) & 0x7) << 12) +#define G_0280A0_NUMBER_TYPE(x) (((x) >> 12) & 0x7) +#define C_0280A0_NUMBER_TYPE 0xFFFF8FFF +#define S_0280A0_READ_SIZE(x) (((x) & 0x1) << 15) +#define G_0280A0_READ_SIZE(x) (((x) >> 15) & 0x1) +#define C_0280A0_READ_SIZE 0xFFFF7FFF +#define S_0280A0_COMP_SWAP(x) (((x) & 0x3) << 16) +#define G_0280A0_COMP_SWAP(x) (((x) >> 16) & 0x3) +#define C_0280A0_COMP_SWAP 0xFFFCFFFF +#define S_0280A0_TILE_MODE(x) (((x) & 0x3) << 18) +#define G_0280A0_TILE_MODE(x) (((x) >> 18) & 0x3) +#define C_0280A0_TILE_MODE 0xFFF3FFFF +#define S_0280A0_BLEND_CLAMP(x) (((x) & 0x1) << 20) +#define G_0280A0_BLEND_CLAMP(x) (((x) >> 20) & 0x1) +#define C_0280A0_BLEND_CLAMP 0xFFEFFFFF +#define S_0280A0_CLEAR_COLOR(x) (((x) & 0x1) << 21) +#define G_0280A0_CLEAR_COLOR(x) (((x) >> 21) & 0x1) +#define C_0280A0_CLEAR_COLOR 0xFFDFFFFF +#define S_0280A0_BLEND_BYPASS(x) (((x) & 0x1) << 22) +#define G_0280A0_BLEND_BYPASS(x) (((x) >> 22) & 0x1) +#define C_0280A0_BLEND_BYPASS 0xFFBFFFFF +#define S_0280A0_BLEND_FLOAT32(x) (((x) & 0x1) << 23) +#define G_0280A0_BLEND_FLOAT32(x) (((x) >> 23) & 0x1) +#define C_0280A0_BLEND_FLOAT32 0xFF7FFFFF +#define S_0280A0_SIMPLE_FLOAT(x) (((x) & 0x1) << 24) +#define G_0280A0_SIMPLE_FLOAT(x) (((x) >> 24) & 0x1) +#define C_0280A0_SIMPLE_FLOAT 0xFEFFFFFF +#define S_0280A0_ROUND_MODE(x) (((x) & 0x1) << 25) +#define G_0280A0_ROUND_MODE(x) (((x) >> 25) & 0x1) +#define C_0280A0_ROUND_MODE 0xFDFFFFFF +#define S_0280A0_TILE_COMPACT(x) (((x) & 0x1) << 26) +#define G_0280A0_TILE_COMPACT(x) (((x) >> 26) & 0x1) +#define C_0280A0_TILE_COMPACT 0xFBFFFFFF +#define S_0280A0_SOURCE_FORMAT(x) (((x) & 0x1) << 27) +#define G_0280A0_SOURCE_FORMAT(x) (((x) >> 27) & 0x1) +#define C_0280A0_SOURCE_FORMAT 0xF7FFFFFF +#define R_028060_CB_COLOR0_SIZE 0x028060 +#define S_028060_PITCH_TILE_MAX(x) (((x) & 0x3FF) << 0) +#define G_028060_PITCH_TILE_MAX(x) (((x) >> 0) & 0x3FF) +#define C_028060_PITCH_TILE_MAX 0xFFFFFC00 +#define S_028060_SLICE_TILE_MAX(x) (((x) & 0xFFFFF) << 10) +#define G_028060_SLICE_TILE_MAX(x) (((x) >> 10) & 0xFFFFF) +#define C_028060_SLICE_TILE_MAX 0xC00003FF +#define R_028800_DB_DEPTH_CONTROL 0x028800 +#define S_028800_STENCIL_ENABLE(x) (((x) & 0x1) << 0) +#define G_028800_STENCIL_ENABLE(x) (((x) >> 0) & 0x1) +#define C_028800_STENCIL_ENABLE 0xFFFFFFFE +#define S_028800_Z_ENABLE(x) (((x) & 0x1) << 1) +#define G_028800_Z_ENABLE(x) (((x) >> 1) & 0x1) +#define C_028800_Z_ENABLE 0xFFFFFFFD +#define S_028800_Z_WRITE_ENABLE(x) (((x) & 0x1) << 2) +#define G_028800_Z_WRITE_ENABLE(x) (((x) >> 2) & 0x1) +#define C_028800_Z_WRITE_ENABLE 0xFFFFFFFB +#define S_028800_ZFUNC(x) (((x) & 0x7) << 4) +#define G_028800_ZFUNC(x) (((x) >> 4) & 0x7) +#define C_028800_ZFUNC 0xFFFFFF8F +#define S_028800_BACKFACE_ENABLE(x) (((x) & 0x1) << 7) +#define G_028800_BACKFACE_ENABLE(x) (((x) >> 7) & 0x1) +#define C_028800_BACKFACE_ENABLE 0xFFFFFF7F +#define S_028800_STENCILFUNC(x) (((x) & 0x7) << 8) +#define G_028800_STENCILFUNC(x) (((x) >> 8) & 0x7) +#define C_028800_STENCILFUNC 0xFFFFF8FF +#define S_028800_STENCILFAIL(x) (((x) & 0x7) << 11) +#define G_028800_STENCILFAIL(x) (((x) >> 11) & 0x7) +#define C_028800_STENCILFAIL 0xFFFFC7FF +#define S_028800_STENCILZPASS(x) (((x) & 0x7) << 14) +#define G_028800_STENCILZPASS(x) (((x) >> 14) & 0x7) +#define C_028800_STENCILZPASS 0xFFFE3FFF +#define S_028800_STENCILZFAIL(x) (((x) & 0x7) << 17) +#define G_028800_STENCILZFAIL(x) (((x) >> 17) & 0x7) +#define C_028800_STENCILZFAIL 0xFFF1FFFF +#define S_028800_STENCILFUNC_BF(x) (((x) & 0x7) << 20) +#define G_028800_STENCILFUNC_BF(x) (((x) >> 20) & 0x7) +#define C_028800_STENCILFUNC_BF 0xFF8FFFFF +#define S_028800_STENCILFAIL_BF(x) (((x) & 0x7) << 23) +#define G_028800_STENCILFAIL_BF(x) (((x) >> 23) & 0x7) +#define C_028800_STENCILFAIL_BF 0xFC7FFFFF +#define S_028800_STENCILZPASS_BF(x) (((x) & 0x7) << 26) +#define G_028800_STENCILZPASS_BF(x) (((x) >> 26) & 0x7) +#define C_028800_STENCILZPASS_BF 0xE3FFFFFF +#define S_028800_STENCILZFAIL_BF(x) (((x) & 0x7) << 29) +#define G_028800_STENCILZFAIL_BF(x) (((x) >> 29) & 0x7) +#define C_028800_STENCILZFAIL_BF 0x1FFFFFFF +#define R_028010_DB_DEPTH_INFO 0x028010 +#define S_028010_FORMAT(x) (((x) & 0x7) << 0) +#define G_028010_FORMAT(x) (((x) >> 0) & 0x7) +#define C_028010_FORMAT 0xFFFFFFF8 +#define V_028010_DEPTH_INVALID 0x00000000 +#define V_028010_DEPTH_16 0x00000001 +#define V_028010_DEPTH_X8_24 0x00000002 +#define V_028010_DEPTH_8_24 0x00000003 +#define V_028010_DEPTH_X8_24_FLOAT 0x00000004 +#define V_028010_DEPTH_8_24_FLOAT 0x00000005 +#define V_028010_DEPTH_32_FLOAT 0x00000006 +#define V_028010_DEPTH_X24_8_32_FLOAT 0x00000007 +#define S_028010_READ_SIZE(x) (((x) & 0x1) << 3) +#define G_028010_READ_SIZE(x) (((x) >> 3) & 0x1) +#define C_028010_READ_SIZE 0xFFFFFFF7 +#define S_028010_ARRAY_MODE(x) (((x) & 0xF) << 15) +#define G_028010_ARRAY_MODE(x) (((x) >> 15) & 0xF) +#define C_028010_ARRAY_MODE 0xFFF87FFF +#define S_028010_TILE_SURFACE_ENABLE(x) (((x) & 0x1) << 25) +#define G_028010_TILE_SURFACE_ENABLE(x) (((x) >> 25) & 0x1) +#define C_028010_TILE_SURFACE_ENABLE 0xFDFFFFFF +#define S_028010_TILE_COMPACT(x) (((x) & 0x1) << 26) +#define G_028010_TILE_COMPACT(x) (((x) >> 26) & 0x1) +#define C_028010_TILE_COMPACT 0xFBFFFFFF +#define S_028010_ZRANGE_PRECISION(x) (((x) & 0x1) << 31) +#define G_028010_ZRANGE_PRECISION(x) (((x) >> 31) & 0x1) +#define C_028010_ZRANGE_PRECISION 0x7FFFFFFF +#define R_028000_DB_DEPTH_SIZE 0x028000 +#define S_028000_PITCH_TILE_MAX(x) (((x) & 0x3FF) << 0) +#define G_028000_PITCH_TILE_MAX(x) (((x) >> 0) & 0x3FF) +#define C_028000_PITCH_TILE_MAX 0xFFFFFC00 +#define S_028000_SLICE_TILE_MAX(x) (((x) & 0xFFFFF) << 10) +#define G_028000_SLICE_TILE_MAX(x) (((x) >> 10) & 0xFFFFF) +#define C_028000_SLICE_TILE_MAX 0xC00003FF +#define R_028004_DB_DEPTH_VIEW 0x028004 +#define S_028004_SLICE_START(x) (((x) & 0x7FF) << 0) +#define G_028004_SLICE_START(x) (((x) >> 0) & 0x7FF) +#define C_028004_SLICE_START 0xFFFFF800 +#define S_028004_SLICE_MAX(x) (((x) & 0x7FF) << 13) +#define G_028004_SLICE_MAX(x) (((x) >> 13) & 0x7FF) +#define C_028004_SLICE_MAX 0xFF001FFF +#define R_028D24_DB_HTILE_SURFACE 0x028D24 +#define S_028D24_HTILE_WIDTH(x) (((x) & 0x1) << 0) +#define G_028D24_HTILE_WIDTH(x) (((x) >> 0) & 0x1) +#define C_028D24_HTILE_WIDTH 0xFFFFFFFE +#define S_028D24_HTILE_HEIGHT(x) (((x) & 0x1) << 1) +#define G_028D24_HTILE_HEIGHT(x) (((x) >> 1) & 0x1) +#define C_028D24_HTILE_HEIGHT 0xFFFFFFFD +#define S_028D24_LINEAR(x) (((x) & 0x1) << 2) +#define G_028D24_LINEAR(x) (((x) >> 2) & 0x1) +#define C_028D24_LINEAR 0xFFFFFFFB +#define S_028D24_FULL_CACHE(x) (((x) & 0x1) << 3) +#define G_028D24_FULL_CACHE(x) (((x) >> 3) & 0x1) +#define C_028D24_FULL_CACHE 0xFFFFFFF7 +#define S_028D24_HTILE_USES_PRELOAD_WIN(x) (((x) & 0x1) << 4) +#define G_028D24_HTILE_USES_PRELOAD_WIN(x) (((x) >> 4) & 0x1) +#define C_028D24_HTILE_USES_PRELOAD_WIN 0xFFFFFFEF +#define S_028D24_PRELOAD(x) (((x) & 0x1) << 5) +#define G_028D24_PRELOAD(x) (((x) >> 5) & 0x1) +#define C_028D24_PRELOAD 0xFFFFFFDF +#define S_028D24_PREFETCH_WIDTH(x) (((x) & 0x3F) << 6) +#define G_028D24_PREFETCH_WIDTH(x) (((x) >> 6) & 0x3F) +#define C_028D24_PREFETCH_WIDTH 0xFFFFF03F +#define S_028D24_PREFETCH_HEIGHT(x) (((x) & 0x3F) << 12) +#define G_028D24_PREFETCH_HEIGHT(x) (((x) >> 12) & 0x3F) +#define C_028D24_PREFETCH_HEIGHT 0xFFFC0FFF +#define R_028D34_DB_PREFETCH_LIMIT 0x028D34 +#define S_028D34_DEPTH_HEIGHT_TILE_MAX(x) (((x) & 0x3FF) << 0) +#define G_028D34_DEPTH_HEIGHT_TILE_MAX(x) (((x) >> 0) & 0x3FF) +#define C_028D34_DEPTH_HEIGHT_TILE_MAX 0xFFFFFC00 +#define R_028D10_DB_RENDER_OVERRIDE 0x028D10 +#define S_028D10_FORCE_HIZ_ENABLE(x) (((x) & 0x3) << 0) +#define G_028D10_FORCE_HIZ_ENABLE(x) (((x) >> 0) & 0x3) +#define C_028D10_FORCE_HIZ_ENABLE 0xFFFFFFFC +#define S_028D10_FORCE_HIS_ENABLE0(x) (((x) & 0x3) << 2) +#define G_028D10_FORCE_HIS_ENABLE0(x) (((x) >> 2) & 0x3) +#define C_028D10_FORCE_HIS_ENABLE0 0xFFFFFFF3 +#define S_028D10_FORCE_HIS_ENABLE1(x) (((x) & 0x3) << 4) +#define G_028D10_FORCE_HIS_ENABLE1(x) (((x) >> 4) & 0x3) +#define C_028D10_FORCE_HIS_ENABLE1 0xFFFFFFCF +#define S_028D10_FORCE_SHADER_Z_ORDER(x) (((x) & 0x1) << 6) +#define G_028D10_FORCE_SHADER_Z_ORDER(x) (((x) >> 6) & 0x1) +#define C_028D10_FORCE_SHADER_Z_ORDER 0xFFFFFFBF +#define S_028D10_FAST_Z_DISABLE(x) (((x) & 0x1) << 7) +#define G_028D10_FAST_Z_DISABLE(x) (((x) >> 7) & 0x1) +#define C_028D10_FAST_Z_DISABLE 0xFFFFFF7F +#define S_028D10_FAST_STENCIL_DISABLE(x) (((x) & 0x1) << 8) +#define G_028D10_FAST_STENCIL_DISABLE(x) (((x) >> 8) & 0x1) +#define C_028D10_FAST_STENCIL_DISABLE 0xFFFFFEFF +#define S_028D10_NOOP_CULL_DISABLE(x) (((x) & 0x1) << 9) +#define G_028D10_NOOP_CULL_DISABLE(x) (((x) >> 9) & 0x1) +#define C_028D10_NOOP_CULL_DISABLE 0xFFFFFDFF +#define S_028D10_FORCE_COLOR_KILL(x) (((x) & 0x1) << 10) +#define G_028D10_FORCE_COLOR_KILL(x) (((x) >> 10) & 0x1) +#define C_028D10_FORCE_COLOR_KILL 0xFFFFFBFF +#define S_028D10_FORCE_Z_READ(x) (((x) & 0x1) << 11) +#define G_028D10_FORCE_Z_READ(x) (((x) >> 11) & 0x1) +#define C_028D10_FORCE_Z_READ 0xFFFFF7FF +#define S_028D10_FORCE_STENCIL_READ(x) (((x) & 0x1) << 12) +#define G_028D10_FORCE_STENCIL_READ(x) (((x) >> 12) & 0x1) +#define C_028D10_FORCE_STENCIL_READ 0xFFFFEFFF +#define S_028D10_FORCE_FULL_Z_RANGE(x) (((x) & 0x3) << 13) +#define G_028D10_FORCE_FULL_Z_RANGE(x) (((x) >> 13) & 0x3) +#define C_028D10_FORCE_FULL_Z_RANGE 0xFFFF9FFF +#define S_028D10_FORCE_QC_SMASK_CONFLICT(x) (((x) & 0x1) << 15) +#define G_028D10_FORCE_QC_SMASK_CONFLICT(x) (((x) >> 15) & 0x1) +#define C_028D10_FORCE_QC_SMASK_CONFLICT 0xFFFF7FFF +#define S_028D10_DISABLE_VIEWPORT_CLAMP(x) (((x) & 0x1) << 16) +#define G_028D10_DISABLE_VIEWPORT_CLAMP(x) (((x) >> 16) & 0x1) +#define C_028D10_DISABLE_VIEWPORT_CLAMP 0xFFFEFFFF +#define S_028D10_IGNORE_SC_ZRANGE(x) (((x) & 0x1) << 17) +#define G_028D10_IGNORE_SC_ZRANGE(x) (((x) >> 17) & 0x1) +#define C_028D10_IGNORE_SC_ZRANGE 0xFFFDFFFF +#define R_028A40_VGT_GS_MODE 0x028A40 +#define S_028A40_MODE(x) (((x) & 0x3) << 0) +#define G_028A40_MODE(x) (((x) >> 0) & 0x3) +#define C_028A40_MODE 0xFFFFFFFC +#define S_028A40_ES_PASSTHRU(x) (((x) & 0x1) << 2) +#define G_028A40_ES_PASSTHRU(x) (((x) >> 2) & 0x1) +#define C_028A40_ES_PASSTHRU 0xFFFFFFFB +#define S_028A40_CUT_MODE(x) (((x) & 0x3) << 3) +#define G_028A40_CUT_MODE(x) (((x) >> 3) & 0x3) +#define C_028A40_CUT_MODE 0xFFFFFFE7 +#define R_008DFC_SQ_CF_WORD0 0x008DFC +#define S_008DFC_ADDR(x) (((x) & 0xFFFFFFFF) << 0) +#define G_008DFC_ADDR(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_008DFC_ADDR 0x00000000 +#define R_008DFC_SQ_CF_WORD1 0x008DFC +#define S_008DFC_POP_COUNT(x) (((x) & 0x7) << 0) +#define G_008DFC_POP_COUNT(x) (((x) >> 0) & 0x7) +#define C_008DFC_POP_COUNT 0xFFFFFFF8 +#define S_008DFC_CF_CONST(x) (((x) & 0x1F) << 3) +#define G_008DFC_CF_CONST(x) (((x) >> 3) & 0x1F) +#define C_008DFC_CF_CONST 0xFFFFFF07 +#define S_008DFC_COND(x) (((x) & 0x3) << 8) +#define G_008DFC_COND(x) (((x) >> 8) & 0x3) +#define C_008DFC_COND 0xFFFFFCFF +#define S_008DFC_COUNT(x) (((x) & 0x7) << 10) +#define G_008DFC_COUNT(x) (((x) >> 10) & 0x7) +#define C_008DFC_COUNT 0xFFFFE3FF +#define S_008DFC_CALL_COUNT(x) (((x) & 0x3F) << 13) +#define G_008DFC_CALL_COUNT(x) (((x) >> 13) & 0x3F) +#define C_008DFC_CALL_COUNT 0xFFF81FFF +#define S_008DFC_END_OF_PROGRAM(x) (((x) & 0x1) << 21) +#define G_008DFC_END_OF_PROGRAM(x) (((x) >> 21) & 0x1) +#define C_008DFC_END_OF_PROGRAM 0xFFDFFFFF +#define S_008DFC_VALID_PIXEL_MODE(x) (((x) & 0x1) << 22) +#define G_008DFC_VALID_PIXEL_MODE(x) (((x) >> 22) & 0x1) +#define C_008DFC_VALID_PIXEL_MODE 0xFFBFFFFF +#define S_008DFC_CF_INST(x) (((x) & 0x7F) << 23) +#define G_008DFC_CF_INST(x) (((x) >> 23) & 0x7F) +#define C_008DFC_CF_INST 0xC07FFFFF +#define V_008DFC_SQ_CF_INST_NOP 0x00000000 +#define V_008DFC_SQ_CF_INST_TEX 0x00000001 +#define V_008DFC_SQ_CF_INST_VTX 0x00000002 +#define V_008DFC_SQ_CF_INST_VTX_TC 0x00000003 +#define V_008DFC_SQ_CF_INST_LOOP_START 0x00000004 +#define V_008DFC_SQ_CF_INST_LOOP_END 0x00000005 +#define V_008DFC_SQ_CF_INST_LOOP_START_DX10 0x00000006 +#define V_008DFC_SQ_CF_INST_LOOP_START_NO_AL 0x00000007 +#define V_008DFC_SQ_CF_INST_LOOP_CONTINUE 0x00000008 +#define V_008DFC_SQ_CF_INST_LOOP_BREAK 0x00000009 +#define V_008DFC_SQ_CF_INST_JUMP 0x0000000A +#define V_008DFC_SQ_CF_INST_PUSH 0x0000000B +#define V_008DFC_SQ_CF_INST_PUSH_ELSE 0x0000000C +#define V_008DFC_SQ_CF_INST_ELSE 0x0000000D +#define V_008DFC_SQ_CF_INST_POP 0x0000000E +#define V_008DFC_SQ_CF_INST_POP_JUMP 0x0000000F +#define V_008DFC_SQ_CF_INST_POP_PUSH 0x00000010 +#define V_008DFC_SQ_CF_INST_POP_PUSH_ELSE 0x00000011 +#define V_008DFC_SQ_CF_INST_CALL 0x00000012 +#define V_008DFC_SQ_CF_INST_CALL_FS 0x00000013 +#define V_008DFC_SQ_CF_INST_RETURN 0x00000014 +#define V_008DFC_SQ_CF_INST_EMIT_VERTEX 0x00000015 +#define V_008DFC_SQ_CF_INST_EMIT_CUT_VERTEX 0x00000016 +#define V_008DFC_SQ_CF_INST_CUT_VERTEX 0x00000017 +#define V_008DFC_SQ_CF_INST_KILL 0x00000018 +#define S_008DFC_WHOLE_QUAD_MODE(x) (((x) & 0x1) << 30) +#define G_008DFC_WHOLE_QUAD_MODE(x) (((x) >> 30) & 0x1) +#define C_008DFC_WHOLE_QUAD_MODE 0xBFFFFFFF +#define S_008DFC_BARRIER(x) (((x) & 0x1) << 31) +#define G_008DFC_BARRIER(x) (((x) >> 31) & 0x1) +#define C_008DFC_BARRIER 0x7FFFFFFF +#define R_008DFC_SQ_CF_ALU_WORD0 0x008DFC +#define S_008DFC_ALU_ADDR(x) (((x) & 0x3FFFFF) << 0) +#define G_008DFC_ALU_ADDR(x) (((x) >> 0) & 0x3FFFFF) +#define C_008DFC_ALU_ADDR 0xFFC00000 +#define S_008DFC_KCACHE_BANK0(x) (((x) & 0xF) << 22) +#define G_008DFC_KCACHE_BANK0(x) (((x) >> 22) & 0xF) +#define C_008DFC_KCACHE_BANK0 0xFC3FFFFF +#define S_008DFC_KCACHE_BANK1(x) (((x) & 0xF) << 26) +#define G_008DFC_KCACHE_BANK1(x) (((x) >> 26) & 0xF) +#define C_008DFC_KCACHE_BANK1 0xC3FFFFFF +#define S_008DFC_KCACHE_MODE0(x) (((x) & 0x3) << 30) +#define G_008DFC_KCACHE_MODE0(x) (((x) >> 30) & 0x3) +#define C_008DFC_KCACHE_MODE0 0x3FFFFFFF +#define R_008DFC_SQ_CF_ALU_WORD1 0x008DFC +#define S_008DFC_KCACHE_MODE1(x) (((x) & 0x3) << 0) +#define G_008DFC_KCACHE_MODE1(x) (((x) >> 0) & 0x3) +#define C_008DFC_KCACHE_MODE1 0xFFFFFFFC +#define S_008DFC_KCACHE_ADDR0(x) (((x) & 0xFF) << 2) +#define G_008DFC_KCACHE_ADDR0(x) (((x) >> 2) & 0xFF) +#define C_008DFC_KCACHE_ADDR0 0xFFFFFC03 +#define S_008DFC_KCACHE_ADDR1(x) (((x) & 0xFF) << 10) +#define G_008DFC_KCACHE_ADDR1(x) (((x) >> 10) & 0xFF) +#define C_008DFC_KCACHE_ADDR1 0xFFFC03FF +#define S_008DFC_ALU_COUNT(x) (((x) & 0x7F) << 18) +#define G_008DFC_ALU_COUNT(x) (((x) >> 18) & 0x7F) +#define C_008DFC_ALU_COUNT 0xFE03FFFF +#define S_008DFC_USES_WATERFALL(x) (((x) & 0x1) << 25) +#define G_008DFC_USES_WATERFALL(x) (((x) >> 25) & 0x1) +#define C_008DFC_USES_WATERFALL 0xFDFFFFFF +#define S_008DFC_CF_ALU_INST(x) (((x) & 0xF) << 26) +#define G_008DFC_CF_ALU_INST(x) (((x) >> 26) & 0xF) +#define C_008DFC_CF_ALU_INST 0xC3FFFFFF +#define V_008DFC_SQ_CF_INST_ALU 0x00000008 +#define V_008DFC_SQ_CF_INST_ALU_PUSH_BEFORE 0x00000009 +#define V_008DFC_SQ_CF_INST_ALU_POP_AFTER 0x0000000A +#define V_008DFC_SQ_CF_INST_ALU_POP2_AFTER 0x0000000B +#define V_008DFC_SQ_CF_INST_ALU_CONTINUE 0x0000000D +#define V_008DFC_SQ_CF_INST_ALU_BREAK 0x0000000E +#define V_008DFC_SQ_CF_INST_ALU_ELSE_AFTER 0x0000000F +#define S_008DFC_WHOLE_QUAD_MODE(x) (((x) & 0x1) << 30) +#define G_008DFC_WHOLE_QUAD_MODE(x) (((x) >> 30) & 0x1) +#define C_008DFC_WHOLE_QUAD_MODE 0xBFFFFFFF +#define S_008DFC_BARRIER(x) (((x) & 0x1) << 31) +#define G_008DFC_BARRIER(x) (((x) >> 31) & 0x1) +#define C_008DFC_BARRIER 0x7FFFFFFF +#define R_008DFC_SQ_CF_ALLOC_EXPORT_WORD0 0x008DFC +#define S_008DFC_ARRAY_BASE(x) (((x) & 0x1FFF) << 0) +#define G_008DFC_ARRAY_BASE(x) (((x) >> 0) & 0x1FFF) +#define C_008DFC_ARRAY_BASE 0xFFFFE000 +#define S_008DFC_TYPE(x) (((x) & 0x3) << 13) +#define G_008DFC_TYPE(x) (((x) >> 13) & 0x3) +#define C_008DFC_TYPE 0xFFFF9FFF +#define S_008DFC_RW_GPR(x) (((x) & 0x7F) << 15) +#define G_008DFC_RW_GPR(x) (((x) >> 15) & 0x7F) +#define C_008DFC_RW_GPR 0xFFC07FFF +#define S_008DFC_RW_REL(x) (((x) & 0x1) << 22) +#define G_008DFC_RW_REL(x) (((x) >> 22) & 0x1) +#define C_008DFC_RW_REL 0xFFBFFFFF +#define S_008DFC_INDEX_GPR(x) (((x) & 0x7F) << 23) +#define G_008DFC_INDEX_GPR(x) (((x) >> 23) & 0x7F) +#define C_008DFC_INDEX_GPR 0xC07FFFFF +#define S_008DFC_ELEM_SIZE(x) (((x) & 0x3) << 30) +#define G_008DFC_ELEM_SIZE(x) (((x) >> 30) & 0x3) +#define C_008DFC_ELEM_SIZE 0x3FFFFFFF +#define R_008DFC_SQ_CF_ALLOC_EXPORT_WORD1 0x008DFC +#define S_008DFC_BURST_COUNT(x) (((x) & 0xF) << 17) +#define G_008DFC_BURST_COUNT(x) (((x) >> 17) & 0xF) +#define C_008DFC_BURST_COUNT 0xFFE1FFFF +#define S_008DFC_END_OF_PROGRAM(x) (((x) & 0x1) << 21) +#define G_008DFC_END_OF_PROGRAM(x) (((x) >> 21) & 0x1) +#define C_008DFC_END_OF_PROGRAM 0xFFDFFFFF +#define S_008DFC_VALID_PIXEL_MODE(x) (((x) & 0x1) << 22) +#define G_008DFC_VALID_PIXEL_MODE(x) (((x) >> 22) & 0x1) +#define C_008DFC_VALID_PIXEL_MODE 0xFFBFFFFF +#define S_008DFC_CF_INST(x) (((x) & 0x7F) << 23) +#define G_008DFC_CF_INST(x) (((x) >> 23) & 0x7F) +#define C_008DFC_CF_INST 0xC07FFFFF +#define V_008DFC_SQ_CF_INST_MEM_STREAM0 0x00000020 +#define V_008DFC_SQ_CF_INST_MEM_STREAM1 0x00000021 +#define V_008DFC_SQ_CF_INST_MEM_STREAM2 0x00000022 +#define V_008DFC_SQ_CF_INST_MEM_STREAM3 0x00000023 +#define V_008DFC_SQ_CF_INST_MEM_SCRATCH 0x00000024 +#define V_008DFC_SQ_CF_INST_MEM_REDUCTION 0x00000025 +#define V_008DFC_SQ_CF_INST_MEM_RING 0x00000026 +#define V_008DFC_SQ_CF_INST_EXPORT 0x00000027 +#define V_008DFC_SQ_CF_INST_EXPORT_DONE 0x00000028 +#define S_008DFC_WHOLE_QUAD_MODE(x) (((x) & 0x1) << 30) +#define G_008DFC_WHOLE_QUAD_MODE(x) (((x) >> 30) & 0x1) +#define C_008DFC_WHOLE_QUAD_MODE 0xBFFFFFFF +#define S_008DFC_BARRIER(x) (((x) & 0x1) << 31) +#define G_008DFC_BARRIER(x) (((x) >> 31) & 0x1) +#define C_008DFC_BARRIER 0x7FFFFFFF +#define R_008DFC_SQ_CF_ALLOC_EXPORT_WORD1_BUF 0x008DFC +#define S_008DFC_ARRAY_SIZE(x) (((x) & 0xFFF) << 0) +#define G_008DFC_ARRAY_SIZE(x) (((x) >> 0) & 0xFFF) +#define C_008DFC_ARRAY_SIZE 0xFFFFF000 +#define S_008DFC_COMP_MASK(x) (((x) & 0xF) << 12) +#define G_008DFC_COMP_MASK(x) (((x) >> 12) & 0xF) +#define C_008DFC_COMP_MASK 0xFFFF0FFF +#define R_008DFC_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ 0x008DFC +#define S_008DFC_SEL_X(x) (((x) & 0x7) << 0) +#define G_008DFC_SEL_X(x) (((x) >> 0) & 0x7) +#define C_008DFC_SEL_X 0xFFFFFFF8 +#define S_008DFC_SEL_Y(x) (((x) & 0x7) << 3) +#define G_008DFC_SEL_Y(x) (((x) >> 3) & 0x7) +#define C_008DFC_SEL_Y 0xFFFFFFC7 +#define S_008DFC_SEL_Z(x) (((x) & 0x7) << 6) +#define G_008DFC_SEL_Z(x) (((x) >> 6) & 0x7) +#define C_008DFC_SEL_Z 0xFFFFFE3F +#define S_008DFC_SEL_W(x) (((x) & 0x7) << 9) +#define G_008DFC_SEL_W(x) (((x) >> 9) & 0x7) +#define C_008DFC_SEL_W 0xFFFFF1FF +#define R_008DFC_SQ_VTX_WORD0 0x008DFC +#define S_008DFC_VTX_INST(x) (((x) & 0x1F) << 0) +#define G_008DFC_VTX_INST(x) (((x) >> 0) & 0x1F) +#define C_008DFC_VTX_INST 0xFFFFFFE0 +#define S_008DFC_FETCH_TYPE(x) (((x) & 0x3) << 5) +#define G_008DFC_FETCH_TYPE(x) (((x) >> 5) & 0x3) +#define C_008DFC_FETCH_TYPE 0xFFFFFF9F +#define S_008DFC_FETCH_WHOLE_QUAD(x) (((x) & 0x1) << 7) +#define G_008DFC_FETCH_WHOLE_QUAD(x) (((x) >> 7) & 0x1) +#define C_008DFC_FETCH_WHOLE_QUAD 0xFFFFFF7F +#define S_008DFC_BUFFER_ID(x) (((x) & 0xFF) << 8) +#define G_008DFC_BUFFER_ID(x) (((x) >> 8) & 0xFF) +#define C_008DFC_BUFFER_ID 0xFFFF00FF +#define S_008DFC_SRC_GPR(x) (((x) & 0x7F) << 16) +#define G_008DFC_SRC_GPR(x) (((x) >> 16) & 0x7F) +#define C_008DFC_SRC_GPR 0xFF80FFFF +#define S_008DFC_SRC_REL(x) (((x) & 0x1) << 23) +#define G_008DFC_SRC_REL(x) (((x) >> 23) & 0x1) +#define C_008DFC_SRC_REL 0xFF7FFFFF +#define S_008DFC_SRC_SEL_X(x) (((x) & 0x3) << 24) +#define G_008DFC_SRC_SEL_X(x) (((x) >> 24) & 0x3) +#define C_008DFC_SRC_SEL_X 0xFCFFFFFF +#define S_008DFC_MEGA_FETCH_COUNT(x) (((x) & 0x3F) << 26) +#define G_008DFC_MEGA_FETCH_COUNT(x) (((x) >> 26) & 0x3F) +#define C_008DFC_MEGA_FETCH_COUNT 0x03FFFFFF +#define R_008DFC_SQ_VTX_WORD1 0x008DFC +#define S_008DFC_DST_SEL_X(x) (((x) & 0x7) << 9) +#define G_008DFC_DST_SEL_X(x) (((x) >> 9) & 0x7) +#define C_008DFC_DST_SEL_X 0xFFFFF1FF +#define S_008DFC_DST_SEL_Y(x) (((x) & 0x7) << 12) +#define G_008DFC_DST_SEL_Y(x) (((x) >> 12) & 0x7) +#define C_008DFC_DST_SEL_Y 0xFFFF8FFF +#define S_008DFC_DST_SEL_Z(x) (((x) & 0x7) << 15) +#define G_008DFC_DST_SEL_Z(x) (((x) >> 15) & 0x7) +#define C_008DFC_DST_SEL_Z 0xFFFC7FFF +#define S_008DFC_DST_SEL_W(x) (((x) & 0x7) << 18) +#define G_008DFC_DST_SEL_W(x) (((x) >> 18) & 0x7) +#define C_008DFC_DST_SEL_W 0xFFE3FFFF +#define S_008DFC_USE_CONST_FIELDS(x) (((x) & 0x1) << 21) +#define G_008DFC_USE_CONST_FIELDS(x) (((x) >> 21) & 0x1) +#define C_008DFC_USE_CONST_FIELDS 0xFFDFFFFF +#define S_008DFC_DATA_FORMAT(x) (((x) & 0x3F) << 22) +#define G_008DFC_DATA_FORMAT(x) (((x) >> 22) & 0x3F) +#define C_008DFC_DATA_FORMAT 0xF03FFFFF +#define S_008DFC_NUM_FORMAT_ALL(x) (((x) & 0x3) << 28) +#define G_008DFC_NUM_FORMAT_ALL(x) (((x) >> 28) & 0x3) +#define C_008DFC_NUM_FORMAT_ALL 0xCFFFFFFF +#define S_008DFC_FORMAT_COMP_ALL(x) (((x) & 0x1) << 30) +#define G_008DFC_FORMAT_COMP_ALL(x) (((x) >> 30) & 0x1) +#define C_008DFC_FORMAT_COMP_ALL 0xBFFFFFFF +#define S_008DFC_SRF_MODE_ALL(x) (((x) & 0x1) << 31) +#define G_008DFC_SRF_MODE_ALL(x) (((x) >> 31) & 0x1) +#define C_008DFC_SRF_MODE_ALL 0x7FFFFFFF +#define R_008DFC_SQ_VTX_WORD1_GPR 0x008DFC +#define S_008DFC_DST_GPR(x) (((x) & 0x7F) << 0) +#define G_008DFC_DST_GPR(x) (((x) >> 0) & 0x7F) +#define C_008DFC_DST_GPR 0xFFFFFF80 +#define S_008DFC_DST_REL(x) (((x) & 0x1) << 7) +#define G_008DFC_DST_REL(x) (((x) >> 7) & 0x1) +#define C_008DFC_DST_REL 0xFFFFFF7F +#define R_008DFC_SQ_VTX_WORD2 0x008DFC +#define S_008DFC_OFFSET(x) (((x) & 0xFFFF) << 0) +#define G_008DFC_OFFSET(x) (((x) >> 0) & 0xFFFF) +#define C_008DFC_OFFSET 0xFFFF0000 +#define S_008DFC_ENDIAN_SWAP(x) (((x) & 0x3) << 16) +#define G_008DFC_ENDIAN_SWAP(x) (((x) >> 16) & 0x3) +#define C_008DFC_ENDIAN_SWAP 0xFFFCFFFF +#define S_008DFC_CONST_BUF_NO_STRIDE(x) (((x) & 0x1) << 18) +#define G_008DFC_CONST_BUF_NO_STRIDE(x) (((x) >> 18) & 0x1) +#define C_008DFC_CONST_BUF_NO_STRIDE 0xFFFBFFFF +#define S_008DFC_MEGA_FETCH(x) (((x) & 0x1) << 19) +#define G_008DFC_MEGA_FETCH(x) (((x) >> 19) & 0x1) +#define C_008DFC_MEGA_FETCH 0xFFF7FFFF +#define S_008DFC_ALT_CONST(x) (((x) & 0x1) << 20) +#define G_008DFC_ALT_CONST(x) (((x) >> 20) & 0x1) +#define C_008DFC_ALT_CONST 0xFFEFFFFF +#define R_008040_WAIT_UNTIL 0x008040 +#define S_008040_WAIT_CP_DMA_IDLE(x) (((x) & 0x1) << 8) +#define G_008040_WAIT_CP_DMA_IDLE(x) (((x) >> 8) & 0x1) +#define C_008040_WAIT_CP_DMA_IDLE 0xFFFFFEFF +#define S_008040_WAIT_CMDFIFO(x) (((x) & 0x1) << 10) +#define G_008040_WAIT_CMDFIFO(x) (((x) >> 10) & 0x1) +#define C_008040_WAIT_CMDFIFO 0xFFFFFBFF +#define S_008040_WAIT_2D_IDLE(x) (((x) & 0x1) << 14) +#define G_008040_WAIT_2D_IDLE(x) (((x) >> 14) & 0x1) +#define C_008040_WAIT_2D_IDLE 0xFFFFBFFF +#define S_008040_WAIT_3D_IDLE(x) (((x) & 0x1) << 15) +#define G_008040_WAIT_3D_IDLE(x) (((x) >> 15) & 0x1) +#define C_008040_WAIT_3D_IDLE 0xFFFF7FFF +#define S_008040_WAIT_2D_IDLECLEAN(x) (((x) & 0x1) << 16) +#define G_008040_WAIT_2D_IDLECLEAN(x) (((x) >> 16) & 0x1) +#define C_008040_WAIT_2D_IDLECLEAN 0xFFFEFFFF +#define S_008040_WAIT_3D_IDLECLEAN(x) (((x) & 0x1) << 17) +#define G_008040_WAIT_3D_IDLECLEAN(x) (((x) >> 17) & 0x1) +#define C_008040_WAIT_3D_IDLECLEAN 0xFFFDFFFF +#define S_008040_WAIT_EXTERN_SIG(x) (((x) & 0x1) << 19) +#define G_008040_WAIT_EXTERN_SIG(x) (((x) >> 19) & 0x1) +#define C_008040_WAIT_EXTERN_SIG 0xFFF7FFFF +#define S_008040_CMDFIFO_ENTRIES(x) (((x) & 0x1F) << 20) +#define G_008040_CMDFIFO_ENTRIES(x) (((x) >> 20) & 0x1F) +#define C_008040_CMDFIFO_ENTRIES 0xFE0FFFFF +#define R_0286CC_SPI_PS_IN_CONTROL_0 0x0286CC +#define S_0286CC_NUM_INTERP(x) (((x) & 0x3F) << 0) +#define G_0286CC_NUM_INTERP(x) (((x) >> 0) & 0x3F) +#define C_0286CC_NUM_INTERP 0xFFFFFFC0 +#define S_0286CC_POSITION_ENA(x) (((x) & 0x1) << 8) +#define G_0286CC_POSITION_ENA(x) (((x) >> 8) & 0x1) +#define C_0286CC_POSITION_ENA 0xFFFFFEFF +#define S_0286CC_POSITION_CENTROID(x) (((x) & 0x1) << 9) +#define G_0286CC_POSITION_CENTROID(x) (((x) >> 9) & 0x1) +#define C_0286CC_POSITION_CENTROID 0xFFFFFDFF +#define S_0286CC_POSITION_ADDR(x) (((x) & 0x1F) << 10) +#define G_0286CC_POSITION_ADDR(x) (((x) >> 10) & 0x1F) +#define C_0286CC_POSITION_ADDR 0xFFFF83FF +#define S_0286CC_PARAM_GEN(x) (((x) & 0xF) << 15) +#define G_0286CC_PARAM_GEN(x) (((x) >> 15) & 0xF) +#define C_0286CC_PARAM_GEN 0xFFF87FFF +#define S_0286CC_PARAM_GEN_ADDR(x) (((x) & 0x7F) << 19) +#define G_0286CC_PARAM_GEN_ADDR(x) (((x) >> 19) & 0x7F) +#define C_0286CC_PARAM_GEN_ADDR 0xFC07FFFF +#define S_0286CC_BARYC_SAMPLE_CNTL(x) (((x) & 0x3) << 26) +#define G_0286CC_BARYC_SAMPLE_CNTL(x) (((x) >> 26) & 0x3) +#define C_0286CC_BARYC_SAMPLE_CNTL 0xF3FFFFFF +#define S_0286CC_PERSP_GRADIENT_ENA(x) (((x) & 0x1) << 28) +#define G_0286CC_PERSP_GRADIENT_ENA(x) (((x) >> 28) & 0x1) +#define C_0286CC_PERSP_GRADIENT_ENA 0xEFFFFFFF +#define S_0286CC_LINEAR_GRADIENT_ENA(x) (((x) & 0x1) << 29) +#define G_0286CC_LINEAR_GRADIENT_ENA(x) (((x) >> 29) & 0x1) +#define C_0286CC_LINEAR_GRADIENT_ENA 0xDFFFFFFF +#define S_0286CC_POSITION_SAMPLE(x) (((x) & 0x1) << 30) +#define G_0286CC_POSITION_SAMPLE(x) (((x) >> 30) & 0x1) +#define C_0286CC_POSITION_SAMPLE 0xBFFFFFFF +#define S_0286CC_BARYC_AT_SAMPLE_ENA(x) (((x) & 0x1) << 31) +#define G_0286CC_BARYC_AT_SAMPLE_ENA(x) (((x) >> 31) & 0x1) +#define C_0286CC_BARYC_AT_SAMPLE_ENA 0x7FFFFFFF +#define R_0286D0_SPI_PS_IN_CONTROL_1 0x0286D0 +#define S_0286D0_GEN_INDEX_PIX(x) (((x) & 0x1) << 0) +#define G_0286D0_GEN_INDEX_PIX(x) (((x) >> 0) & 0x1) +#define C_0286D0_GEN_INDEX_PIX 0xFFFFFFFE +#define S_0286D0_GEN_INDEX_PIX_ADDR(x) (((x) & 0x7F) << 1) +#define G_0286D0_GEN_INDEX_PIX_ADDR(x) (((x) >> 1) & 0x7F) +#define C_0286D0_GEN_INDEX_PIX_ADDR 0xFFFFFF01 +#define S_0286D0_FRONT_FACE_ENA(x) (((x) & 0x1) << 8) +#define G_0286D0_FRONT_FACE_ENA(x) (((x) >> 8) & 0x1) +#define C_0286D0_FRONT_FACE_ENA 0xFFFFFEFF +#define S_0286D0_FRONT_FACE_CHAN(x) (((x) & 0x3) << 9) +#define G_0286D0_FRONT_FACE_CHAN(x) (((x) >> 9) & 0x3) +#define C_0286D0_FRONT_FACE_CHAN 0xFFFFF9FF +#define S_0286D0_FRONT_FACE_ALL_BITS(x) (((x) & 0x1) << 11) +#define G_0286D0_FRONT_FACE_ALL_BITS(x) (((x) >> 11) & 0x1) +#define C_0286D0_FRONT_FACE_ALL_BITS 0xFFFFF7FF +#define S_0286D0_FRONT_FACE_ADDR(x) (((x) & 0x1F) << 12) +#define G_0286D0_FRONT_FACE_ADDR(x) (((x) >> 12) & 0x1F) +#define C_0286D0_FRONT_FACE_ADDR 0xFFFE0FFF +#define S_0286D0_FOG_ADDR(x) (((x) & 0x7F) << 17) +#define G_0286D0_FOG_ADDR(x) (((x) >> 17) & 0x7F) +#define C_0286D0_FOG_ADDR 0xFF01FFFF +#define S_0286D0_FIXED_PT_POSITION_ENA(x) (((x) & 0x1) << 24) +#define G_0286D0_FIXED_PT_POSITION_ENA(x) (((x) >> 24) & 0x1) +#define C_0286D0_FIXED_PT_POSITION_ENA 0xFEFFFFFF +#define S_0286D0_FIXED_PT_POSITION_ADDR(x) (((x) & 0x1F) << 25) +#define G_0286D0_FIXED_PT_POSITION_ADDR(x) (((x) >> 25) & 0x1F) +#define C_0286D0_FIXED_PT_POSITION_ADDR 0xC1FFFFFF +#define R_0286C4_SPI_VS_OUT_CONFIG 0x0286C4 +#define S_0286C4_VS_PER_COMPONENT(x) (((x) & 0x1) << 0) +#define G_0286C4_VS_PER_COMPONENT(x) (((x) >> 0) & 0x1) +#define C_0286C4_VS_PER_COMPONENT 0xFFFFFFFE +#define S_0286C4_VS_EXPORT_COUNT(x) (((x) & 0x1F) << 1) +#define G_0286C4_VS_EXPORT_COUNT(x) (((x) >> 1) & 0x1F) +#define C_0286C4_VS_EXPORT_COUNT 0xFFFFFFC1 +#define S_0286C4_VS_EXPORTS_FOG(x) (((x) & 0x1) << 8) +#define G_0286C4_VS_EXPORTS_FOG(x) (((x) >> 8) & 0x1) +#define C_0286C4_VS_EXPORTS_FOG 0xFFFFFEFF +#define S_0286C4_VS_OUT_FOG_VEC_ADDR(x) (((x) & 0x1F) << 9) +#define G_0286C4_VS_OUT_FOG_VEC_ADDR(x) (((x) >> 9) & 0x1F) +#define C_0286C4_VS_OUT_FOG_VEC_ADDR 0xFFFFC1FF +#define R_028240_PA_SC_GENERIC_SCISSOR_TL 0x028240 +#define S_028240_TL_X(x) (((x) & 0x3FFF) << 0) +#define G_028240_TL_X(x) (((x) >> 0) & 0x3FFF) +#define C_028240_TL_X 0xFFFFC000 +#define S_028240_TL_Y(x) (((x) & 0x3FFF) << 16) +#define G_028240_TL_Y(x) (((x) >> 16) & 0x3FFF) +#define C_028240_TL_Y 0xC000FFFF +#define S_028240_WINDOW_OFFSET_DISABLE(x) (((x) & 0x1) << 31) +#define G_028240_WINDOW_OFFSET_DISABLE(x) (((x) >> 31) & 0x1) +#define C_028240_WINDOW_OFFSET_DISABLE 0x7FFFFFFF +#define R_028244_PA_SC_GENERIC_SCISSOR_BR 0x028244 +#define S_028244_BR_X(x) (((x) & 0x3FFF) << 0) +#define G_028244_BR_X(x) (((x) >> 0) & 0x3FFF) +#define C_028244_BR_X 0xFFFFC000 +#define S_028244_BR_Y(x) (((x) & 0x3FFF) << 16) +#define G_028244_BR_Y(x) (((x) >> 16) & 0x3FFF) +#define C_028244_BR_Y 0xC000FFFF +#define R_028030_PA_SC_SCREEN_SCISSOR_TL 0x028030 +#define S_028030_TL_X(x) (((x) & 0x7FFF) << 0) +#define G_028030_TL_X(x) (((x) >> 0) & 0x7FFF) +#define C_028030_TL_X 0xFFFF8000 +#define S_028030_TL_Y(x) (((x) & 0x7FFF) << 16) +#define G_028030_TL_Y(x) (((x) >> 16) & 0x7FFF) +#define C_028030_TL_Y 0x8000FFFF +#define R_028034_PA_SC_SCREEN_SCISSOR_BR 0x028034 +#define S_028034_BR_X(x) (((x) & 0x7FFF) << 0) +#define G_028034_BR_X(x) (((x) >> 0) & 0x7FFF) +#define C_028034_BR_X 0xFFFF8000 +#define S_028034_BR_Y(x) (((x) & 0x7FFF) << 16) +#define G_028034_BR_Y(x) (((x) >> 16) & 0x7FFF) +#define C_028034_BR_Y 0x8000FFFF +#define R_028204_PA_SC_WINDOW_SCISSOR_TL 0x028204 +#define S_028204_TL_X(x) (((x) & 0x3FFF) << 0) +#define G_028204_TL_X(x) (((x) >> 0) & 0x3FFF) +#define C_028204_TL_X 0xFFFFC000 +#define S_028204_TL_Y(x) (((x) & 0x3FFF) << 16) +#define G_028204_TL_Y(x) (((x) >> 16) & 0x3FFF) +#define C_028204_TL_Y 0xC000FFFF +#define S_028204_WINDOW_OFFSET_DISABLE(x) (((x) & 0x1) << 31) +#define G_028204_WINDOW_OFFSET_DISABLE(x) (((x) >> 31) & 0x1) +#define C_028204_WINDOW_OFFSET_DISABLE 0x7FFFFFFF +#define R_028208_PA_SC_WINDOW_SCISSOR_BR 0x028208 +#define S_028208_BR_X(x) (((x) & 0x3FFF) << 0) +#define G_028208_BR_X(x) (((x) >> 0) & 0x3FFF) +#define C_028208_BR_X 0xFFFFC000 +#define S_028208_BR_Y(x) (((x) & 0x3FFF) << 16) +#define G_028208_BR_Y(x) (((x) >> 16) & 0x3FFF) +#define C_028208_BR_Y 0xC000FFFF +#define R_0287F0_VGT_DRAW_INITIATOR 0x0287F0 +#define S_0287F0_SOURCE_SELECT(x) (((x) & 0x3) << 0) +#define G_0287F0_SOURCE_SELECT(x) (((x) >> 0) & 0x3) +#define C_0287F0_SOURCE_SELECT 0xFFFFFFFC +#define S_0287F0_MAJOR_MODE(x) (((x) & 0x3) << 2) +#define G_0287F0_MAJOR_MODE(x) (((x) >> 2) & 0x3) +#define C_0287F0_MAJOR_MODE 0xFFFFFFF3 +#define S_0287F0_SPRITE_EN(x) (((x) & 0x1) << 4) +#define G_0287F0_SPRITE_EN(x) (((x) >> 4) & 0x1) +#define C_0287F0_SPRITE_EN 0xFFFFFFEF +#define S_0287F0_NOT_EOP(x) (((x) & 0x1) << 5) +#define G_0287F0_NOT_EOP(x) (((x) >> 5) & 0x1) +#define C_0287F0_NOT_EOP 0xFFFFFFDF +#define S_0287F0_USE_OPAQUE(x) (((x) & 0x1) << 6) +#define G_0287F0_USE_OPAQUE(x) (((x) >> 6) & 0x1) +#define C_0287F0_USE_OPAQUE 0xFFFFFFBF +#define R_0280A0_CB_COLOR0_INFO 0x0280A0 +#define R_0280A4_CB_COLOR1_INFO 0x0280A4 +#define R_0280A8_CB_COLOR2_INFO 0x0280A8 +#define R_0280AC_CB_COLOR3_INFO 0x0280AC +#define R_0280B0_CB_COLOR4_INFO 0x0280B0 +#define R_0280B4_CB_COLOR5_INFO 0x0280B4 +#define R_0280B8_CB_COLOR6_INFO 0x0280B8 +#define R_0280BC_CB_COLOR7_INFO 0x0280BC +#define R_02800C_DB_DEPTH_BASE 0x02800C +#define R_028000_DB_DEPTH_SIZE 0x028000 +#define R_028004_DB_DEPTH_VIEW 0x028004 +#define R_028010_DB_DEPTH_INFO 0x028010 +#define R_028D24_DB_HTILE_SURFACE 0x028D24 +#define R_028D34_DB_PREFETCH_LIMIT 0x028D34 +#define R_0286D4_SPI_INTERP_CONTROL_0 0x0286D4 +#define R_028A48_PA_SC_MPASS_PS_CNTL 0x028A48 +#define R_028C00_PA_SC_LINE_CNTL 0x028C00 +#define R_028C04_PA_SC_AA_CONFIG 0x028C04 +#define R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX 0x028C1C +#define R_028C48_PA_SC_AA_MASK 0x028C48 +#define R_028810_PA_CL_CLIP_CNTL 0x028810 +#define R_02881C_PA_CL_VS_OUT_CNTL 0x02881C +#define R_028820_PA_CL_NANINF_CNTL 0x028820 +#define R_028C0C_PA_CL_GB_VERT_CLIP_ADJ 0x028C0C +#define R_028C10_PA_CL_GB_VERT_DISC_ADJ 0x028C10 +#define R_028C14_PA_CL_GB_HORZ_CLIP_ADJ 0x028C14 +#define R_028C18_PA_CL_GB_HORZ_DISC_ADJ 0x028C18 +#define R_028814_PA_SU_SC_MODE_CNTL 0x028814 +#define R_028A00_PA_SU_POINT_SIZE 0x028A00 +#define R_028A04_PA_SU_POINT_MINMAX 0x028A04 +#define R_028A08_PA_SU_LINE_CNTL 0x028A08 +#define R_028A0C_PA_SC_LINE_STIPPLE 0x028A0C +#define R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL 0x028DF8 +#define R_028DFC_PA_SU_POLY_OFFSET_CLAMP 0x028DFC +#define R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE 0x028E00 +#define R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET 0x028E04 +#define R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE 0x028E08 +#define R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET 0x028E0C +#define R_028818_PA_CL_VTE_CNTL 0x028818 +#define R_02843C_PA_CL_VPORT_XSCALE_0 0x02843C +#define R_028444_PA_CL_VPORT_YSCALE_0 0x028444 +#define R_02844C_PA_CL_VPORT_ZSCALE_0 0x02844C +#define R_028440_PA_CL_VPORT_XOFFSET_0 0x028440 +#define R_028448_PA_CL_VPORT_YOFFSET_0 0x028448 +#define R_028450_PA_CL_VPORT_ZOFFSET_0 0x028450 +#define R_028250_PA_SC_VPORT_SCISSOR_0_TL 0x028250 +#define R_028254_PA_SC_VPORT_SCISSOR_0_BR 0x028254 +#define R_028780_CB_BLEND0_CONTROL 0x028780 +#define R_028784_CB_BLEND1_CONTROL 0x028784 +#define R_028788_CB_BLEND2_CONTROL 0x028788 +#define R_02878C_CB_BLEND3_CONTROL 0x02878C +#define R_028790_CB_BLEND4_CONTROL 0x028790 +#define R_028794_CB_BLEND5_CONTROL 0x028794 +#define R_028798_CB_BLEND6_CONTROL 0x028798 +#define R_02879C_CB_BLEND7_CONTROL 0x02879C +#define R_028804_CB_BLEND_CONTROL 0x028804 +#define R_028028_DB_STENCIL_CLEAR 0x028028 +#define R_02802C_DB_DEPTH_CLEAR 0x02802C +#define R_028430_DB_STENCILREFMASK 0x028430 +#define R_028434_DB_STENCILREFMASK_BF 0x028434 +#define R_028800_DB_DEPTH_CONTROL 0x028800 +#define R_02880C_DB_SHADER_CONTROL 0x02880C +#define R_028D0C_DB_RENDER_CONTROL 0x028D0C +#define R_028D10_DB_RENDER_OVERRIDE 0x028D10 +#define R_028D2C_DB_SRESULTS_COMPARE_STATE1 0x028D2C +#define R_028D30_DB_PRELOAD_CONTROL 0x028D30 +#define R_028D44_DB_ALPHA_TO_MASK 0x028D44 +#define R_028868_SQ_PGM_RESOURCES_VS 0x028868 +#define R_0286CC_SPI_PS_IN_CONTROL_0 0x0286CC +#define R_0286D0_SPI_PS_IN_CONTROL_1 0x0286D0 +#define R_028644_SPI_PS_INPUT_CNTL_0 0x028644 +#define R_028648_SPI_PS_INPUT_CNTL_1 0x028648 +#define R_02864C_SPI_PS_INPUT_CNTL_2 0x02864C +#define R_028650_SPI_PS_INPUT_CNTL_3 0x028650 +#define R_028654_SPI_PS_INPUT_CNTL_4 0x028654 +#define R_028658_SPI_PS_INPUT_CNTL_5 0x028658 +#define R_02865C_SPI_PS_INPUT_CNTL_6 0x02865C +#define R_028660_SPI_PS_INPUT_CNTL_7 0x028660 +#define R_028664_SPI_PS_INPUT_CNTL_8 0x028664 +#define R_028668_SPI_PS_INPUT_CNTL_9 0x028668 +#define R_02866C_SPI_PS_INPUT_CNTL_10 0x02866C +#define R_028670_SPI_PS_INPUT_CNTL_11 0x028670 +#define R_028674_SPI_PS_INPUT_CNTL_12 0x028674 +#define R_028678_SPI_PS_INPUT_CNTL_13 0x028678 +#define R_02867C_SPI_PS_INPUT_CNTL_14 0x02867C +#define R_028680_SPI_PS_INPUT_CNTL_15 0x028680 +#define R_028684_SPI_PS_INPUT_CNTL_16 0x028684 +#define R_028688_SPI_PS_INPUT_CNTL_17 0x028688 +#define R_02868C_SPI_PS_INPUT_CNTL_18 0x02868C +#define R_028690_SPI_PS_INPUT_CNTL_19 0x028690 +#define R_028694_SPI_PS_INPUT_CNTL_20 0x028694 +#define R_028698_SPI_PS_INPUT_CNTL_21 0x028698 +#define R_02869C_SPI_PS_INPUT_CNTL_22 0x02869C +#define R_0286A0_SPI_PS_INPUT_CNTL_23 0x0286A0 +#define R_0286A4_SPI_PS_INPUT_CNTL_24 0x0286A4 +#define R_0286A8_SPI_PS_INPUT_CNTL_25 0x0286A8 +#define R_0286AC_SPI_PS_INPUT_CNTL_26 0x0286AC +#define R_0286B0_SPI_PS_INPUT_CNTL_27 0x0286B0 +#define R_0286B4_SPI_PS_INPUT_CNTL_28 0x0286B4 +#define R_0286B8_SPI_PS_INPUT_CNTL_29 0x0286B8 +#define R_0286BC_SPI_PS_INPUT_CNTL_30 0x0286BC +#define R_0286C0_SPI_PS_INPUT_CNTL_31 0x0286C0 +#define R_028850_SQ_PGM_RESOURCES_PS 0x028850 +#define R_028854_SQ_PGM_EXPORTS_PS 0x028854 +#define R_008958_VGT_PRIMITIVE_TYPE 0x008958 +#define R_028A7C_VGT_DMA_INDEX_TYPE 0x028A7C +#define R_028A88_VGT_DMA_NUM_INSTANCES 0x028A88 +#define R_008970_VGT_NUM_INDICES 0x008970 +#define R_0287F0_VGT_DRAW_INITIATOR 0x0287F0 +#define R_028238_CB_TARGET_MASK 0x028238 +#define R_02823C_CB_SHADER_MASK 0x02823C +#define R_028060_CB_COLOR0_SIZE 0x028060 +#define S_028060_PITCH_TILE_MAX(x) (((x) & 0x3FF) << 0) +#define G_028060_PITCH_TILE_MAX(x) (((x) >> 0) & 0x3FF) +#define C_028060_PITCH_TILE_MAX 0xFFFFFC00 +#define S_028060_SLICE_TILE_MAX(x) (((x) & 0xFFFFF) << 10) +#define G_028060_SLICE_TILE_MAX(x) (((x) >> 10) & 0xFFFFF) +#define C_028060_SLICE_TILE_MAX 0xC00003FF +#define R_028064_CB_COLOR1_SIZE 0x028064 +#define R_028068_CB_COLOR2_SIZE 0x028068 +#define R_02806C_CB_COLOR3_SIZE 0x02806C +#define R_028070_CB_COLOR4_SIZE 0x028070 +#define R_028074_CB_COLOR5_SIZE 0x028074 +#define R_028078_CB_COLOR6_SIZE 0x028078 +#define R_02807C_CB_COLOR7_SIZE 0x02807C +#define R_028040_CB_COLOR0_BASE 0x028040 +#define R_028044_CB_COLOR1_BASE 0x028044 +#define R_028048_CB_COLOR2_BASE 0x028048 +#define R_02804C_CB_COLOR3_BASE 0x02804C +#define R_028050_CB_COLOR4_BASE 0x028050 +#define R_028054_CB_COLOR5_BASE 0x028054 +#define R_028058_CB_COLOR6_BASE 0x028058 +#define R_02805C_CB_COLOR7_BASE 0x02805C +#define R_028240_PA_SC_GENERIC_SCISSOR_TL 0x028240 +#define S_028240_TL_X(x) (((x) & 0x3FFF) << 0) +#define G_028240_TL_X(x) (((x) >> 0) & 0x3FFF) +#define C_028240_TL_X 0xFFFFC000 +#define S_028240_TL_Y(x) (((x) & 0x3FFF) << 16) +#define G_028240_TL_Y(x) (((x) >> 16) & 0x3FFF) +#define C_028240_TL_Y 0xC000FFFF +#define R_028C04_PA_SC_AA_CONFIG 0x028C04 +#define S_028C04_MSAA_NUM_SAMPLES(x) (((x) & 0x3) << 0) +#define G_028C04_MSAA_NUM_SAMPLES(x) (((x) >> 0) & 0x3) +#define C_028C04_MSAA_NUM_SAMPLES 0xFFFFFFFC +#define S_028C04_AA_MASK_CENTROID_DTMN(x) (((x) & 0x1) << 4) +#define G_028C04_AA_MASK_CENTROID_DTMN(x) (((x) >> 4) & 0x1) +#define C_028C04_AA_MASK_CENTROID_DTMN 0xFFFFFFEF +#define S_028C04_MAX_SAMPLE_DIST(x) (((x) & 0xF) << 13) +#define G_028C04_MAX_SAMPLE_DIST(x) (((x) >> 13) & 0xF) +#define C_028C04_MAX_SAMPLE_DIST 0xFFFE1FFF +#define R_0288CC_SQ_PGM_CF_OFFSET_PS 0x0288CC +#define R_0288DC_SQ_PGM_CF_OFFSET_FS 0x0288DC +#define R_0288D0_SQ_PGM_CF_OFFSET_VS 0x0288D0 +#define R_028840_SQ_PGM_START_PS 0x028840 +#define R_028894_SQ_PGM_START_FS 0x028894 +#define R_028858_SQ_PGM_START_VS 0x028858 +#define R_028080_CB_COLOR0_VIEW 0x028080 +#define S_028080_SLICE_START(x) (((x) & 0x7FF) << 0) +#define G_028080_SLICE_START(x) (((x) >> 0) & 0x7FF) +#define C_028080_SLICE_START 0xFFFFF800 +#define S_028080_SLICE_MAX(x) (((x) & 0x7FF) << 13) +#define G_028080_SLICE_MAX(x) (((x) >> 13) & 0x7FF) +#define C_028080_SLICE_MAX 0xFF001FFF +#define R_028100_CB_COLOR0_MASK 0x028100 +#define S_028100_CMASK_BLOCK_MAX(x) (((x) & 0xFFF) << 0) +#define G_028100_CMASK_BLOCK_MAX(x) (((x) >> 0) & 0xFFF) +#define C_028100_CMASK_BLOCK_MAX 0xFFFFF000 +#define S_028100_FMASK_TILE_MAX(x) (((x) & 0xFFFFF) << 12) +#define G_028100_FMASK_TILE_MAX(x) (((x) >> 12) & 0xFFFFF) +#define C_028100_FMASK_TILE_MAX 0x00000FFF +#define R_028040_CB_COLOR0_BASE 0x028040 +#define S_028040_BASE_256B(x) (((x) & 0xFFFFFFFF) << 0) +#define G_028040_BASE_256B(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_028040_BASE_256B 0x00000000 +#define R_0280E0_CB_COLOR0_FRAG 0x0280E0 +#define S_0280E0_BASE_256B(x) (((x) & 0xFFFFFFFF) << 0) +#define G_0280E0_BASE_256B(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_0280E0_BASE_256B 0x00000000 +#define R_0280C0_CB_COLOR0_TILE 0x0280C0 +#define S_0280C0_BASE_256B(x) (((x) & 0xFFFFFFFF) << 0) +#define G_0280C0_BASE_256B(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_0280C0_BASE_256B 0x00000000 +#define R_028808_CB_COLOR_CONTROL 0x028808 +#define S_028808_FOG_ENABLE(x) (((x) & 0x1) << 0) +#define G_028808_FOG_ENABLE(x) (((x) >> 0) & 0x1) +#define C_028808_FOG_ENABLE 0xFFFFFFFE +#define S_028808_MULTIWRITE_ENABLE(x) (((x) & 0x1) << 1) +#define G_028808_MULTIWRITE_ENABLE(x) (((x) >> 1) & 0x1) +#define C_028808_MULTIWRITE_ENABLE 0xFFFFFFFD +#define S_028808_DITHER_ENABLE(x) (((x) & 0x1) << 2) +#define G_028808_DITHER_ENABLE(x) (((x) >> 2) & 0x1) +#define C_028808_DITHER_ENABLE 0xFFFFFFFB +#define S_028808_DEGAMMA_ENABLE(x) (((x) & 0x1) << 3) +#define G_028808_DEGAMMA_ENABLE(x) (((x) >> 3) & 0x1) +#define C_028808_DEGAMMA_ENABLE 0xFFFFFFF7 +#define S_028808_SPECIAL_OP(x) (((x) & 0x7) << 4) +#define G_028808_SPECIAL_OP(x) (((x) >> 4) & 0x7) +#define C_028808_SPECIAL_OP 0xFFFFFF8F +#define S_028808_PER_MRT_BLEND(x) (((x) & 0x1) << 7) +#define G_028808_PER_MRT_BLEND(x) (((x) >> 7) & 0x1) +#define C_028808_PER_MRT_BLEND 0xFFFFFF7F +#define S_028808_TARGET_BLEND_ENABLE(x) (((x) & 0xFF) << 8) +#define G_028808_TARGET_BLEND_ENABLE(x) (((x) >> 8) & 0xFF) +#define C_028808_TARGET_BLEND_ENABLE 0xFFFF00FF +#define S_028808_ROP3(x) (((x) & 0xFF) << 16) +#define G_028808_ROP3(x) (((x) >> 16) & 0xFF) +#define C_028808_ROP3 0xFF00FFFF +#define R_028614_SPI_VS_OUT_ID_0 0x028614 +#define S_028614_SEMANTIC_0(x) (((x) & 0xFF) << 0) +#define G_028614_SEMANTIC_0(x) (((x) >> 0) & 0xFF) +#define C_028614_SEMANTIC_0 0xFFFFFF00 +#define S_028614_SEMANTIC_1(x) (((x) & 0xFF) << 8) +#define G_028614_SEMANTIC_1(x) (((x) >> 8) & 0xFF) +#define C_028614_SEMANTIC_1 0xFFFF00FF +#define S_028614_SEMANTIC_2(x) (((x) & 0xFF) << 16) +#define G_028614_SEMANTIC_2(x) (((x) >> 16) & 0xFF) +#define C_028614_SEMANTIC_2 0xFF00FFFF +#define S_028614_SEMANTIC_3(x) (((x) & 0xFF) << 24) +#define G_028614_SEMANTIC_3(x) (((x) >> 24) & 0xFF) +#define C_028614_SEMANTIC_3 0x00FFFFFF +#define R_028618_SPI_VS_OUT_ID_1 0x028618 +#define R_02861C_SPI_VS_OUT_ID_2 0x02861C +#define R_028620_SPI_VS_OUT_ID_3 0x028620 +#define R_028624_SPI_VS_OUT_ID_4 0x028624 +#define R_028628_SPI_VS_OUT_ID_5 0x028628 +#define R_02862C_SPI_VS_OUT_ID_6 0x02862C +#define R_028630_SPI_VS_OUT_ID_7 0x028630 +#define R_028634_SPI_VS_OUT_ID_8 0x028634 +#define R_028638_SPI_VS_OUT_ID_9 0x028638 +#define R_038000_SQ_TEX_RESOURCE_WORD0_0 0x038000 +#define S_038000_DIM(x) (((x) & 0x7) << 0) +#define G_038000_DIM(x) (((x) >> 0) & 0x7) +#define C_038000_DIM 0xFFFFFFF8 +#define S_038000_TILE_MODE(x) (((x) & 0xF) << 3) +#define G_038000_TILE_MODE(x) (((x) >> 3) & 0xF) +#define C_038000_TILE_MODE 0xFFFFFF87 +#define S_038000_TILE_TYPE(x) (((x) & 0x1) << 7) +#define G_038000_TILE_TYPE(x) (((x) >> 7) & 0x1) +#define C_038000_TILE_TYPE 0xFFFFFF7F +#define S_038000_PITCH(x) (((x) & 0x7FF) << 8) +#define G_038000_PITCH(x) (((x) >> 8) & 0x7FF) +#define C_038000_PITCH 0xFFF800FF +#define S_038000_TEX_WIDTH(x) (((x) & 0x1FFF) << 19) +#define G_038000_TEX_WIDTH(x) (((x) >> 19) & 0x1FFF) +#define C_038000_TEX_WIDTH 0x0007FFFF +#define R_038004_SQ_TEX_RESOURCE_WORD1_0 0x038004 +#define S_038004_TEX_HEIGHT(x) (((x) & 0x1FFF) << 0) +#define G_038004_TEX_HEIGHT(x) (((x) >> 0) & 0x1FFF) +#define C_038004_TEX_HEIGHT 0xFFFFE000 +#define S_038004_TEX_DEPTH(x) (((x) & 0x1FFF) << 13) +#define G_038004_TEX_DEPTH(x) (((x) >> 13) & 0x1FFF) +#define C_038004_TEX_DEPTH 0xFC001FFF +#define S_038004_DATA_FORMAT(x) (((x) & 0x3F) << 26) +#define G_038004_DATA_FORMAT(x) (((x) >> 26) & 0x3F) +#define C_038004_DATA_FORMAT 0x03FFFFFF +#define V_038004_COLOR_INVALID 0x00000000 +#define V_038004_COLOR_8 0x00000001 +#define V_038004_COLOR_4_4 0x00000002 +#define V_038004_COLOR_3_3_2 0x00000003 +#define V_038004_COLOR_16 0x00000005 +#define V_038004_COLOR_16_FLOAT 0x00000006 +#define V_038004_COLOR_8_8 0x00000007 +#define V_038004_COLOR_5_6_5 0x00000008 +#define V_038004_COLOR_6_5_5 0x00000009 +#define V_038004_COLOR_1_5_5_5 0x0000000A +#define V_038004_COLOR_4_4_4_4 0x0000000B +#define V_038004_COLOR_5_5_5_1 0x0000000C +#define V_038004_COLOR_32 0x0000000D +#define V_038004_COLOR_32_FLOAT 0x0000000E +#define V_038004_COLOR_16_16 0x0000000F +#define V_038004_COLOR_16_16_FLOAT 0x00000010 +#define V_038004_COLOR_8_24 0x00000011 +#define V_038004_COLOR_8_24_FLOAT 0x00000012 +#define V_038004_COLOR_24_8 0x00000013 +#define V_038004_COLOR_24_8_FLOAT 0x00000014 +#define V_038004_COLOR_10_11_11 0x00000015 +#define V_038004_COLOR_10_11_11_FLOAT 0x00000016 +#define V_038004_COLOR_11_11_10 0x00000017 +#define V_038004_COLOR_11_11_10_FLOAT 0x00000018 +#define V_038004_COLOR_2_10_10_10 0x00000019 +#define V_038004_COLOR_8_8_8_8 0x0000001A +#define V_038004_COLOR_10_10_10_2 0x0000001B +#define V_038004_COLOR_X24_8_32_FLOAT 0x0000001C +#define V_038004_COLOR_32_32 0x0000001D +#define V_038004_COLOR_32_32_FLOAT 0x0000001E +#define V_038004_COLOR_16_16_16_16 0x0000001F +#define V_038004_COLOR_16_16_16_16_FLOAT 0x00000020 +#define V_038004_COLOR_32_32_32_32 0x00000022 +#define V_038004_COLOR_32_32_32_32_FLOAT 0x00000023 +#define R_038008_SQ_TEX_RESOURCE_WORD2_0 0x038008 +#define S_038008_BASE_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0) +#define G_038008_BASE_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_038008_BASE_ADDRESS 0x00000000 +#define R_03800C_SQ_TEX_RESOURCE_WORD3_0 0x03800C +#define S_03800C_MIP_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0) +#define G_03800C_MIP_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_03800C_MIP_ADDRESS 0x00000000 +#define R_038010_SQ_TEX_RESOURCE_WORD4_0 0x038010 +#define S_038010_FORMAT_COMP_X(x) (((x) & 0x3) << 0) +#define G_038010_FORMAT_COMP_X(x) (((x) >> 0) & 0x3) +#define C_038010_FORMAT_COMP_X 0xFFFFFFFC +#define S_038010_FORMAT_COMP_Y(x) (((x) & 0x3) << 2) +#define G_038010_FORMAT_COMP_Y(x) (((x) >> 2) & 0x3) +#define C_038010_FORMAT_COMP_Y 0xFFFFFFF3 +#define S_038010_FORMAT_COMP_Z(x) (((x) & 0x3) << 4) +#define G_038010_FORMAT_COMP_Z(x) (((x) >> 4) & 0x3) +#define C_038010_FORMAT_COMP_Z 0xFFFFFFCF +#define S_038010_FORMAT_COMP_W(x) (((x) & 0x3) << 6) +#define G_038010_FORMAT_COMP_W(x) (((x) >> 6) & 0x3) +#define C_038010_FORMAT_COMP_W 0xFFFFFF3F +#define S_038010_NUM_FORMAT_ALL(x) (((x) & 0x3) << 8) +#define G_038010_NUM_FORMAT_ALL(x) (((x) >> 8) & 0x3) +#define C_038010_NUM_FORMAT_ALL 0xFFFFFCFF +#define S_038010_SRF_MODE_ALL(x) (((x) & 0x1) << 10) +#define G_038010_SRF_MODE_ALL(x) (((x) >> 10) & 0x1) +#define C_038010_SRF_MODE_ALL 0xFFFFFBFF +#define S_038010_FORCE_DEGAMMA(x) (((x) & 0x1) << 11) +#define G_038010_FORCE_DEGAMMA(x) (((x) >> 11) & 0x1) +#define C_038010_FORCE_DEGAMMA 0xFFFFF7FF +#define S_038010_ENDIAN_SWAP(x) (((x) & 0x3) << 12) +#define G_038010_ENDIAN_SWAP(x) (((x) >> 12) & 0x3) +#define C_038010_ENDIAN_SWAP 0xFFFFCFFF +#define S_038010_REQUEST_SIZE(x) (((x) & 0x3) << 14) +#define G_038010_REQUEST_SIZE(x) (((x) >> 14) & 0x3) +#define C_038010_REQUEST_SIZE 0xFFFF3FFF +#define S_038010_DST_SEL_X(x) (((x) & 0x7) << 16) +#define G_038010_DST_SEL_X(x) (((x) >> 16) & 0x7) +#define C_038010_DST_SEL_X 0xFFF8FFFF +#define S_038010_DST_SEL_Y(x) (((x) & 0x7) << 19) +#define G_038010_DST_SEL_Y(x) (((x) >> 19) & 0x7) +#define C_038010_DST_SEL_Y 0xFFC7FFFF +#define S_038010_DST_SEL_Z(x) (((x) & 0x7) << 22) +#define G_038010_DST_SEL_Z(x) (((x) >> 22) & 0x7) +#define C_038010_DST_SEL_Z 0xFE3FFFFF +#define S_038010_DST_SEL_W(x) (((x) & 0x7) << 25) +#define G_038010_DST_SEL_W(x) (((x) >> 25) & 0x7) +#define C_038010_DST_SEL_W 0xF1FFFFFF +#define S_038010_BASE_LEVEL(x) (((x) & 0xF) << 28) +#define G_038010_BASE_LEVEL(x) (((x) >> 28) & 0xF) +#define C_038010_BASE_LEVEL 0x0FFFFFFF +#define R_038014_SQ_TEX_RESOURCE_WORD5_0 0x038014 +#define S_038014_LAST_LEVEL(x) (((x) & 0xF) << 0) +#define G_038014_LAST_LEVEL(x) (((x) >> 0) & 0xF) +#define C_038014_LAST_LEVEL 0xFFFFFFF0 +#define S_038014_BASE_ARRAY(x) (((x) & 0x1FFF) << 4) +#define G_038014_BASE_ARRAY(x) (((x) >> 4) & 0x1FFF) +#define C_038014_BASE_ARRAY 0xFFFE000F +#define S_038014_LAST_ARRAY(x) (((x) & 0x1FFF) << 17) +#define G_038014_LAST_ARRAY(x) (((x) >> 17) & 0x1FFF) +#define C_038014_LAST_ARRAY 0xC001FFFF +#define R_038018_SQ_TEX_RESOURCE_WORD6_0 0x038018 +#define S_038018_MPEG_CLAMP(x) (((x) & 0x3) << 0) +#define G_038018_MPEG_CLAMP(x) (((x) >> 0) & 0x3) +#define C_038018_MPEG_CLAMP 0xFFFFFFFC +#define S_038018_PERF_MODULATION(x) (((x) & 0x7) << 5) +#define G_038018_PERF_MODULATION(x) (((x) >> 5) & 0x7) +#define C_038018_PERF_MODULATION 0xFFFFFF1F +#define S_038018_INTERLACED(x) (((x) & 0x1) << 8) +#define G_038018_INTERLACED(x) (((x) >> 8) & 0x1) +#define C_038018_INTERLACED 0xFFFFFEFF +#define S_038018_TYPE(x) (((x) & 0x3) << 30) +#define G_038018_TYPE(x) (((x) >> 30) & 0x3) +#define C_038018_TYPE 0x3FFFFFFF +#define R_008040_WAIT_UNTIL 0x008040 +#define S_008040_WAIT_CP_DMA_IDLE(x) (((x) & 0x1) << 8) +#define G_008040_WAIT_CP_DMA_IDLE(x) (((x) >> 8) & 0x1) +#define C_008040_WAIT_CP_DMA_IDLE 0xFFFFFEFF +#define S_008040_WAIT_CMDFIFO(x) (((x) & 0x1) << 10) +#define G_008040_WAIT_CMDFIFO(x) (((x) >> 10) & 0x1) +#define C_008040_WAIT_CMDFIFO 0xFFFFFBFF +#define S_008040_WAIT_2D_IDLE(x) (((x) & 0x1) << 14) +#define G_008040_WAIT_2D_IDLE(x) (((x) >> 14) & 0x1) +#define C_008040_WAIT_2D_IDLE 0xFFFFBFFF +#define S_008040_WAIT_3D_IDLE(x) (((x) & 0x1) << 15) +#define G_008040_WAIT_3D_IDLE(x) (((x) >> 15) & 0x1) +#define C_008040_WAIT_3D_IDLE 0xFFFF7FFF +#define S_008040_WAIT_2D_IDLECLEAN(x) (((x) & 0x1) << 16) +#define G_008040_WAIT_2D_IDLECLEAN(x) (((x) >> 16) & 0x1) +#define C_008040_WAIT_2D_IDLECLEAN 0xFFFEFFFF +#define S_008040_WAIT_3D_IDLECLEAN(x) (((x) & 0x1) << 17) +#define G_008040_WAIT_3D_IDLECLEAN(x) (((x) >> 17) & 0x1) +#define C_008040_WAIT_3D_IDLECLEAN 0xFFFDFFFF +#define S_008040_WAIT_EXTERN_SIG(x) (((x) & 0x1) << 19) +#define G_008040_WAIT_EXTERN_SIG(x) (((x) >> 19) & 0x1) +#define C_008040_WAIT_EXTERN_SIG 0xFFF7FFFF +#define S_008040_CMDFIFO_ENTRIES(x) (((x) & 0x1F) << 20) +#define G_008040_CMDFIFO_ENTRIES(x) (((x) >> 20) & 0x1F) +#define C_008040_CMDFIFO_ENTRIES 0xFE0FFFFF +#define R_008958_VGT_PRIMITIVE_TYPE 0x008958 +#define S_008958_PRIM_TYPE(x) (((x) & 0x3F) << 0) +#define G_008958_PRIM_TYPE(x) (((x) >> 0) & 0x3F) +#define C_008958_PRIM_TYPE 0xFFFFFFC0 +#define R_008C00_SQ_CONFIG 0x008C00 +#define S_008C00_VC_ENABLE(x) (((x) & 0x1) << 0) +#define G_008C00_VC_ENABLE(x) (((x) >> 0) & 0x1) +#define C_008C00_VC_ENABLE 0xFFFFFFFE +#define S_008C00_EXPORT_SRC_C(x) (((x) & 0x1) << 1) +#define G_008C00_EXPORT_SRC_C(x) (((x) >> 1) & 0x1) +#define C_008C00_EXPORT_SRC_C 0xFFFFFFFD +#define S_008C00_DX9_CONSTS(x) (((x) & 0x1) << 2) +#define G_008C00_DX9_CONSTS(x) (((x) >> 2) & 0x1) +#define C_008C00_DX9_CONSTS 0xFFFFFFFB +#define S_008C00_ALU_INST_PREFER_VECTOR(x) (((x) & 0x1) << 3) +#define G_008C00_ALU_INST_PREFER_VECTOR(x) (((x) >> 3) & 0x1) +#define C_008C00_ALU_INST_PREFER_VECTOR 0xFFFFFFF7 +#define S_008C00_DX10_CLAMP(x) (((x) & 0x1) << 4) +#define G_008C00_DX10_CLAMP(x) (((x) >> 4) & 0x1) +#define C_008C00_DX10_CLAMP 0xFFFFFFEF +#define S_008C00_ALU_PREFER_ONE_WATERFALL(x) (((x) & 0x1) << 5) +#define G_008C00_ALU_PREFER_ONE_WATERFALL(x) (((x) >> 5) & 0x1) +#define C_008C00_ALU_PREFER_ONE_WATERFALL 0xFFFFFFDF +#define S_008C00_ALU_MAX_ONE_WATERFALL(x) (((x) & 0x1) << 6) +#define G_008C00_ALU_MAX_ONE_WATERFALL(x) (((x) >> 6) & 0x1) +#define C_008C00_ALU_MAX_ONE_WATERFALL 0xFFFFFFBF +#define S_008C00_CLAUSE_SEQ_PRIO(x) (((x) & 0x3) << 8) +#define G_008C00_CLAUSE_SEQ_PRIO(x) (((x) >> 8) & 0x3) +#define C_008C00_CLAUSE_SEQ_PRIO 0xFFFFFCFF +#define S_008C00_PS_PRIO(x) (((x) & 0x3) << 24) +#define G_008C00_PS_PRIO(x) (((x) >> 24) & 0x3) +#define C_008C00_PS_PRIO 0xFCFFFFFF +#define S_008C00_VS_PRIO(x) (((x) & 0x3) << 26) +#define G_008C00_VS_PRIO(x) (((x) >> 26) & 0x3) +#define C_008C00_VS_PRIO 0xF3FFFFFF +#define S_008C00_GS_PRIO(x) (((x) & 0x3) << 28) +#define G_008C00_GS_PRIO(x) (((x) >> 28) & 0x3) +#define C_008C00_GS_PRIO 0xCFFFFFFF +#define S_008C00_ES_PRIO(x) (((x) & 0x3) << 30) +#define G_008C00_ES_PRIO(x) (((x) >> 30) & 0x3) +#define C_008C00_ES_PRIO 0x3FFFFFFF +#define R_008C04_SQ_GPR_RESOURCE_MGMT_1 0x008C04 +#define S_008C04_NUM_PS_GPRS(x) (((x) & 0xFF) << 0) +#define G_008C04_NUM_PS_GPRS(x) (((x) >> 0) & 0xFF) +#define C_008C04_NUM_PS_GPRS 0xFFFFFF00 +#define S_008C04_NUM_VS_GPRS(x) (((x) & 0xFF) << 16) +#define G_008C04_NUM_VS_GPRS(x) (((x) >> 16) & 0xFF) +#define C_008C04_NUM_VS_GPRS 0xFF00FFFF +#define S_008C04_NUM_CLAUSE_TEMP_GPRS(x) (((x) & 0xF) << 28) +#define G_008C04_NUM_CLAUSE_TEMP_GPRS(x) (((x) >> 28) & 0xF) +#define C_008C04_NUM_CLAUSE_TEMP_GPRS 0x0FFFFFFF +#define R_008C08_SQ_GPR_RESOURCE_MGMT_2 0x008C08 +#define S_008C08_NUM_GS_GPRS(x) (((x) & 0xFF) << 0) +#define G_008C08_NUM_GS_GPRS(x) (((x) >> 0) & 0xFF) +#define C_008C08_NUM_GS_GPRS 0xFFFFFF00 +#define S_008C08_NUM_ES_GPRS(x) (((x) & 0xFF) << 16) +#define G_008C08_NUM_ES_GPRS(x) (((x) >> 16) & 0xFF) +#define C_008C08_NUM_ES_GPRS 0xFF00FFFF +#define R_008C0C_SQ_THREAD_RESOURCE_MGMT 0x008C0C +#define S_008C0C_NUM_PS_THREADS(x) (((x) & 0xFF) << 0) +#define G_008C0C_NUM_PS_THREADS(x) (((x) >> 0) & 0xFF) +#define C_008C0C_NUM_PS_THREADS 0xFFFFFF00 +#define S_008C0C_NUM_VS_THREADS(x) (((x) & 0xFF) << 8) +#define G_008C0C_NUM_VS_THREADS(x) (((x) >> 8) & 0xFF) +#define C_008C0C_NUM_VS_THREADS 0xFFFF00FF +#define S_008C0C_NUM_GS_THREADS(x) (((x) & 0xFF) << 16) +#define G_008C0C_NUM_GS_THREADS(x) (((x) >> 16) & 0xFF) +#define C_008C0C_NUM_GS_THREADS 0xFF00FFFF +#define S_008C0C_NUM_ES_THREADS(x) (((x) & 0xFF) << 24) +#define G_008C0C_NUM_ES_THREADS(x) (((x) >> 24) & 0xFF) +#define C_008C0C_NUM_ES_THREADS 0x00FFFFFF +#define R_008C10_SQ_STACK_RESOURCE_MGMT_1 0x008C10 +#define S_008C10_NUM_PS_STACK_ENTRIES(x) (((x) & 0xFFF) << 0) +#define G_008C10_NUM_PS_STACK_ENTRIES(x) (((x) >> 0) & 0xFFF) +#define C_008C10_NUM_PS_STACK_ENTRIES 0xFFFFF000 +#define S_008C10_NUM_VS_STACK_ENTRIES(x) (((x) & 0xFFF) << 16) +#define G_008C10_NUM_VS_STACK_ENTRIES(x) (((x) >> 16) & 0xFFF) +#define C_008C10_NUM_VS_STACK_ENTRIES 0xF000FFFF +#define R_008C14_SQ_STACK_RESOURCE_MGMT_2 0x008C14 +#define S_008C14_NUM_GS_STACK_ENTRIES(x) (((x) & 0xFFF) << 0) +#define G_008C14_NUM_GS_STACK_ENTRIES(x) (((x) >> 0) & 0xFFF) +#define C_008C14_NUM_GS_STACK_ENTRIES 0xFFFFF000 +#define S_008C14_NUM_ES_STACK_ENTRIES(x) (((x) & 0xFFF) << 16) +#define G_008C14_NUM_ES_STACK_ENTRIES(x) (((x) >> 16) & 0xFFF) +#define C_008C14_NUM_ES_STACK_ENTRIES 0xF000FFFF +#define R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ 0x008D8C +#define S_008D8C_RING0_OFFSET(x) (((x) & 0xFF) << 0) +#define G_008D8C_RING0_OFFSET(x) (((x) >> 0) & 0xFF) +#define C_008D8C_RING0_OFFSET 0xFFFFFF00 +#define S_008D8C_ISOLATE_ES_ENABLE(x) (((x) & 0x1) << 12) +#define G_008D8C_ISOLATE_ES_ENABLE(x) (((x) >> 12) & 0x1) +#define C_008D8C_ISOLATE_ES_ENABLE 0xFFFFEFFF +#define S_008D8C_ISOLATE_GS_ENABLE(x) (((x) & 0x1) << 13) +#define G_008D8C_ISOLATE_GS_ENABLE(x) (((x) >> 13) & 0x1) +#define C_008D8C_ISOLATE_GS_ENABLE 0xFFFFDFFF +#define S_008D8C_VS_PC_LIMIT_ENABLE(x) (((x) & 0x1) << 14) +#define G_008D8C_VS_PC_LIMIT_ENABLE(x) (((x) >> 14) & 0x1) +#define C_008D8C_VS_PC_LIMIT_ENABLE 0xFFFFBFFF +#define R_009508_TA_CNTL_AUX 0x009508 +#define S_009508_DISABLE_CUBE_WRAP(x) (((x) & 0x1) << 0) +#define G_009508_DISABLE_CUBE_WRAP(x) (((x) >> 0) & 0x1) +#define C_009508_DISABLE_CUBE_WRAP 0xFFFFFFFE +#define S_009508_SYNC_GRADIENT(x) (((x) & 0x1) << 24) +#define G_009508_SYNC_GRADIENT(x) (((x) >> 24) & 0x1) +#define C_009508_SYNC_GRADIENT 0xFEFFFFFF +#define S_009508_SYNC_WALKER(x) (((x) & 0x1) << 25) +#define G_009508_SYNC_WALKER(x) (((x) >> 25) & 0x1) +#define C_009508_SYNC_WALKER 0xFDFFFFFF +#define S_009508_SYNC_ALIGNER(x) (((x) & 0x1) << 26) +#define G_009508_SYNC_ALIGNER(x) (((x) >> 26) & 0x1) +#define C_009508_SYNC_ALIGNER 0xFBFFFFFF +#define S_009508_BILINEAR_PRECISION(x) (((x) & 0x1) << 31) +#define G_009508_BILINEAR_PRECISION(x) (((x) >> 31) & 0x1) +#define C_009508_BILINEAR_PRECISION 0x7FFFFFFF +#define R_009714_VC_ENHANCE 0x009714 +#define R_009830_DB_DEBUG 0x009830 +#define R_009838_DB_WATERMARKS 0x009838 +#define S_009838_DEPTH_FREE(x) (((x) & 0x1F) << 0) +#define G_009838_DEPTH_FREE(x) (((x) >> 0) & 0x1F) +#define C_009838_DEPTH_FREE 0xFFFFFFE0 +#define S_009838_DEPTH_FLUSH(x) (((x) & 0x3F) << 5) +#define G_009838_DEPTH_FLUSH(x) (((x) >> 5) & 0x3F) +#define C_009838_DEPTH_FLUSH 0xFFFFF81F +#define S_009838_FORCE_SUMMARIZE(x) (((x) & 0xF) << 11) +#define G_009838_FORCE_SUMMARIZE(x) (((x) >> 11) & 0xF) +#define C_009838_FORCE_SUMMARIZE 0xFFFF87FF +#define S_009838_DEPTH_PENDING_FREE(x) (((x) & 0x1F) << 15) +#define G_009838_DEPTH_PENDING_FREE(x) (((x) >> 15) & 0x1F) +#define C_009838_DEPTH_PENDING_FREE 0xFFF07FFF +#define S_009838_DEPTH_CACHELINE_FREE(x) (((x) & 0x1F) << 20) +#define G_009838_DEPTH_CACHELINE_FREE(x) (((x) >> 20) & 0x1F) +#define C_009838_DEPTH_CACHELINE_FREE 0xFE0FFFFF +#define S_009838_EARLY_Z_PANIC_DISABLE(x) (((x) & 0x1) << 25) +#define G_009838_EARLY_Z_PANIC_DISABLE(x) (((x) >> 25) & 0x1) +#define C_009838_EARLY_Z_PANIC_DISABLE 0xFDFFFFFF +#define S_009838_LATE_Z_PANIC_DISABLE(x) (((x) & 0x1) << 26) +#define G_009838_LATE_Z_PANIC_DISABLE(x) (((x) >> 26) & 0x1) +#define C_009838_LATE_Z_PANIC_DISABLE 0xFBFFFFFF +#define S_009838_RE_Z_PANIC_DISABLE(x) (((x) & 0x1) << 27) +#define G_009838_RE_Z_PANIC_DISABLE(x) (((x) >> 27) & 0x1) +#define C_009838_RE_Z_PANIC_DISABLE 0xF7FFFFFF +#define S_009838_DB_EXTRA_DEBUG(x) (((x) & 0xF) << 28) +#define G_009838_DB_EXTRA_DEBUG(x) (((x) >> 28) & 0xF) +#define C_009838_DB_EXTRA_DEBUG 0x0FFFFFFF +#define R_028030_PA_SC_SCREEN_SCISSOR_TL 0x028030 +#define S_028030_TL_X(x) (((x) & 0x7FFF) << 0) +#define G_028030_TL_X(x) (((x) >> 0) & 0x7FFF) +#define C_028030_TL_X 0xFFFF8000 +#define S_028030_TL_Y(x) (((x) & 0x7FFF) << 16) +#define G_028030_TL_Y(x) (((x) >> 16) & 0x7FFF) +#define C_028030_TL_Y 0x8000FFFF +#define R_028034_PA_SC_SCREEN_SCISSOR_BR 0x028034 +#define S_028034_BR_X(x) (((x) & 0x7FFF) << 0) +#define G_028034_BR_X(x) (((x) >> 0) & 0x7FFF) +#define C_028034_BR_X 0xFFFF8000 +#define S_028034_BR_Y(x) (((x) & 0x7FFF) << 16) +#define G_028034_BR_Y(x) (((x) >> 16) & 0x7FFF) +#define C_028034_BR_Y 0x8000FFFF +#define R_028200_PA_SC_WINDOW_OFFSET 0x028200 +#define S_028200_WINDOW_X_OFFSET(x) (((x) & 0x7FFF) << 0) +#define G_028200_WINDOW_X_OFFSET(x) (((x) >> 0) & 0x7FFF) +#define C_028200_WINDOW_X_OFFSET 0xFFFF8000 +#define S_028200_WINDOW_Y_OFFSET(x) (((x) & 0x7FFF) << 16) +#define G_028200_WINDOW_Y_OFFSET(x) (((x) >> 16) & 0x7FFF) +#define C_028200_WINDOW_Y_OFFSET 0x8000FFFF +#define R_028204_PA_SC_WINDOW_SCISSOR_TL 0x028204 +#define S_028204_TL_X(x) (((x) & 0x3FFF) << 0) +#define G_028204_TL_X(x) (((x) >> 0) & 0x3FFF) +#define C_028204_TL_X 0xFFFFC000 +#define S_028204_TL_Y(x) (((x) & 0x3FFF) << 16) +#define G_028204_TL_Y(x) (((x) >> 16) & 0x3FFF) +#define C_028204_TL_Y 0xC000FFFF +#define S_028204_WINDOW_OFFSET_DISABLE(x) (((x) & 0x1) << 31) +#define G_028204_WINDOW_OFFSET_DISABLE(x) (((x) >> 31) & 0x1) +#define C_028204_WINDOW_OFFSET_DISABLE 0x7FFFFFFF +#define R_028208_PA_SC_WINDOW_SCISSOR_BR 0x028208 +#define S_028208_BR_X(x) (((x) & 0x3FFF) << 0) +#define G_028208_BR_X(x) (((x) >> 0) & 0x3FFF) +#define C_028208_BR_X 0xFFFFC000 +#define S_028208_BR_Y(x) (((x) & 0x3FFF) << 16) +#define G_028208_BR_Y(x) (((x) >> 16) & 0x3FFF) +#define C_028208_BR_Y 0xC000FFFF +#define R_02820C_PA_SC_CLIPRECT_RULE 0x02820C +#define S_02820C_CLIP_RULE(x) (((x) & 0xFFFF) << 0) +#define G_02820C_CLIP_RULE(x) (((x) >> 0) & 0xFFFF) +#define C_02820C_CLIP_RULE 0xFFFF0000 +#define R_028210_PA_SC_CLIPRECT_0_TL 0x028210 +#define S_028210_TL_X(x) (((x) & 0x3FFF) << 0) +#define G_028210_TL_X(x) (((x) >> 0) & 0x3FFF) +#define C_028210_TL_X 0xFFFFC000 +#define S_028210_TL_Y(x) (((x) & 0x3FFF) << 16) +#define G_028210_TL_Y(x) (((x) >> 16) & 0x3FFF) +#define C_028210_TL_Y 0xC000FFFF +#define R_028214_PA_SC_CLIPRECT_0_BR 0x028214 +#define S_028214_BR_X(x) (((x) & 0x3FFF) << 0) +#define G_028214_BR_X(x) (((x) >> 0) & 0x3FFF) +#define C_028214_BR_X 0xFFFFC000 +#define S_028214_BR_Y(x) (((x) & 0x3FFF) << 16) +#define G_028214_BR_Y(x) (((x) >> 16) & 0x3FFF) +#define C_028214_BR_Y 0xC000FFFF +#define R_028218_PA_SC_CLIPRECT_1_TL 0x028218 +#define R_02821C_PA_SC_CLIPRECT_1_BR 0x02821C +#define R_028220_PA_SC_CLIPRECT_2_TL 0x028220 +#define R_028224_PA_SC_CLIPRECT_2_BR 0x028224 +#define R_028228_PA_SC_CLIPRECT_3_TL 0x028228 +#define R_02822C_PA_SC_CLIPRECT_3_BR 0x02822C +#define R_028230_PA_SC_EDGERULE 0x028230 +#define R_028240_PA_SC_GENERIC_SCISSOR_TL 0x028240 +#define S_028240_TL_X(x) (((x) & 0x3FFF) << 0) +#define G_028240_TL_X(x) (((x) >> 0) & 0x3FFF) +#define C_028240_TL_X 0xFFFFC000 +#define S_028240_TL_Y(x) (((x) & 0x3FFF) << 16) +#define G_028240_TL_Y(x) (((x) >> 16) & 0x3FFF) +#define C_028240_TL_Y 0xC000FFFF +#define S_028240_WINDOW_OFFSET_DISABLE(x) (((x) & 0x1) << 31) +#define G_028240_WINDOW_OFFSET_DISABLE(x) (((x) >> 31) & 0x1) +#define C_028240_WINDOW_OFFSET_DISABLE 0x7FFFFFFF +#define R_028244_PA_SC_GENERIC_SCISSOR_BR 0x028244 +#define S_028244_BR_X(x) (((x) & 0x3FFF) << 0) +#define G_028244_BR_X(x) (((x) >> 0) & 0x3FFF) +#define C_028244_BR_X 0xFFFFC000 +#define S_028244_BR_Y(x) (((x) & 0x3FFF) << 16) +#define G_028244_BR_Y(x) (((x) >> 16) & 0x3FFF) +#define C_028244_BR_Y 0xC000FFFF +#define R_0282D0_PA_SC_VPORT_ZMIN_0 0x0282D0 +#define S_0282D0_VPORT_ZMIN(x) (((x) & 0xFFFFFFFF) << 0) +#define G_0282D0_VPORT_ZMIN(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_0282D0_VPORT_ZMIN 0x00000000 +#define R_0282D4_PA_SC_VPORT_ZMAX_0 0x0282D4 +#define S_0282D4_VPORT_ZMAX(x) (((x) & 0xFFFFFFFF) << 0) +#define G_0282D4_VPORT_ZMAX(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_0282D4_VPORT_ZMAX 0x00000000 +#define R_028350_SX_MISC 0x028350 +#define S_028350_MULTIPASS(x) (((x) & 0x1) << 0) +#define G_028350_MULTIPASS(x) (((x) >> 0) & 0x1) +#define C_028350_MULTIPASS 0xFFFFFFFE +#define R_028380_SQ_VTX_SEMANTIC_0 0x028380 +#define S_028380_SEMANTIC_ID(x) (((x) & 0xFF) << 0) +#define G_028380_SEMANTIC_ID(x) (((x) >> 0) & 0xFF) +#define C_028380_SEMANTIC_ID 0xFFFFFF00 +#define R_028384_SQ_VTX_SEMANTIC_1 0x028384 +#define R_028388_SQ_VTX_SEMANTIC_2 0x028388 +#define R_02838C_SQ_VTX_SEMANTIC_3 0x02838C +#define R_028390_SQ_VTX_SEMANTIC_4 0x028390 +#define R_028394_SQ_VTX_SEMANTIC_5 0x028394 +#define R_028398_SQ_VTX_SEMANTIC_6 0x028398 +#define R_02839C_SQ_VTX_SEMANTIC_7 0x02839C +#define R_0283A0_SQ_VTX_SEMANTIC_8 0x0283A0 +#define R_0283A4_SQ_VTX_SEMANTIC_9 0x0283A4 +#define R_0283A8_SQ_VTX_SEMANTIC_10 0x0283A8 +#define R_0283AC_SQ_VTX_SEMANTIC_11 0x0283AC +#define R_0283B0_SQ_VTX_SEMANTIC_12 0x0283B0 +#define R_0283B4_SQ_VTX_SEMANTIC_13 0x0283B4 +#define R_0283B8_SQ_VTX_SEMANTIC_14 0x0283B8 +#define R_0283BC_SQ_VTX_SEMANTIC_15 0x0283BC +#define R_0283C0_SQ_VTX_SEMANTIC_16 0x0283C0 +#define R_0283C4_SQ_VTX_SEMANTIC_17 0x0283C4 +#define R_0283C8_SQ_VTX_SEMANTIC_18 0x0283C8 +#define R_0283CC_SQ_VTX_SEMANTIC_19 0x0283CC +#define R_0283D0_SQ_VTX_SEMANTIC_20 0x0283D0 +#define R_0283D4_SQ_VTX_SEMANTIC_21 0x0283D4 +#define R_0283D8_SQ_VTX_SEMANTIC_22 0x0283D8 +#define R_0283DC_SQ_VTX_SEMANTIC_23 0x0283DC +#define R_0283E0_SQ_VTX_SEMANTIC_24 0x0283E0 +#define R_0283E4_SQ_VTX_SEMANTIC_25 0x0283E4 +#define R_0283E8_SQ_VTX_SEMANTIC_26 0x0283E8 +#define R_0283EC_SQ_VTX_SEMANTIC_27 0x0283EC +#define R_0283F0_SQ_VTX_SEMANTIC_28 0x0283F0 +#define R_0283F4_SQ_VTX_SEMANTIC_29 0x0283F4 +#define R_0283F8_SQ_VTX_SEMANTIC_30 0x0283F8 +#define R_0283FC_SQ_VTX_SEMANTIC_31 0x0283FC +#define R_028400_VGT_MAX_VTX_INDX 0x028400 +#define S_028400_MAX_INDX(x) (((x) & 0xFFFFFFFF) << 0) +#define G_028400_MAX_INDX(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_028400_MAX_INDX 0x00000000 +#define R_028404_VGT_MIN_VTX_INDX 0x028404 +#define S_028404_MIN_INDX(x) (((x) & 0xFFFFFFFF) << 0) +#define G_028404_MIN_INDX(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_028404_MIN_INDX 0x00000000 +#define R_028408_VGT_INDX_OFFSET 0x028408 +#define S_028408_INDX_OFFSET(x) (((x) & 0xFFFFFFFF) << 0) +#define G_028408_INDX_OFFSET(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_028408_INDX_OFFSET 0x00000000 +#define R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX 0x02840C +#define S_02840C_RESET_INDX(x) (((x) & 0xFFFFFFFF) << 0) +#define G_02840C_RESET_INDX(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_02840C_RESET_INDX 0x00000000 +#define R_028410_SX_ALPHA_TEST_CONTROL 0x028410 +#define S_028410_ALPHA_FUNC(x) (((x) & 0x7) << 0) +#define G_028410_ALPHA_FUNC(x) (((x) >> 0) & 0x7) +#define C_028410_ALPHA_FUNC 0xFFFFFFF8 +#define S_028410_ALPHA_TEST_ENABLE(x) (((x) & 0x1) << 3) +#define G_028410_ALPHA_TEST_ENABLE(x) (((x) >> 3) & 0x1) +#define C_028410_ALPHA_TEST_ENABLE 0xFFFFFFF7 +#define S_028410_ALPHA_TEST_BYPASS(x) (((x) & 0x1) << 8) +#define G_028410_ALPHA_TEST_BYPASS(x) (((x) >> 8) & 0x1) +#define C_028410_ALPHA_TEST_BYPASS 0xFFFFFEFF +#define R_028414_CB_BLEND_RED 0x028414 +#define S_028414_BLEND_RED(x) (((x) & 0xFFFFFFFF) << 0) +#define G_028414_BLEND_RED(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_028414_BLEND_RED 0x00000000 +#define R_028418_CB_BLEND_GREEN 0x028418 +#define S_028418_BLEND_GREEN(x) (((x) & 0xFFFFFFFF) << 0) +#define G_028418_BLEND_GREEN(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_028418_BLEND_GREEN 0x00000000 +#define R_02841C_CB_BLEND_BLUE 0x02841C +#define S_02841C_BLEND_BLUE(x) (((x) & 0xFFFFFFFF) << 0) +#define G_02841C_BLEND_BLUE(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_02841C_BLEND_BLUE 0x00000000 +#define R_028420_CB_BLEND_ALPHA 0x028420 +#define S_028420_BLEND_ALPHA(x) (((x) & 0xFFFFFFFF) << 0) +#define G_028420_BLEND_ALPHA(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_028420_BLEND_ALPHA 0x00000000 +#define R_028438_SX_ALPHA_REF 0x028438 +#define S_028438_ALPHA_REF(x) (((x) & 0xFFFFFFFF) << 0) +#define G_028438_ALPHA_REF(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_028438_ALPHA_REF 0x00000000 +#define R_0286C8_SPI_THREAD_GROUPING 0x0286C8 +#define S_0286C8_PS_GROUPING(x) (((x) & 0x1F) << 0) +#define G_0286C8_PS_GROUPING(x) (((x) >> 0) & 0x1F) +#define C_0286C8_PS_GROUPING 0xFFFFFFE0 +#define S_0286C8_VS_GROUPING(x) (((x) & 0x1F) << 8) +#define G_0286C8_VS_GROUPING(x) (((x) >> 8) & 0x1F) +#define C_0286C8_VS_GROUPING 0xFFFFE0FF +#define S_0286C8_GS_GROUPING(x) (((x) & 0x1F) << 16) +#define G_0286C8_GS_GROUPING(x) (((x) >> 16) & 0x1F) +#define C_0286C8_GS_GROUPING 0xFFE0FFFF +#define S_0286C8_ES_GROUPING(x) (((x) & 0x1F) << 24) +#define G_0286C8_ES_GROUPING(x) (((x) >> 24) & 0x1F) +#define C_0286C8_ES_GROUPING 0xE0FFFFFF +#define R_0286D8_SPI_INPUT_Z 0x0286D8 +#define S_0286D8_PROVIDE_Z_TO_SPI(x) (((x) & 0x1) << 0) +#define G_0286D8_PROVIDE_Z_TO_SPI(x) (((x) >> 0) & 0x1) +#define C_0286D8_PROVIDE_Z_TO_SPI 0xFFFFFFFE +#define R_0286DC_SPI_FOG_CNTL 0x0286DC +#define S_0286DC_PASS_FOG_THROUGH_PS(x) (((x) & 0x1) << 0) +#define G_0286DC_PASS_FOG_THROUGH_PS(x) (((x) >> 0) & 0x1) +#define C_0286DC_PASS_FOG_THROUGH_PS 0xFFFFFFFE +#define S_0286DC_PIXEL_FOG_FUNC(x) (((x) & 0x3) << 1) +#define G_0286DC_PIXEL_FOG_FUNC(x) (((x) >> 1) & 0x3) +#define C_0286DC_PIXEL_FOG_FUNC 0xFFFFFFF9 +#define S_0286DC_PIXEL_FOG_SRC_SEL(x) (((x) & 0x1) << 3) +#define G_0286DC_PIXEL_FOG_SRC_SEL(x) (((x) >> 3) & 0x1) +#define C_0286DC_PIXEL_FOG_SRC_SEL 0xFFFFFFF7 +#define S_0286DC_VS_FOG_CLAMP_DISABLE(x) (((x) & 0x1) << 4) +#define G_0286DC_VS_FOG_CLAMP_DISABLE(x) (((x) >> 4) & 0x1) +#define C_0286DC_VS_FOG_CLAMP_DISABLE 0xFFFFFFEF +#define R_0286E0_SPI_FOG_FUNC_SCALE 0x0286E0 +#define S_0286E0_VALUE(x) (((x) & 0xFFFFFFFF) << 0) +#define G_0286E0_VALUE(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_0286E0_VALUE 0x00000000 +#define R_0286E4_SPI_FOG_FUNC_BIAS 0x0286E4 +#define S_0286E4_VALUE(x) (((x) & 0xFFFFFFFF) << 0) +#define G_0286E4_VALUE(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_0286E4_VALUE 0x00000000 +#define R_0287A0_CB_SHADER_CONTROL 0x0287A0 +#define S_0287A0_RT0_ENABLE(x) (((x) & 0x1) << 0) +#define G_0287A0_RT0_ENABLE(x) (((x) >> 0) & 0x1) +#define C_0287A0_RT0_ENABLE 0xFFFFFFFE +#define S_0287A0_RT1_ENABLE(x) (((x) & 0x1) << 1) +#define G_0287A0_RT1_ENABLE(x) (((x) >> 1) & 0x1) +#define C_0287A0_RT1_ENABLE 0xFFFFFFFD +#define S_0287A0_RT2_ENABLE(x) (((x) & 0x1) << 2) +#define G_0287A0_RT2_ENABLE(x) (((x) >> 2) & 0x1) +#define C_0287A0_RT2_ENABLE 0xFFFFFFFB +#define S_0287A0_RT3_ENABLE(x) (((x) & 0x1) << 3) +#define G_0287A0_RT3_ENABLE(x) (((x) >> 3) & 0x1) +#define C_0287A0_RT3_ENABLE 0xFFFFFFF7 +#define S_0287A0_RT4_ENABLE(x) (((x) & 0x1) << 4) +#define G_0287A0_RT4_ENABLE(x) (((x) >> 4) & 0x1) +#define C_0287A0_RT4_ENABLE 0xFFFFFFEF +#define S_0287A0_RT5_ENABLE(x) (((x) & 0x1) << 5) +#define G_0287A0_RT5_ENABLE(x) (((x) >> 5) & 0x1) +#define C_0287A0_RT5_ENABLE 0xFFFFFFDF +#define S_0287A0_RT6_ENABLE(x) (((x) & 0x1) << 6) +#define G_0287A0_RT6_ENABLE(x) (((x) >> 6) & 0x1) +#define C_0287A0_RT6_ENABLE 0xFFFFFFBF +#define S_0287A0_RT7_ENABLE(x) (((x) & 0x1) << 7) +#define G_0287A0_RT7_ENABLE(x) (((x) >> 7) & 0x1) +#define C_0287A0_RT7_ENABLE 0xFFFFFF7F +#define R_028894_SQ_PGM_START_FS 0x028894 +#define S_028894_PGM_START(x) (((x) & 0xFFFFFFFF) << 0) +#define G_028894_PGM_START(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_028894_PGM_START 0x00000000 +#define R_0288A4_SQ_PGM_RESOURCES_FS 0x0288A4 +#define S_0288A4_NUM_GPRS(x) (((x) & 0xFF) << 0) +#define G_0288A4_NUM_GPRS(x) (((x) >> 0) & 0xFF) +#define C_0288A4_NUM_GPRS 0xFFFFFF00 +#define S_0288A4_STACK_SIZE(x) (((x) & 0xFF) << 8) +#define G_0288A4_STACK_SIZE(x) (((x) >> 8) & 0xFF) +#define C_0288A4_STACK_SIZE 0xFFFF00FF +#define S_0288A4_DX10_CLAMP(x) (((x) & 0x1) << 21) +#define G_0288A4_DX10_CLAMP(x) (((x) >> 21) & 0x1) +#define C_0288A4_DX10_CLAMP 0xFFDFFFFF +#define R_0288A8_SQ_ESGS_RING_ITEMSIZE 0x0288A8 +#define S_0288A8_ITEMSIZE(x) (((x) & 0x7FFF) << 0) +#define G_0288A8_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) +#define C_0288A8_ITEMSIZE 0xFFFF8000 +#define R_0288AC_SQ_GSVS_RING_ITEMSIZE 0x0288AC +#define S_0288AC_ITEMSIZE(x) (((x) & 0x7FFF) << 0) +#define G_0288AC_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) +#define C_0288AC_ITEMSIZE 0xFFFF8000 +#define R_0288B0_SQ_ESTMP_RING_ITEMSIZE 0x0288B0 +#define S_0288B0_ITEMSIZE(x) (((x) & 0x7FFF) << 0) +#define G_0288B0_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) +#define C_0288B0_ITEMSIZE 0xFFFF8000 +#define R_0288B4_SQ_GSTMP_RING_ITEMSIZE 0x0288B4 +#define S_0288B4_ITEMSIZE(x) (((x) & 0x7FFF) << 0) +#define G_0288B4_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) +#define C_0288B4_ITEMSIZE 0xFFFF8000 +#define R_0288B8_SQ_VSTMP_RING_ITEMSIZE 0x0288B8 +#define S_0288B8_ITEMSIZE(x) (((x) & 0x7FFF) << 0) +#define G_0288B8_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) +#define C_0288B8_ITEMSIZE 0xFFFF8000 +#define R_0288BC_SQ_PSTMP_RING_ITEMSIZE 0x0288BC +#define S_0288BC_ITEMSIZE(x) (((x) & 0x7FFF) << 0) +#define G_0288BC_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) +#define C_0288BC_ITEMSIZE 0xFFFF8000 +#define R_0288C0_SQ_FBUF_RING_ITEMSIZE 0x0288C0 +#define S_0288C0_ITEMSIZE(x) (((x) & 0x7FFF) << 0) +#define G_0288C0_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) +#define C_0288C0_ITEMSIZE 0xFFFF8000 +#define R_0288C4_SQ_REDUC_RING_ITEMSIZE 0x0288C4 +#define S_0288C4_ITEMSIZE(x) (((x) & 0x7FFF) << 0) +#define G_0288C4_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) +#define C_0288C4_ITEMSIZE 0xFFFF8000 +#define R_0288C8_SQ_GS_VERT_ITEMSIZE 0x0288C8 +#define S_0288C8_ITEMSIZE(x) (((x) & 0x7FFF) << 0) +#define G_0288C8_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) +#define C_0288C8_ITEMSIZE 0xFFFF8000 +#define R_0288DC_SQ_PGM_CF_OFFSET_FS 0x0288DC +#define S_0288DC_PGM_CF_OFFSET(x) (((x) & 0xFFFFF) << 0) +#define G_0288DC_PGM_CF_OFFSET(x) (((x) >> 0) & 0xFFFFF) +#define C_0288DC_PGM_CF_OFFSET 0xFFF00000 +#define R_028A10_VGT_OUTPUT_PATH_CNTL 0x028A10 +#define S_028A10_PATH_SELECT(x) (((x) & 0x3) << 0) +#define G_028A10_PATH_SELECT(x) (((x) >> 0) & 0x3) +#define C_028A10_PATH_SELECT 0xFFFFFFFC +#define R_028A14_VGT_HOS_CNTL 0x028A14 +#define S_028A14_TESS_MODE(x) (((x) & 0x3) << 0) +#define G_028A14_TESS_MODE(x) (((x) >> 0) & 0x3) +#define C_028A14_TESS_MODE 0xFFFFFFFC +#define R_028A18_VGT_HOS_MAX_TESS_LEVEL 0x028A18 +#define S_028A18_MAX_TESS(x) (((x) & 0xFFFFFFFF) << 0) +#define G_028A18_MAX_TESS(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_028A18_MAX_TESS 0x00000000 +#define R_028A1C_VGT_HOS_MIN_TESS_LEVEL 0x028A1C +#define S_028A1C_MIN_TESS(x) (((x) & 0xFFFFFFFF) << 0) +#define G_028A1C_MIN_TESS(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_028A1C_MIN_TESS 0x00000000 +#define R_028A20_VGT_HOS_REUSE_DEPTH 0x028A20 +#define S_028A20_REUSE_DEPTH(x) (((x) & 0xFF) << 0) +#define G_028A20_REUSE_DEPTH(x) (((x) >> 0) & 0xFF) +#define C_028A20_REUSE_DEPTH 0xFFFFFF00 +#define R_028A24_VGT_GROUP_PRIM_TYPE 0x028A24 +#define S_028A24_PRIM_TYPE(x) (((x) & 0x1F) << 0) +#define G_028A24_PRIM_TYPE(x) (((x) >> 0) & 0x1F) +#define C_028A24_PRIM_TYPE 0xFFFFFFE0 +#define S_028A24_RETAIN_ORDER(x) (((x) & 0x1) << 14) +#define G_028A24_RETAIN_ORDER(x) (((x) >> 14) & 0x1) +#define C_028A24_RETAIN_ORDER 0xFFFFBFFF +#define S_028A24_RETAIN_QUADS(x) (((x) & 0x1) << 15) +#define G_028A24_RETAIN_QUADS(x) (((x) >> 15) & 0x1) +#define C_028A24_RETAIN_QUADS 0xFFFF7FFF +#define S_028A24_PRIM_ORDER(x) (((x) & 0x7) << 16) +#define G_028A24_PRIM_ORDER(x) (((x) >> 16) & 0x7) +#define C_028A24_PRIM_ORDER 0xFFF8FFFF +#define R_028A28_VGT_GROUP_FIRST_DECR 0x028A28 +#define S_028A28_FIRST_DECR(x) (((x) & 0xF) << 0) +#define G_028A28_FIRST_DECR(x) (((x) >> 0) & 0xF) +#define C_028A28_FIRST_DECR 0xFFFFFFF0 +#define R_028A2C_VGT_GROUP_DECR 0x028A2C +#define S_028A2C_DECR(x) (((x) & 0xF) << 0) +#define G_028A2C_DECR(x) (((x) >> 0) & 0xF) +#define C_028A2C_DECR 0xFFFFFFF0 +#define R_028A30_VGT_GROUP_VECT_0_CNTL 0x028A30 +#define S_028A30_COMP_X_EN(x) (((x) & 0x1) << 0) +#define G_028A30_COMP_X_EN(x) (((x) >> 0) & 0x1) +#define C_028A30_COMP_X_EN 0xFFFFFFFE +#define S_028A30_COMP_Y_EN(x) (((x) & 0x1) << 1) +#define G_028A30_COMP_Y_EN(x) (((x) >> 1) & 0x1) +#define C_028A30_COMP_Y_EN 0xFFFFFFFD +#define S_028A30_COMP_Z_EN(x) (((x) & 0x1) << 2) +#define G_028A30_COMP_Z_EN(x) (((x) >> 2) & 0x1) +#define C_028A30_COMP_Z_EN 0xFFFFFFFB +#define S_028A30_COMP_W_EN(x) (((x) & 0x1) << 3) +#define G_028A30_COMP_W_EN(x) (((x) >> 3) & 0x1) +#define C_028A30_COMP_W_EN 0xFFFFFFF7 +#define S_028A30_STRIDE(x) (((x) & 0xFF) << 8) +#define G_028A30_STRIDE(x) (((x) >> 8) & 0xFF) +#define C_028A30_STRIDE 0xFFFF00FF +#define S_028A30_SHIFT(x) (((x) & 0xFF) << 16) +#define G_028A30_SHIFT(x) (((x) >> 16) & 0xFF) +#define C_028A30_SHIFT 0xFF00FFFF +#define R_028A34_VGT_GROUP_VECT_1_CNTL 0x028A34 +#define S_028A34_COMP_X_EN(x) (((x) & 0x1) << 0) +#define G_028A34_COMP_X_EN(x) (((x) >> 0) & 0x1) +#define C_028A34_COMP_X_EN 0xFFFFFFFE +#define S_028A34_COMP_Y_EN(x) (((x) & 0x1) << 1) +#define G_028A34_COMP_Y_EN(x) (((x) >> 1) & 0x1) +#define C_028A34_COMP_Y_EN 0xFFFFFFFD +#define S_028A34_COMP_Z_EN(x) (((x) & 0x1) << 2) +#define G_028A34_COMP_Z_EN(x) (((x) >> 2) & 0x1) +#define C_028A34_COMP_Z_EN 0xFFFFFFFB +#define S_028A34_COMP_W_EN(x) (((x) & 0x1) << 3) +#define G_028A34_COMP_W_EN(x) (((x) >> 3) & 0x1) +#define C_028A34_COMP_W_EN 0xFFFFFFF7 +#define S_028A34_STRIDE(x) (((x) & 0xFF) << 8) +#define G_028A34_STRIDE(x) (((x) >> 8) & 0xFF) +#define C_028A34_STRIDE 0xFFFF00FF +#define S_028A34_SHIFT(x) (((x) & 0xFF) << 16) +#define G_028A34_SHIFT(x) (((x) >> 16) & 0xFF) +#define C_028A34_SHIFT 0xFF00FFFF +#define R_028A38_VGT_GROUP_VECT_0_FMT_CNTL 0x028A38 +#define S_028A38_X_CONV(x) (((x) & 0xF) << 0) +#define G_028A38_X_CONV(x) (((x) >> 0) & 0xF) +#define C_028A38_X_CONV 0xFFFFFFF0 +#define S_028A38_X_OFFSET(x) (((x) & 0xF) << 4) +#define G_028A38_X_OFFSET(x) (((x) >> 4) & 0xF) +#define C_028A38_X_OFFSET 0xFFFFFF0F +#define S_028A38_Y_CONV(x) (((x) & 0xF) << 8) +#define G_028A38_Y_CONV(x) (((x) >> 8) & 0xF) +#define C_028A38_Y_CONV 0xFFFFF0FF +#define S_028A38_Y_OFFSET(x) (((x) & 0xF) << 12) +#define G_028A38_Y_OFFSET(x) (((x) >> 12) & 0xF) +#define C_028A38_Y_OFFSET 0xFFFF0FFF +#define S_028A38_Z_CONV(x) (((x) & 0xF) << 16) +#define G_028A38_Z_CONV(x) (((x) >> 16) & 0xF) +#define C_028A38_Z_CONV 0xFFF0FFFF +#define S_028A38_Z_OFFSET(x) (((x) & 0xF) << 20) +#define G_028A38_Z_OFFSET(x) (((x) >> 20) & 0xF) +#define C_028A38_Z_OFFSET 0xFF0FFFFF +#define S_028A38_W_CONV(x) (((x) & 0xF) << 24) +#define G_028A38_W_CONV(x) (((x) >> 24) & 0xF) +#define C_028A38_W_CONV 0xF0FFFFFF +#define S_028A38_W_OFFSET(x) (((x) & 0xF) << 28) +#define G_028A38_W_OFFSET(x) (((x) >> 28) & 0xF) +#define C_028A38_W_OFFSET 0x0FFFFFFF +#define R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL 0x028A3C +#define S_028A3C_X_CONV(x) (((x) & 0xF) << 0) +#define G_028A3C_X_CONV(x) (((x) >> 0) & 0xF) +#define C_028A3C_X_CONV 0xFFFFFFF0 +#define S_028A3C_X_OFFSET(x) (((x) & 0xF) << 4) +#define G_028A3C_X_OFFSET(x) (((x) >> 4) & 0xF) +#define C_028A3C_X_OFFSET 0xFFFFFF0F +#define S_028A3C_Y_CONV(x) (((x) & 0xF) << 8) +#define G_028A3C_Y_CONV(x) (((x) >> 8) & 0xF) +#define C_028A3C_Y_CONV 0xFFFFF0FF +#define S_028A3C_Y_OFFSET(x) (((x) & 0xF) << 12) +#define G_028A3C_Y_OFFSET(x) (((x) >> 12) & 0xF) +#define C_028A3C_Y_OFFSET 0xFFFF0FFF +#define S_028A3C_Z_CONV(x) (((x) & 0xF) << 16) +#define G_028A3C_Z_CONV(x) (((x) >> 16) & 0xF) +#define C_028A3C_Z_CONV 0xFFF0FFFF +#define S_028A3C_Z_OFFSET(x) (((x) & 0xF) << 20) +#define G_028A3C_Z_OFFSET(x) (((x) >> 20) & 0xF) +#define C_028A3C_Z_OFFSET 0xFF0FFFFF +#define S_028A3C_W_CONV(x) (((x) & 0xF) << 24) +#define G_028A3C_W_CONV(x) (((x) >> 24) & 0xF) +#define C_028A3C_W_CONV 0xF0FFFFFF +#define S_028A3C_W_OFFSET(x) (((x) & 0xF) << 28) +#define G_028A3C_W_OFFSET(x) (((x) >> 28) & 0xF) +#define C_028A3C_W_OFFSET 0x0FFFFFFF +#define R_028A40_VGT_GS_MODE 0x028A40 +#define S_028A40_MODE(x) (((x) & 0x3) << 0) +#define G_028A40_MODE(x) (((x) >> 0) & 0x3) +#define C_028A40_MODE 0xFFFFFFFC +#define S_028A40_ES_PASSTHRU(x) (((x) & 0x1) << 2) +#define G_028A40_ES_PASSTHRU(x) (((x) >> 2) & 0x1) +#define C_028A40_ES_PASSTHRU 0xFFFFFFFB +#define S_028A40_CUT_MODE(x) (((x) & 0x3) << 3) +#define G_028A40_CUT_MODE(x) (((x) >> 3) & 0x3) +#define C_028A40_CUT_MODE 0xFFFFFFE7 +#define R_028A4C_PA_SC_MODE_CNTL 0x028A4C +#define S_028A4C_MSAA_ENABLE(x) (((x) & 0x1) << 0) +#define G_028A4C_MSAA_ENABLE(x) (((x) >> 0) & 0x1) +#define C_028A4C_MSAA_ENABLE 0xFFFFFFFE +#define S_028A4C_CLIPRECT_ENABLE(x) (((x) & 0x1) << 1) +#define G_028A4C_CLIPRECT_ENABLE(x) (((x) >> 1) & 0x1) +#define C_028A4C_CLIPRECT_ENABLE 0xFFFFFFFD +#define S_028A4C_LINE_STIPPLE_ENABLE(x) (((x) & 0x1) << 2) +#define G_028A4C_LINE_STIPPLE_ENABLE(x) (((x) >> 2) & 0x1) +#define C_028A4C_LINE_STIPPLE_ENABLE 0xFFFFFFFB +#define S_028A4C_MULTI_CHIP_PRIM_DISCARD_ENAB(x) (((x) & 0x1) << 3) +#define G_028A4C_MULTI_CHIP_PRIM_DISCARD_ENAB(x) (((x) >> 3) & 0x1) +#define C_028A4C_MULTI_CHIP_PRIM_DISCARD_ENAB 0xFFFFFFF7 +#define S_028A4C_WALK_ORDER_ENABLE(x) (((x) & 0x1) << 4) +#define G_028A4C_WALK_ORDER_ENABLE(x) (((x) >> 4) & 0x1) +#define C_028A4C_WALK_ORDER_ENABLE 0xFFFFFFEF +#define S_028A4C_HALVE_DETAIL_SAMPLE_PERF(x) (((x) & 0x1) << 5) +#define G_028A4C_HALVE_DETAIL_SAMPLE_PERF(x) (((x) >> 5) & 0x1) +#define C_028A4C_HALVE_DETAIL_SAMPLE_PERF 0xFFFFFFDF +#define S_028A4C_WALK_SIZE(x) (((x) & 0x1) << 6) +#define G_028A4C_WALK_SIZE(x) (((x) >> 6) & 0x1) +#define C_028A4C_WALK_SIZE 0xFFFFFFBF +#define S_028A4C_WALK_ALIGNMENT(x) (((x) & 0x1) << 7) +#define G_028A4C_WALK_ALIGNMENT(x) (((x) >> 7) & 0x1) +#define C_028A4C_WALK_ALIGNMENT 0xFFFFFF7F +#define S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(x) (((x) & 0x1) << 8) +#define G_028A4C_WALK_ALIGN8_PRIM_FITS_ST(x) (((x) >> 8) & 0x1) +#define C_028A4C_WALK_ALIGN8_PRIM_FITS_ST 0xFFFFFEFF +#define S_028A4C_TILE_COVER_NO_SCISSOR(x) (((x) & 0x1) << 9) +#define G_028A4C_TILE_COVER_NO_SCISSOR(x) (((x) >> 9) & 0x1) +#define C_028A4C_TILE_COVER_NO_SCISSOR 0xFFFFFDFF +#define S_028A4C_KILL_PIX_POST_HI_Z(x) (((x) & 0x1) << 10) +#define G_028A4C_KILL_PIX_POST_HI_Z(x) (((x) >> 10) & 0x1) +#define C_028A4C_KILL_PIX_POST_HI_Z 0xFFFFFBFF +#define S_028A4C_KILL_PIX_POST_DETAIL_MASK(x) (((x) & 0x1) << 11) +#define G_028A4C_KILL_PIX_POST_DETAIL_MASK(x) (((x) >> 11) & 0x1) +#define C_028A4C_KILL_PIX_POST_DETAIL_MASK 0xFFFFF7FF +#define S_028A4C_MULTI_CHIP_SUPERTILE_ENABLE(x) (((x) & 0x1) << 12) +#define G_028A4C_MULTI_CHIP_SUPERTILE_ENABLE(x) (((x) >> 12) & 0x1) +#define C_028A4C_MULTI_CHIP_SUPERTILE_ENABLE 0xFFFFEFFF +#define S_028A4C_TILE_COVER_DISABLE(x) (((x) & 0x1) << 13) +#define G_028A4C_TILE_COVER_DISABLE(x) (((x) >> 13) & 0x1) +#define C_028A4C_TILE_COVER_DISABLE 0xFFFFDFFF +#define S_028A4C_FORCE_EOV_CNTDWN_ENABLE(x) (((x) & 0x1) << 14) +#define G_028A4C_FORCE_EOV_CNTDWN_ENABLE(x) (((x) >> 14) & 0x1) +#define C_028A4C_FORCE_EOV_CNTDWN_ENABLE 0xFFFFBFFF +#define S_028A4C_FORCE_EOV_TILE_ENABLE(x) (((x) & 0x1) << 15) +#define G_028A4C_FORCE_EOV_TILE_ENABLE(x) (((x) >> 15) & 0x1) +#define C_028A4C_FORCE_EOV_TILE_ENABLE 0xFFFF7FFF +#define S_028A4C_FORCE_EOV_REZ_ENABLE(x) (((x) & 0x1) << 16) +#define G_028A4C_FORCE_EOV_REZ_ENABLE(x) (((x) >> 16) & 0x1) +#define C_028A4C_FORCE_EOV_REZ_ENABLE 0xFFFEFFFF +#define S_028A4C_PS_ITER_SAMPLE(x) (((x) & 0x1) << 17) +#define G_028A4C_PS_ITER_SAMPLE(x) (((x) >> 17) & 0x1) +#define C_028A4C_PS_ITER_SAMPLE 0xFFFDFFFF +#define R_028A84_VGT_PRIMITIVEID_EN 0x028A84 +#define S_028A84_PRIMITIVEID_EN(x) (((x) & 0x1) << 0) +#define G_028A84_PRIMITIVEID_EN(x) (((x) >> 0) & 0x1) +#define C_028A84_PRIMITIVEID_EN 0xFFFFFFFE +#define R_028A94_VGT_MULTI_PRIM_IB_RESET_EN 0x028A94 +#define S_028A94_RESET_EN(x) (((x) & 0x1) << 0) +#define G_028A94_RESET_EN(x) (((x) >> 0) & 0x1) +#define C_028A94_RESET_EN 0xFFFFFFFE +#define R_028AA0_VGT_INSTANCE_STEP_RATE_0 0x028AA0 +#define S_028AA0_STEP_RATE(x) (((x) & 0xFFFFFFFF) << 0) +#define G_028AA0_STEP_RATE(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_028AA0_STEP_RATE 0x00000000 +#define R_028AA4_VGT_INSTANCE_STEP_RATE_1 0x028AA4 +#define S_028AA4_STEP_RATE(x) (((x) & 0xFFFFFFFF) << 0) +#define G_028AA4_STEP_RATE(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_028AA4_STEP_RATE 0x00000000 +#define R_028AB0_VGT_STRMOUT_EN 0x028AB0 +#define S_028AB0_STREAMOUT(x) (((x) & 0x1) << 0) +#define G_028AB0_STREAMOUT(x) (((x) >> 0) & 0x1) +#define C_028AB0_STREAMOUT 0xFFFFFFFE +#define R_028AB4_VGT_REUSE_OFF 0x028AB4 +#define S_028AB4_REUSE_OFF(x) (((x) & 0x1) << 0) +#define G_028AB4_REUSE_OFF(x) (((x) >> 0) & 0x1) +#define C_028AB4_REUSE_OFF 0xFFFFFFFE +#define R_028AB8_VGT_VTX_CNT_EN 0x028AB8 +#define S_028AB8_VTX_CNT_EN(x) (((x) & 0x1) << 0) +#define G_028AB8_VTX_CNT_EN(x) (((x) >> 0) & 0x1) +#define C_028AB8_VTX_CNT_EN 0xFFFFFFFE +#define R_028B20_VGT_STRMOUT_BUFFER_EN 0x028B20 +#define S_028B20_BUFFER_0_EN(x) (((x) & 0x1) << 0) +#define G_028B20_BUFFER_0_EN(x) (((x) >> 0) & 0x1) +#define C_028B20_BUFFER_0_EN 0xFFFFFFFE +#define S_028B20_BUFFER_1_EN(x) (((x) & 0x1) << 1) +#define G_028B20_BUFFER_1_EN(x) (((x) >> 1) & 0x1) +#define C_028B20_BUFFER_1_EN 0xFFFFFFFD +#define S_028B20_BUFFER_2_EN(x) (((x) & 0x1) << 2) +#define G_028B20_BUFFER_2_EN(x) (((x) >> 2) & 0x1) +#define C_028B20_BUFFER_2_EN 0xFFFFFFFB +#define S_028B20_BUFFER_3_EN(x) (((x) & 0x1) << 3) +#define G_028B20_BUFFER_3_EN(x) (((x) >> 3) & 0x1) +#define C_028B20_BUFFER_3_EN 0xFFFFFFF7 +#define R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX 0x028C20 +#define S_028C20_S4_X(x) (((x) & 0xF) << 0) +#define G_028C20_S4_X(x) (((x) >> 0) & 0xF) +#define C_028C20_S4_X 0xFFFFFFF0 +#define S_028C20_S4_Y(x) (((x) & 0xF) << 4) +#define G_028C20_S4_Y(x) (((x) >> 4) & 0xF) +#define C_028C20_S4_Y 0xFFFFFF0F +#define S_028C20_S5_X(x) (((x) & 0xF) << 8) +#define G_028C20_S5_X(x) (((x) >> 8) & 0xF) +#define C_028C20_S5_X 0xFFFFF0FF +#define S_028C20_S5_Y(x) (((x) & 0xF) << 12) +#define G_028C20_S5_Y(x) (((x) >> 12) & 0xF) +#define C_028C20_S5_Y 0xFFFF0FFF +#define S_028C20_S6_X(x) (((x) & 0xF) << 16) +#define G_028C20_S6_X(x) (((x) >> 16) & 0xF) +#define C_028C20_S6_X 0xFFF0FFFF +#define S_028C20_S6_Y(x) (((x) & 0xF) << 20) +#define G_028C20_S6_Y(x) (((x) >> 20) & 0xF) +#define C_028C20_S6_Y 0xFF0FFFFF +#define S_028C20_S7_X(x) (((x) & 0xF) << 24) +#define G_028C20_S7_X(x) (((x) >> 24) & 0xF) +#define C_028C20_S7_X 0xF0FFFFFF +#define S_028C20_S7_Y(x) (((x) & 0xF) << 28) +#define G_028C20_S7_Y(x) (((x) >> 28) & 0xF) +#define C_028C20_S7_Y 0x0FFFFFFF +#define R_028C30_CB_CLRCMP_CONTROL 0x028C30 +#define S_028C30_CLRCMP_FCN_SRC(x) (((x) & 0x7) << 0) +#define G_028C30_CLRCMP_FCN_SRC(x) (((x) >> 0) & 0x7) +#define C_028C30_CLRCMP_FCN_SRC 0xFFFFFFF8 +#define S_028C30_CLRCMP_FCN_DST(x) (((x) & 0x7) << 8) +#define G_028C30_CLRCMP_FCN_DST(x) (((x) >> 8) & 0x7) +#define C_028C30_CLRCMP_FCN_DST 0xFFFFF8FF +#define S_028C30_CLRCMP_FCN_SEL(x) (((x) & 0x3) << 24) +#define G_028C30_CLRCMP_FCN_SEL(x) (((x) >> 24) & 0x3) +#define C_028C30_CLRCMP_FCN_SEL 0xFCFFFFFF +#define R_028C34_CB_CLRCMP_SRC 0x028C34 +#define S_028C34_CLRCMP_SRC(x) (((x) & 0xFFFFFFFF) << 0) +#define G_028C34_CLRCMP_SRC(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_028C34_CLRCMP_SRC 0x00000000 +#define R_028C38_CB_CLRCMP_DST 0x028C38 +#define S_028C38_CLRCMP_DST(x) (((x) & 0xFFFFFFFF) << 0) +#define G_028C38_CLRCMP_DST(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_028C38_CLRCMP_DST 0x00000000 +#define R_028C3C_CB_CLRCMP_MSK 0x028C3C +#define S_028C3C_CLRCMP_MSK(x) (((x) & 0xFFFFFFFF) << 0) +#define G_028C3C_CLRCMP_MSK(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_028C3C_CLRCMP_MSK 0x00000000 +#define R_0085F0_CP_COHER_CNTL 0x0085F0 +#define S_0085F0_DEST_BASE_0_ENA(x) (((x) & 0x1) << 0) +#define G_0085F0_DEST_BASE_0_ENA(x) (((x) >> 0) & 0x1) +#define C_0085F0_DEST_BASE_0_ENA 0xFFFFFFFE +#define S_0085F0_DEST_BASE_1_ENA(x) (((x) & 0x1) << 1) +#define G_0085F0_DEST_BASE_1_ENA(x) (((x) >> 1) & 0x1) +#define C_0085F0_DEST_BASE_1_ENA 0xFFFFFFFD +#define S_0085F0_SO0_DEST_BASE_ENA(x) (((x) & 0x1) << 2) +#define G_0085F0_SO0_DEST_BASE_ENA(x) (((x) >> 2) & 0x1) +#define C_0085F0_SO0_DEST_BASE_ENA 0xFFFFFFFB +#define S_0085F0_SO1_DEST_BASE_ENA(x) (((x) & 0x1) << 3) +#define G_0085F0_SO1_DEST_BASE_ENA(x) (((x) >> 3) & 0x1) +#define C_0085F0_SO1_DEST_BASE_ENA 0xFFFFFFF7 +#define S_0085F0_SO2_DEST_BASE_ENA(x) (((x) & 0x1) << 4) +#define G_0085F0_SO2_DEST_BASE_ENA(x) (((x) >> 4) & 0x1) +#define C_0085F0_SO2_DEST_BASE_ENA 0xFFFFFFEF +#define S_0085F0_SO3_DEST_BASE_ENA(x) (((x) & 0x1) << 5) +#define G_0085F0_SO3_DEST_BASE_ENA(x) (((x) >> 5) & 0x1) +#define C_0085F0_SO3_DEST_BASE_ENA 0xFFFFFFDF +#define S_0085F0_CB0_DEST_BASE_ENA(x) (((x) & 0x1) << 6) +#define G_0085F0_CB0_DEST_BASE_ENA(x) (((x) >> 6) & 0x1) +#define C_0085F0_CB0_DEST_BASE_ENA 0xFFFFFFBF +#define S_0085F0_CB1_DEST_BASE_ENA(x) (((x) & 0x1) << 7) +#define G_0085F0_CB1_DEST_BASE_ENA(x) (((x) >> 7) & 0x1) +#define C_0085F0_CB1_DEST_BASE_ENA 0xFFFFFF7F +#define S_0085F0_CB2_DEST_BASE_ENA(x) (((x) & 0x1) << 8) +#define G_0085F0_CB2_DEST_BASE_ENA(x) (((x) >> 8) & 0x1) +#define C_0085F0_CB2_DEST_BASE_ENA 0xFFFFFEFF +#define S_0085F0_CB3_DEST_BASE_ENA(x) (((x) & 0x1) << 9) +#define G_0085F0_CB3_DEST_BASE_ENA(x) (((x) >> 9) & 0x1) +#define C_0085F0_CB3_DEST_BASE_ENA 0xFFFFFDFF +#define S_0085F0_CB4_DEST_BASE_ENA(x) (((x) & 0x1) << 10) +#define G_0085F0_CB4_DEST_BASE_ENA(x) (((x) >> 10) & 0x1) +#define C_0085F0_CB4_DEST_BASE_ENA 0xFFFFFBFF +#define S_0085F0_CB5_DEST_BASE_ENA(x) (((x) & 0x1) << 11) +#define G_0085F0_CB5_DEST_BASE_ENA(x) (((x) >> 11) & 0x1) +#define C_0085F0_CB5_DEST_BASE_ENA 0xFFFFF7FF +#define S_0085F0_CB6_DEST_BASE_ENA(x) (((x) & 0x1) << 12) +#define G_0085F0_CB6_DEST_BASE_ENA(x) (((x) >> 12) & 0x1) +#define C_0085F0_CB6_DEST_BASE_ENA 0xFFFFEFFF +#define S_0085F0_CB7_DEST_BASE_ENA(x) (((x) & 0x1) << 13) +#define G_0085F0_CB7_DEST_BASE_ENA(x) (((x) >> 13) & 0x1) +#define C_0085F0_CB7_DEST_BASE_ENA 0xFFFFDFFF +#define S_0085F0_DB_DEST_BASE_ENA(x) (((x) & 0x1) << 14) +#define G_0085F0_DB_DEST_BASE_ENA(x) (((x) >> 14) & 0x1) +#define C_0085F0_DB_DEST_BASE_ENA 0xFFFFBFFF +#define S_0085F0_CR_DEST_BASE_ENA(x) (((x) & 0x1) << 15) +#define G_0085F0_CR_DEST_BASE_ENA(x) (((x) >> 15) & 0x1) +#define C_0085F0_CR_DEST_BASE_ENA 0xFFFF7FFF +#define S_0085F0_TC_ACTION_ENA(x) (((x) & 0x1) << 23) +#define G_0085F0_TC_ACTION_ENA(x) (((x) >> 23) & 0x1) +#define C_0085F0_TC_ACTION_ENA 0xFF7FFFFF +#define S_0085F0_VC_ACTION_ENA(x) (((x) & 0x1) << 24) +#define G_0085F0_VC_ACTION_ENA(x) (((x) >> 24) & 0x1) +#define C_0085F0_VC_ACTION_ENA 0xFEFFFFFF +#define S_0085F0_CB_ACTION_ENA(x) (((x) & 0x1) << 25) +#define G_0085F0_CB_ACTION_ENA(x) (((x) >> 25) & 0x1) +#define C_0085F0_CB_ACTION_ENA 0xFDFFFFFF +#define S_0085F0_DB_ACTION_ENA(x) (((x) & 0x1) << 26) +#define G_0085F0_DB_ACTION_ENA(x) (((x) >> 26) & 0x1) +#define C_0085F0_DB_ACTION_ENA 0xFBFFFFFF +#define S_0085F0_SH_ACTION_ENA(x) (((x) & 0x1) << 27) +#define G_0085F0_SH_ACTION_ENA(x) (((x) >> 27) & 0x1) +#define C_0085F0_SH_ACTION_ENA 0xF7FFFFFF +#define S_0085F0_SMX_ACTION_ENA(x) (((x) & 0x1) << 28) +#define G_0085F0_SMX_ACTION_ENA(x) (((x) >> 28) & 0x1) +#define C_0085F0_SMX_ACTION_ENA 0xEFFFFFFF +#define S_0085F0_CR0_ACTION_ENA(x) (((x) & 0x1) << 29) +#define G_0085F0_CR0_ACTION_ENA(x) (((x) >> 29) & 0x1) +#define C_0085F0_CR0_ACTION_ENA 0xDFFFFFFF +#define S_0085F0_CR1_ACTION_ENA(x) (((x) & 0x1) << 30) +#define G_0085F0_CR1_ACTION_ENA(x) (((x) >> 30) & 0x1) +#define C_0085F0_CR1_ACTION_ENA 0xBFFFFFFF +#define S_0085F0_CR2_ACTION_ENA(x) (((x) & 0x1) << 31) +#define G_0085F0_CR2_ACTION_ENA(x) (((x) >> 31) & 0x1) +#define C_0085F0_CR2_ACTION_ENA 0x7FFFFFFF + + +#define R_02812C_CB_CLEAR_ALPHA 0x02812C +#define S_02812C_CLEAR_ALPHA(x) (((x) & 0xFFFFFFFF) << 0) +#define G_02812C_CLEAR_ALPHA(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_02812C_CLEAR_ALPHA 0x00000000 +#define R_028128_CB_CLEAR_BLUE 0x028128 +#define S_028128_CLEAR_BLUE(x) (((x) & 0xFFFFFFFF) << 0) +#define G_028128_CLEAR_BLUE(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_028128_CLEAR_BLUE 0x00000000 +#define R_028124_CB_CLEAR_GREEN 0x028124 +#define S_028124_CLEAR_GREEN(x) (((x) & 0xFFFFFFFF) << 0) +#define G_028124_CLEAR_GREEN(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_028124_CLEAR_GREEN 0x00000000 +#define R_028120_CB_CLEAR_RED 0x028120 +#define S_028120_CLEAR_RED(x) (((x) & 0xFFFFFFFF) << 0) +#define G_028120_CLEAR_RED(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_028120_CLEAR_RED 0x00000000 +#define R_02842C_CB_FOG_BLUE 0x02842C +#define S_02842C_FOG_BLUE(x) (((x) & 0xFFFFFFFF) << 0) +#define G_02842C_FOG_BLUE(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_02842C_FOG_BLUE 0x00000000 +#define R_028428_CB_FOG_GREEN 0x028428 +#define S_028428_FOG_GREEN(x) (((x) & 0xFFFFFFFF) << 0) +#define G_028428_FOG_GREEN(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_028428_FOG_GREEN 0x00000000 +#define R_028424_CB_FOG_RED 0x028424 +#define S_028424_FOG_RED(x) (((x) & 0xFFFFFFFF) << 0) +#define G_028424_FOG_RED(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_028424_FOG_RED 0x00000000 +#define R_03C000_SQ_TEX_SAMPLER_WORD0_0 0x03C000 +#define S_03C000_CLAMP_X(x) (((x) & 0x7) << 0) +#define G_03C000_CLAMP_X(x) (((x) >> 0) & 0x7) +#define C_03C000_CLAMP_X 0xFFFFFFF8 +#define S_03C000_CLAMP_Y(x) (((x) & 0x7) << 3) +#define G_03C000_CLAMP_Y(x) (((x) >> 3) & 0x7) +#define C_03C000_CLAMP_Y 0xFFFFFFC7 +#define S_03C000_CLAMP_Z(x) (((x) & 0x7) << 6) +#define G_03C000_CLAMP_Z(x) (((x) >> 6) & 0x7) +#define C_03C000_CLAMP_Z 0xFFFFFE3F +#define S_03C000_XY_MAG_FILTER(x) (((x) & 0x7) << 9) +#define G_03C000_XY_MAG_FILTER(x) (((x) >> 9) & 0x7) +#define C_03C000_XY_MAG_FILTER 0xFFFFF1FF +#define S_03C000_XY_MIN_FILTER(x) (((x) & 0x7) << 12) +#define G_03C000_XY_MIN_FILTER(x) (((x) >> 12) & 0x7) +#define C_03C000_XY_MIN_FILTER 0xFFFF8FFF +#define S_03C000_Z_FILTER(x) (((x) & 0x3) << 15) +#define G_03C000_Z_FILTER(x) (((x) >> 15) & 0x3) +#define C_03C000_Z_FILTER 0xFFFE7FFF +#define S_03C000_MIP_FILTER(x) (((x) & 0x3) << 17) +#define G_03C000_MIP_FILTER(x) (((x) >> 17) & 0x3) +#define C_03C000_MIP_FILTER 0xFFF9FFFF +#define S_03C000_BORDER_COLOR_TYPE(x) (((x) & 0x3) << 22) +#define G_03C000_BORDER_COLOR_TYPE(x) (((x) >> 22) & 0x3) +#define C_03C000_BORDER_COLOR_TYPE 0xFF3FFFFF +#define S_03C000_POINT_SAMPLING_CLAMP(x) (((x) & 0x1) << 24) +#define G_03C000_POINT_SAMPLING_CLAMP(x) (((x) >> 24) & 0x1) +#define C_03C000_POINT_SAMPLING_CLAMP 0xFEFFFFFF +#define S_03C000_TEX_ARRAY_OVERRIDE(x) (((x) & 0x1) << 25) +#define G_03C000_TEX_ARRAY_OVERRIDE(x) (((x) >> 25) & 0x1) +#define C_03C000_TEX_ARRAY_OVERRIDE 0xFDFFFFFF +#define S_03C000_DEPTH_COMPARE_FUNCTION(x) (((x) & 0x7) << 26) +#define G_03C000_DEPTH_COMPARE_FUNCTION(x) (((x) >> 26) & 0x7) +#define C_03C000_DEPTH_COMPARE_FUNCTION 0xE3FFFFFF +#define S_03C000_CHROMA_KEY(x) (((x) & 0x3) << 29) +#define G_03C000_CHROMA_KEY(x) (((x) >> 29) & 0x3) +#define C_03C000_CHROMA_KEY 0x9FFFFFFF +#define S_03C000_LOD_USES_MINOR_AXIS(x) (((x) & 0x1) << 31) +#define G_03C000_LOD_USES_MINOR_AXIS(x) (((x) >> 31) & 0x1) +#define C_03C000_LOD_USES_MINOR_AXIS 0x7FFFFFFF +#define R_03C004_SQ_TEX_SAMPLER_WORD1_0 0x03C004 +#define S_03C004_MIN_LOD(x) (((x) & 0x3FF) << 0) +#define G_03C004_MIN_LOD(x) (((x) >> 0) & 0x3FF) +#define C_03C004_MIN_LOD 0xFFFFFC00 +#define S_03C004_MAX_LOD(x) (((x) & 0x3FF) << 10) +#define G_03C004_MAX_LOD(x) (((x) >> 10) & 0x3FF) +#define C_03C004_MAX_LOD 0xFFF003FF +#define S_03C004_LOD_BIAS(x) (((x) & 0xFFF) << 20) +#define G_03C004_LOD_BIAS(x) (((x) >> 20) & 0xFFF) +#define C_03C004_LOD_BIAS 0x000FFFFF +#define R_03C008_SQ_TEX_SAMPLER_WORD2_0 0x03C008 +#define S_03C008_LOD_BIAS_SEC(x) (((x) & 0xFFF) << 0) +#define G_03C008_LOD_BIAS_SEC(x) (((x) >> 0) & 0xFFF) +#define C_03C008_LOD_BIAS_SEC 0xFFFFF000 +#define S_03C008_MC_COORD_TRUNCATE(x) (((x) & 0x1) << 12) +#define G_03C008_MC_COORD_TRUNCATE(x) (((x) >> 12) & 0x1) +#define C_03C008_MC_COORD_TRUNCATE 0xFFFFEFFF +#define S_03C008_FORCE_DEGAMMA(x) (((x) & 0x1) << 13) +#define G_03C008_FORCE_DEGAMMA(x) (((x) >> 13) & 0x1) +#define C_03C008_FORCE_DEGAMMA 0xFFFFDFFF +#define S_03C008_HIGH_PRECISION_FILTER(x) (((x) & 0x1) << 14) +#define G_03C008_HIGH_PRECISION_FILTER(x) (((x) >> 14) & 0x1) +#define C_03C008_HIGH_PRECISION_FILTER 0xFFFFBFFF +#define S_03C008_PERF_MIP(x) (((x) & 0x7) << 15) +#define G_03C008_PERF_MIP(x) (((x) >> 15) & 0x7) +#define C_03C008_PERF_MIP 0xFFFC7FFF +#define S_03C008_PERF_Z(x) (((x) & 0x3) << 18) +#define G_03C008_PERF_Z(x) (((x) >> 18) & 0x3) +#define C_03C008_PERF_Z 0xFFF3FFFF +#define S_03C008_FETCH_4(x) (((x) & 0x1) << 26) +#define G_03C008_FETCH_4(x) (((x) >> 26) & 0x1) +#define C_03C008_FETCH_4 0xFBFFFFFF +#define S_03C008_SAMPLE_IS_PCF(x) (((x) & 0x1) << 27) +#define G_03C008_SAMPLE_IS_PCF(x) (((x) >> 27) & 0x1) +#define C_03C008_SAMPLE_IS_PCF 0xF7FFFFFF +#define S_03C008_TYPE(x) (((x) & 0x1) << 31) +#define G_03C008_TYPE(x) (((x) >> 31) & 0x1) +#define C_03C008_TYPE 0x7FFFFFFF +#define R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA 0x00A40C +#define S_00A40C_BORDER_ALPHA(x) (((x) & 0xFFFFFFFF) << 0) +#define G_00A40C_BORDER_ALPHA(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_00A40C_BORDER_ALPHA 0x00000000 +#define R_00A408_TD_PS_SAMPLER0_BORDER_BLUE 0x00A408 +#define S_00A408_BORDER_BLUE(x) (((x) & 0xFFFFFFFF) << 0) +#define G_00A408_BORDER_BLUE(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_00A408_BORDER_BLUE 0x00000000 +#define R_00A404_TD_PS_SAMPLER0_BORDER_GREEN 0x00A404 +#define S_00A404_BORDER_GREEN(x) (((x) & 0xFFFFFFFF) << 0) +#define G_00A404_BORDER_GREEN(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_00A404_BORDER_GREEN 0x00000000 +#define R_00A400_TD_PS_SAMPLER0_BORDER_RED 0x00A400 +#define S_00A400_BORDER_RED(x) (((x) & 0xFFFFFFFF) << 0) +#define G_00A400_BORDER_RED(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_00A400_BORDER_RED 0x00000000 +#define R_00A60C_TD_VS_SAMPLER0_BORDER_ALPHA 0x00A60C +#define S_00A60C_BORDER_ALPHA(x) (((x) & 0xFFFFFFFF) << 0) +#define G_00A60C_BORDER_ALPHA(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_00A60C_BORDER_ALPHA 0x00000000 +#define R_00A608_TD_VS_SAMPLER0_BORDER_BLUE 0x00A608 +#define S_00A608_BORDER_BLUE(x) (((x) & 0xFFFFFFFF) << 0) +#define G_00A608_BORDER_BLUE(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_00A608_BORDER_BLUE 0x00000000 +#define R_00A604_TD_VS_SAMPLER0_BORDER_GREEN 0x00A604 +#define S_00A604_BORDER_GREEN(x) (((x) & 0xFFFFFFFF) << 0) +#define G_00A604_BORDER_GREEN(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_00A604_BORDER_GREEN 0x00000000 +#define R_00A600_TD_VS_SAMPLER0_BORDER_RED 0x00A600 +#define S_00A600_BORDER_RED(x) (((x) & 0xFFFFFFFF) << 0) +#define G_00A600_BORDER_RED(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_00A600_BORDER_RED 0x00000000 +#define R_00A80C_TD_GS_SAMPLER0_BORDER_ALPHA 0x00A80C +#define S_00A80C_BORDER_ALPHA(x) (((x) & 0xFFFFFFFF) << 0) +#define G_00A80C_BORDER_ALPHA(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_00A80C_BORDER_ALPHA 0x00000000 +#define R_00A808_TD_GS_SAMPLER0_BORDER_BLUE 0x00A808 +#define S_00A808_BORDER_BLUE(x) (((x) & 0xFFFFFFFF) << 0) +#define G_00A808_BORDER_BLUE(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_00A808_BORDER_BLUE 0x00000000 +#define R_00A804_TD_GS_SAMPLER0_BORDER_GREEN 0x00A804 +#define S_00A804_BORDER_GREEN(x) (((x) & 0xFFFFFFFF) << 0) +#define G_00A804_BORDER_GREEN(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_00A804_BORDER_GREEN 0x00000000 +#define R_00A800_TD_GS_SAMPLER0_BORDER_RED 0x00A800 +#define S_00A800_BORDER_RED(x) (((x) & 0xFFFFFFFF) << 0) +#define G_00A800_BORDER_RED(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_00A800_BORDER_RED 0x00000000 +#define R_030000_SQ_ALU_CONSTANT0_0 0x030000 +#define S_030000_X(x) (((x) & 0xFFFFFFFF) << 0) +#define G_030000_X(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_030000_X 0x00000000 +#define R_030004_SQ_ALU_CONSTANT1_0 0x030004 +#define S_030004_Y(x) (((x) & 0xFFFFFFFF) << 0) +#define G_030004_Y(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_030004_Y 0x00000000 +#define R_030008_SQ_ALU_CONSTANT2_0 0x030008 +#define S_030008_Z(x) (((x) & 0xFFFFFFFF) << 0) +#define G_030008_Z(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_030008_Z 0x00000000 +#define R_03000C_SQ_ALU_CONSTANT3_0 0x03000C +#define S_03000C_W(x) (((x) & 0xFFFFFFFF) << 0) +#define G_03000C_W(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_03000C_W 0x00000000 +#define R_0287E4_VGT_DMA_BASE_HI 0x0287E4 +#define R_0287E8_VGT_DMA_BASE 0x0287E8 + +#endif diff --git a/src/gallium/winsys/drm/r600/core/radeon.c b/src/gallium/winsys/drm/r600/core/radeon.c new file mode 100644 index 00000000000..f2113c5807e --- /dev/null +++ b/src/gallium/winsys/drm/r600/core/radeon.c @@ -0,0 +1,195 @@ +/* + * Copyright © 2009 Jerome Glisse <[email protected]> + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License + * as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software Foundation, + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. + */ +#include <stdio.h> +#include <stdlib.h> +#include <stdint.h> +#include <unistd.h> +#include <string.h> +#include <errno.h> +#include "xf86drm.h" +#include "radeon_priv.h" +#include "radeon_drm.h" +#include "r600d.h" + +static int radeon_get_device(struct radeon *radeon) +{ + struct drm_radeon_info info; + int r; + + radeon->device = 0; + info.request = RADEON_INFO_DEVICE_ID; + info.value = (uintptr_t)&radeon->device; + r = drmCommandWriteRead(radeon->fd, DRM_RADEON_INFO, &info, + sizeof(struct drm_radeon_info)); + return r; +} + +/* symbol missing drove me crazy hack to get symbol exported */ +static void fake(void) +{ + struct radeon_ctx *ctx; + struct radeon_draw *draw; + + ctx = radeon_ctx(NULL); + draw = radeon_draw(NULL); +} + +struct radeon *radeon_new(int fd, unsigned device) +{ + struct radeon *radeon; + int r; + + radeon = calloc(1, sizeof(*radeon)); + if (radeon == NULL) { + fake(); + return NULL; + } + radeon->fd = fd; + radeon->device = device; + radeon->refcount = 1; + if (fd >= 0) { + r = radeon_get_device(radeon); + if (r) { + fprintf(stderr, "Failed to get device id\n"); + return radeon_decref(radeon); + } + } + radeon->family = radeon_family_from_device(radeon->device); + if (radeon->family == CHIP_UNKNOWN) { + fprintf(stderr, "Unknown chipset 0x%04X\n", radeon->device); + return radeon_decref(radeon); + } + switch (radeon->family) { + case CHIP_R600: + case CHIP_RV610: + case CHIP_RV630: + case CHIP_RV670: + case CHIP_RV620: + case CHIP_RV635: + case CHIP_RS780: + case CHIP_RS880: + case CHIP_RV770: + case CHIP_RV730: + case CHIP_RV710: + case CHIP_RV740: + if (r600_init(radeon)) { + return radeon_decref(radeon); + } + break; + case CHIP_R100: + case CHIP_RV100: + case CHIP_RS100: + case CHIP_RV200: + case CHIP_RS200: + case CHIP_R200: + case CHIP_RV250: + case CHIP_RS300: + case CHIP_RV280: + case CHIP_R300: + case CHIP_R350: + case CHIP_RV350: + case CHIP_RV380: + case CHIP_R420: + case CHIP_R423: + case CHIP_RV410: + case CHIP_RS400: + case CHIP_RS480: + case CHIP_RS600: + case CHIP_RS690: + case CHIP_RS740: + case CHIP_RV515: + case CHIP_R520: + case CHIP_RV530: + case CHIP_RV560: + case CHIP_RV570: + case CHIP_R580: + case CHIP_CEDAR: + case CHIP_REDWOOD: + case CHIP_JUNIPER: + case CHIP_CYPRESS: + case CHIP_HEMLOCK: + default: + fprintf(stderr, "%s unknown or unsupported chipset 0x%04X\n", + __func__, radeon->device); + break; + } + return radeon; +} + +struct radeon *radeon_incref(struct radeon *radeon) +{ + if (radeon == NULL) + return NULL; + radeon->refcount++; + return radeon; +} + +struct radeon *radeon_decref(struct radeon *radeon) +{ + if (radeon == NULL) + return NULL; + if (--radeon->refcount > 0) { + return NULL; + } + drmClose(radeon->fd); + free(radeon); + return NULL; +} + +int radeon_reg_id(struct radeon *radeon, unsigned offset, unsigned *typeid, unsigned *stateid, unsigned *id) +{ + unsigned i, j; + + for (i = 0; i < radeon->ntype; i++) { + if (radeon->type[i].range_start) { + if (offset >= radeon->type[i].range_start && offset < radeon->type[i].range_end) { + *typeid = i; + j = offset - radeon->type[i].range_start; + j /= radeon->type[i].stride; + *stateid = radeon->type[i].id + j; + *id = (offset - radeon->type[i].range_start - radeon->type[i].stride * j) / 4; + return 0; + } + } else { + for (j = 0; j < radeon->type[i].nstates; j++) { + if (radeon->type[i].regs[j].offset == offset) { + *typeid = i; + *stateid = radeon->type[i].id; + *id = j; + return 0; + } + } + } + } + fprintf(stderr, "%s unknown register 0x%08X\n", __func__, offset); + return -EINVAL; +} + +unsigned radeon_type_from_id(struct radeon *radeon, unsigned id) +{ + unsigned i; + + for (i = 0; i < radeon->ntype - 1; i++) { + if (radeon->type[i].id == id) + return i; + if (id > radeon->type[i].id && id < radeon->type[i + 1].id) + return i; + } + if (radeon->type[i].id == id) + return i; + return -1; +} diff --git a/src/gallium/winsys/drm/r600/core/radeon_bo.c b/src/gallium/winsys/drm/r600/core/radeon_bo.c new file mode 100644 index 00000000000..f259ae7fb57 --- /dev/null +++ b/src/gallium/winsys/drm/r600/core/radeon_bo.c @@ -0,0 +1,170 @@ +/* + * Copyright 2010 Jerome Glisse <[email protected]> + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Jerome Glisse + */ +#define _FILE_OFFSET_BITS 64 +#include <stdio.h> +#include <stdlib.h> +#include <string.h> +#include <sys/mman.h> +#include <errno.h> +#include "radeon_priv.h" +#include "xf86drm.h" +#include "radeon_drm.h" + +struct radeon_bo *radeon_bo(struct radeon *radeon, unsigned handle, + unsigned size, unsigned alignment, void *ptr) +{ + struct radeon_bo *bo; + int r; + + bo = calloc(1, sizeof(*bo)); + if (bo == NULL) { + return NULL; + } + bo->size = size; + bo->handle = handle; + bo->refcount = 1; + bo->alignment = alignment; + + if (handle) { + struct drm_gem_open open_arg; + + memset(&open_arg, 0, sizeof(open_arg)); + open_arg.name = handle; + r = drmIoctl(radeon->fd, DRM_IOCTL_GEM_OPEN, &open_arg); + if (r != 0) { + free(bo); + return NULL; + } + bo->handle = open_arg.handle; + bo->size = open_arg.size; + } else { + struct drm_radeon_gem_create args; + + args.size = size; + args.alignment = alignment; + args.initial_domain = RADEON_GEM_DOMAIN_CPU; + args.flags = 0; + args.handle = 0; + r = drmCommandWriteRead(radeon->fd, DRM_RADEON_GEM_CREATE, + &args, sizeof(args)); + bo->handle = args.handle; + if (r) { + fprintf(stderr, "Failed to allocate :\n"); + fprintf(stderr, " size : %d bytes\n", size); + fprintf(stderr, " alignment : %d bytes\n", alignment); + free(bo); + return NULL; + } + } + if (ptr) { + if (radeon_bo_map(radeon, bo)) { + fprintf(stderr, "%s failed to copy data into bo\n", __func__); + return radeon_bo_decref(radeon, bo); + } + memcpy(bo->data, ptr, size); + radeon_bo_unmap(radeon, bo); + } + return bo; +} + +int radeon_bo_map(struct radeon *radeon, struct radeon_bo *bo) +{ + struct drm_radeon_gem_mmap args; + void *ptr; + int r; + + if (bo->map_count++ != 0) { + return 0; + } + /* Zero out args to make valgrind happy */ + memset(&args, 0, sizeof(args)); + args.handle = bo->handle; + args.offset = 0; + args.size = (uint64_t)bo->size; + r = drmCommandWriteRead(radeon->fd, DRM_RADEON_GEM_MMAP, + &args, sizeof(args)); + if (r) { + fprintf(stderr, "error mapping %p 0x%08X (error = %d)\n", + bo, bo->handle, r); + return r; + } + ptr = mmap(0, args.size, PROT_READ|PROT_WRITE, MAP_SHARED, radeon->fd, args.addr_ptr); + if (ptr == MAP_FAILED) { + fprintf(stderr, "%s failed to map bo\n", __func__); + return -errno; + } + bo->data = ptr; + return 0; +} + +void radeon_bo_unmap(struct radeon *radeon, struct radeon_bo *bo) +{ + if (--bo->map_count > 0) { + return; + } + munmap(bo->data, bo->size); + bo->data = NULL; +} + +struct radeon_bo *radeon_bo_incref(struct radeon *radeon, struct radeon_bo *bo) +{ + bo->refcount++; + return bo; +} + +struct radeon_bo *radeon_bo_decref(struct radeon *radeon, struct radeon_bo *bo) +{ + struct drm_gem_close args; + + if (bo == NULL) + return NULL; + if (--bo->refcount > 0) { + return NULL; + } + + munmap(bo->data, bo->size); + memset(&args, 0, sizeof(args)); + args.handle = bo->handle; + drmIoctl(radeon->fd, DRM_IOCTL_GEM_CLOSE, &args); + memset(bo, 0, sizeof(struct radeon_bo)); + free(bo); + return NULL; +} + +int radeon_bo_wait(struct radeon *radeon, struct radeon_bo *bo) +{ + struct drm_radeon_gem_wait_idle args; + int ret; + + /* Zero out args to make valgrind happy */ + memset(&args, 0, sizeof(args)); + args.handle = bo->handle; + do { + ret = drmCommandWriteRead(radeon->fd, DRM_RADEON_GEM_WAIT_IDLE, + &args, sizeof(args)); + } while (ret == -EBUSY); + return ret; +} diff --git a/src/gallium/winsys/drm/r600/core/radeon_ctx.c b/src/gallium/winsys/drm/r600/core/radeon_ctx.c new file mode 100644 index 00000000000..0c8f1fac188 --- /dev/null +++ b/src/gallium/winsys/drm/r600/core/radeon_ctx.c @@ -0,0 +1,407 @@ +/* + * Copyright 2010 Jerome Glisse <[email protected]> + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Jerome Glisse + */ +#include <stdio.h> +#include <stdlib.h> +#include <string.h> +#include "radeon_priv.h" +#include "radeon_drm.h" +#include "bof.h" + +int radeon_ctx_set_bo_new(struct radeon_ctx *ctx, struct radeon_bo *bo) +{ + void *ptr; + + ptr = realloc(ctx->bo, sizeof(struct radeon_bo) * (ctx->nbo + 1)); + if (ptr == NULL) { + return -ENOMEM; + } + ctx->bo = ptr; + ctx->bo[ctx->nbo] = bo; + ctx->nbo++; + return 0; +} + +struct radeon_bo *radeon_ctx_get_bo(struct radeon_ctx *ctx, unsigned reloc) +{ + struct radeon_cs_reloc *greloc; + unsigned i; + + greloc = (void *)(((u8 *)ctx->reloc) + reloc * 4); + for (i = 0; i < ctx->nbo; i++) { + if (ctx->bo[i]->handle == greloc->handle) { + return radeon_bo_incref(ctx->radeon, ctx->bo[i]); + } + } + fprintf(stderr, "%s no bo for reloc[%d 0x%08X] %d\n", __func__, reloc, greloc->handle, ctx->nbo); + return NULL; +} + +void radeon_ctx_get_placement(struct radeon_ctx *ctx, unsigned reloc, u32 *placement) +{ + struct radeon_cs_reloc *greloc; + unsigned i; + + placement[0] = 0; + placement[1] = 0; + greloc = (void *)(((u8 *)ctx->reloc) + reloc * 4); + for (i = 0; i < ctx->nbo; i++) { + if (ctx->bo[i]->handle == greloc->handle) { + placement[0] = greloc->read_domain | greloc->write_domain; + placement[1] = placement[0]; + return; + } + } +} + +struct radeon_ctx *radeon_ctx(struct radeon *radeon) +{ + struct radeon_ctx *ctx; + + if (radeon == NULL) + return NULL; + ctx = calloc(1, sizeof(*ctx)); + if (ctx == NULL) + return NULL; + ctx->radeon = radeon_incref(radeon); + return ctx; +} + +struct radeon_ctx *radeon_ctx_incref(struct radeon_ctx *ctx) +{ + ctx->refcount++; + return ctx; +} + +struct radeon_ctx *radeon_ctx_decref(struct radeon_ctx *ctx) +{ + unsigned i; + + if (ctx == NULL) + return NULL; + if (--ctx->refcount > 0) { + return NULL; + } + + for (i = 0; i < ctx->ndraw; i++) { + ctx->draw[i] = radeon_draw_decref(ctx->draw[i]); + } + for (i = 0; i < ctx->nbo; i++) { + ctx->bo[i] = radeon_bo_decref(ctx->radeon, ctx->bo[i]); + } + ctx->radeon = radeon_decref(ctx->radeon); + free(ctx->draw); + free(ctx->bo); + free(ctx->pm4); + free(ctx->reloc); + memset(ctx, 0, sizeof(*ctx)); + free(ctx); + return NULL; +} + +static int radeon_ctx_state_bo(struct radeon_ctx *ctx, struct radeon_state *state) +{ + unsigned i, j; + int r; + + if (state == NULL) + return 0; + for (i = 0; i < state->nbo; i++) { + for (j = 0; j < ctx->nbo; j++) { + if (state->bo[i] == ctx->bo[j]) + break; + } + if (j == ctx->nbo) { + radeon_bo_incref(ctx->radeon, state->bo[i]); + r = radeon_ctx_set_bo_new(ctx, state->bo[i]); + if (r) + return r; + } + } + return 0; +} + + +int radeon_ctx_submit(struct radeon_ctx *ctx) +{ + struct drm_radeon_cs drmib; + struct drm_radeon_cs_chunk chunks[2]; + uint64_t chunk_array[2]; + int r = 0; + +#if 0 + for (r = 0; r < ctx->cpm4; r++) { + fprintf(stderr, "0x%08X\n", ctx->pm4[r]); + } +#endif + drmib.num_chunks = 2; + drmib.chunks = (uint64_t)(uintptr_t)chunk_array; + chunks[0].chunk_id = RADEON_CHUNK_ID_IB; + chunks[0].length_dw = ctx->cpm4; + chunks[0].chunk_data = (uint64_t)(uintptr_t)ctx->pm4; + chunks[1].chunk_id = RADEON_CHUNK_ID_RELOCS; + chunks[1].length_dw = ctx->nreloc * sizeof(struct radeon_cs_reloc) / 4; + chunks[1].chunk_data = (uint64_t)(uintptr_t)ctx->reloc; + chunk_array[0] = (uint64_t)(uintptr_t)&chunks[0]; + chunk_array[1] = (uint64_t)(uintptr_t)&chunks[1]; +#if 1 + r = drmCommandWriteRead(ctx->radeon->fd, DRM_RADEON_CS, &drmib, + sizeof(struct drm_radeon_cs)); +#endif + return r; +} + +static int radeon_ctx_reloc(struct radeon_ctx *ctx, struct radeon_bo *bo, + unsigned id, unsigned *placement) +{ + unsigned i; + struct radeon_cs_reloc *ptr; + + for (i = 0; i < ctx->nreloc; i++) { + if (ctx->reloc[i].handle == bo->handle) { + ctx->pm4[id] = i * sizeof(struct radeon_cs_reloc) / 4; + return 0; + } + } + ptr = realloc(ctx->reloc, sizeof(struct radeon_cs_reloc) * (ctx->nreloc + 1)); + if (ptr == NULL) + return -ENOMEM; + ctx->reloc = ptr; + ptr[ctx->nreloc].handle = bo->handle; + ptr[ctx->nreloc].read_domain = placement[0] | placement [1]; + ptr[ctx->nreloc].write_domain = placement[0] | placement [1]; + ptr[ctx->nreloc].flags = 0; + ctx->pm4[id] = ctx->nreloc * sizeof(struct radeon_cs_reloc) / 4; + ctx->nreloc++; + return 0; +} + +static int radeon_ctx_state_schedule(struct radeon_ctx *ctx, struct radeon_state *state) +{ + unsigned i, rid, bid, cid; + int r; + + if (state == NULL) + return 0; + memcpy(&ctx->pm4[ctx->id], state->pm4, state->cpm4 * 4); + for (i = 0; i < state->nreloc; i++) { + rid = state->reloc_pm4_id[i]; + bid = state->reloc_bo_id[i]; + cid = ctx->id + rid; + r = radeon_ctx_reloc(ctx, state->bo[bid], cid, + &state->placement[bid * 2]); + if (r) { + fprintf(stderr, "%s state %d failed to reloc\n", __func__, state->type); + return r; + } + } + ctx->id += state->cpm4; + return 0; +} + +int radeon_ctx_set_draw_new(struct radeon_ctx *ctx, struct radeon_draw *draw) +{ + struct radeon_draw *pdraw = NULL; + struct radeon_draw **ndraw; + struct radeon_state *nstate, *ostate; + unsigned cpm4, i, cstate; + void *tmp; + int r = 0; + + ndraw = realloc(ctx->draw, sizeof(void*) * (ctx->ndraw + 1)); + if (ndraw == NULL) + return -ENOMEM; + ctx->draw = ndraw; + for (i = 0; i < draw->nstate; i++) { + r = radeon_ctx_state_bo(ctx, draw->state[i]); + if (r) + return r; + } + r = radeon_draw_check(draw); + if (r) + return r; + if (draw->cpm4 >= RADEON_CTX_MAX_PM4) { + fprintf(stderr, "%s single draw too big %d, max %d\n", + __func__, draw->cpm4, RADEON_CTX_MAX_PM4); + return -EINVAL; + } + tmp = realloc(ctx->state, (ctx->nstate + draw->nstate) * sizeof(void*)); + if (tmp == NULL) + return -ENOMEM; + ctx->state = tmp; + pdraw = ctx->cdraw; + for (i = 0, cpm4 = 0, cstate = ctx->nstate; i < draw->nstate - 1; i++) { + nstate = draw->state[i]; + if (nstate) { + if (pdraw && pdraw->state[i]) { + ostate = pdraw->state[i]; + if (ostate->pm4_crc != nstate->pm4_crc) { + ctx->state[cstate++] = nstate; + cpm4 += nstate->cpm4; + } + } else { + ctx->state[cstate++] = nstate; + cpm4 += nstate->cpm4; + } + } + } + /* The last state is the draw state always add it */ + if (draw->state[i] == NULL) { + fprintf(stderr, "%s no draw command\n", __func__); + return -EINVAL; + } + ctx->state[cstate++] = draw->state[i]; + cpm4 += draw->state[i]->cpm4; + if ((ctx->draw_cpm4 + cpm4) > RADEON_CTX_MAX_PM4) { + /* need to flush */ + return -EBUSY; + } + ctx->draw_cpm4 += cpm4; + ctx->nstate = cstate; + ctx->draw[ctx->ndraw++] = draw; + ctx->cdraw = draw; + return 0; +} + +int radeon_ctx_set_draw(struct radeon_ctx *ctx, struct radeon_draw *draw) +{ + int r; + + radeon_draw_incref(draw); + r = radeon_ctx_set_draw_new(ctx, draw); + if (r) + radeon_draw_decref(draw); + return r; +} + +int radeon_ctx_pm4(struct radeon_ctx *ctx) +{ + unsigned i; + int r; + + free(ctx->pm4); + ctx->cpm4 = 0; + ctx->pm4 = malloc(ctx->draw_cpm4 * 4); + if (ctx->pm4 == NULL) + return -EINVAL; + for (i = 0, ctx->id = 0; i < ctx->nstate; i++) { + r = radeon_ctx_state_schedule(ctx, ctx->state[i]); + if (r) + return r; + } + if (ctx->id != ctx->draw_cpm4) { + fprintf(stderr, "%s miss predicted pm4 size %d for %d\n", + __func__, ctx->draw_cpm4, ctx->id); + return -EINVAL; + } + ctx->cpm4 = ctx->draw_cpm4; + return 0; +} + +void radeon_ctx_dump_bof(struct radeon_ctx *ctx, const char *file) +{ + bof_t *bcs, *blob, *array, *bo, *size, *handle, *device_id, *root; + char tmp[256]; + unsigned i; + + root = device_id = bcs = blob = array = bo = size = handle = NULL; + root = bof_object(); + if (root == NULL) + goto out_err; + device_id = bof_int32(ctx->radeon->device); + if (device_id == NULL) + return; + if (bof_object_set(root, "device_id", device_id)) + goto out_err; + bof_decref(device_id); + device_id = NULL; + /* dump relocs */ +printf("%d relocs\n", ctx->nreloc); + blob = bof_blob(ctx->nreloc * 16, ctx->reloc); + if (blob == NULL) + goto out_err; + if (bof_object_set(root, "reloc", blob)) + goto out_err; + bof_decref(blob); + blob = NULL; + /* dump cs */ +printf("%d pm4\n", ctx->cpm4); + blob = bof_blob(ctx->cpm4 * 4, ctx->pm4); + if (blob == NULL) + goto out_err; + if (bof_object_set(root, "pm4", blob)) + goto out_err; + bof_decref(blob); + blob = NULL; + /* dump bo */ + array = bof_array(); + if (array == NULL) + goto out_err; + for (i = 0; i < ctx->nbo; i++) { + bo = bof_object(); + if (bo == NULL) + goto out_err; + size = bof_int32(ctx->bo[i]->size); +printf("[%d] %d bo\n", i, size); + if (size == NULL) + goto out_err; + if (bof_object_set(bo, "size", size)) + goto out_err; + bof_decref(size); + size = NULL; + handle = bof_int32(ctx->bo[i]->handle); + if (handle == NULL) + goto out_err; + if (bof_object_set(bo, "handle", handle)) + goto out_err; + bof_decref(handle); + handle = NULL; + radeon_bo_map(ctx->radeon, ctx->bo[i]); + blob = bof_blob(ctx->bo[i]->size, ctx->bo[i]->data); + radeon_bo_unmap(ctx->radeon, ctx->bo[i]); + if (blob == NULL) + goto out_err; + if (bof_object_set(bo, "data", blob)) + goto out_err; + bof_decref(blob); + blob = NULL; + if (bof_array_append(array, bo)) + goto out_err; + bof_decref(bo); + bo = NULL; + } + if (bof_object_set(root, "bo", array)) + goto out_err; + bof_dump_file(root, file); +printf("done dump\n"); +out_err: + bof_decref(blob); + bof_decref(array); + bof_decref(bo); + bof_decref(size); + bof_decref(handle); + bof_decref(device_id); + bof_decref(root); +} diff --git a/src/gallium/winsys/drm/r600/core/radeon_draw.c b/src/gallium/winsys/drm/r600/core/radeon_draw.c new file mode 100644 index 00000000000..4413ed79fbd --- /dev/null +++ b/src/gallium/winsys/drm/r600/core/radeon_draw.c @@ -0,0 +1,141 @@ +/* + * Copyright 2010 Jerome Glisse <[email protected]> + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Jerome Glisse + */ +#include <stdlib.h> +#include <string.h> +#include <errno.h> +#include "radeon_priv.h" + +/* + * draw functions + */ +struct radeon_draw *radeon_draw(struct radeon *radeon) +{ + struct radeon_draw *draw; + + draw = calloc(1, sizeof(*draw)); + if (draw == NULL) + return NULL; + draw->nstate = radeon->nstate; + draw->radeon = radeon; + draw->refcount = 1; + draw->state = calloc(1, sizeof(void*) * draw->nstate); + if (draw->state == NULL) { + free(draw); + return NULL; + } + return draw; +} + +struct radeon_draw *radeon_draw_incref(struct radeon_draw *draw) +{ + draw->refcount++; + return draw; +} + +struct radeon_draw *radeon_draw_decref(struct radeon_draw *draw) +{ + unsigned i; + + if (draw == NULL) + return NULL; + if (--draw->refcount > 0) + return NULL; + for (i = 0; i < draw->nstate; i++) { + draw->state[i] = radeon_state_decref(draw->state[i]); + } + free(draw->state); + memset(draw, 0, sizeof(*draw)); + free(draw); + return NULL; +} + +int radeon_draw_set_new(struct radeon_draw *draw, struct radeon_state *state) +{ + if (state == NULL) + return 0; + if (state->type >= draw->radeon->ntype) + return -EINVAL; + draw->state[state->id] = radeon_state_decref(draw->state[state->id]); + draw->state[state->id] = state; + return 0; +} + +int radeon_draw_set(struct radeon_draw *draw, struct radeon_state *state) +{ + if (state == NULL) + return 0; + radeon_state_incref(state); + return radeon_draw_set_new(draw, state); +} + +int radeon_draw_check(struct radeon_draw *draw) +{ + unsigned i; + int r; + + r = radeon_draw_pm4(draw); + if (r) + return r; + for (i = 0, draw->cpm4 = 0; i < draw->nstate; i++) { + if (draw->state[i]) { + draw->cpm4 += draw->state[i]->cpm4; + } + } + return 0; +} + +struct radeon_draw *radeon_draw_duplicate(struct radeon_draw *draw) +{ + struct radeon_draw *ndraw; + unsigned i; + + if (draw == NULL) + return NULL; + ndraw = radeon_draw(draw->radeon); + if (ndraw == NULL) { + return NULL; + } + for (i = 0; i < draw->nstate; i++) { + if (radeon_draw_set(ndraw, draw->state[i])) { + radeon_draw_decref(ndraw); + return NULL; + } + } + return ndraw; +} + +int radeon_draw_pm4(struct radeon_draw *draw) +{ + unsigned i; + int r; + + for (i = 0; i < draw->nstate; i++) { + r = radeon_state_pm4(draw->state[i]); + if (r) + return r; + } + return 0; +} diff --git a/src/gallium/winsys/drm/r600/core/radeon_pciid.c b/src/gallium/winsys/drm/r600/core/radeon_pciid.c new file mode 100644 index 00000000000..dd6156d585e --- /dev/null +++ b/src/gallium/winsys/drm/r600/core/radeon_pciid.c @@ -0,0 +1,528 @@ +/* + * Copyright 2010 Jerome Glisse <[email protected]> + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Jerome Glisse + */ +#include <stdlib.h> +#include "radeon_priv.h" + +struct pci_id { + unsigned vendor; + unsigned device; + unsigned family; +}; + +struct pci_id radeon_pci_id[] = { + {0x1002, 0x3150, CHIP_RV380}, + {0x1002, 0x3152, CHIP_RV380}, + {0x1002, 0x3154, CHIP_RV380}, + {0x1002, 0x3E50, CHIP_RV380}, + {0x1002, 0x3E54, CHIP_RV380}, + {0x1002, 0x4136, CHIP_RS100}, + {0x1002, 0x4137, CHIP_RS200}, + {0x1002, 0x4144, CHIP_R300}, + {0x1002, 0x4145, CHIP_R300}, + {0x1002, 0x4146, CHIP_R300}, + {0x1002, 0x4147, CHIP_R300}, + {0x1002, 0x4148, CHIP_R350}, + {0x1002, 0x4149, CHIP_R350}, + {0x1002, 0x414A, CHIP_R350}, + {0x1002, 0x414B, CHIP_R350}, + {0x1002, 0x4150, CHIP_RV350}, + {0x1002, 0x4151, CHIP_RV350}, + {0x1002, 0x4152, CHIP_RV350}, + {0x1002, 0x4153, CHIP_RV350}, + {0x1002, 0x4154, CHIP_RV350}, + {0x1002, 0x4155, CHIP_RV350}, + {0x1002, 0x4156, CHIP_RV350}, + {0x1002, 0x4237, CHIP_RS200}, + {0x1002, 0x4242, CHIP_R200}, + {0x1002, 0x4243, CHIP_R200}, + {0x1002, 0x4336, CHIP_RS100}, + {0x1002, 0x4337, CHIP_RS200}, + {0x1002, 0x4437, CHIP_RS200}, + {0x1002, 0x4966, CHIP_RV250}, + {0x1002, 0x4967, CHIP_RV250}, + {0x1002, 0x4A48, CHIP_R420}, + {0x1002, 0x4A49, CHIP_R420}, + {0x1002, 0x4A4A, CHIP_R420}, + {0x1002, 0x4A4B, CHIP_R420}, + {0x1002, 0x4A4C, CHIP_R420}, + {0x1002, 0x4A4D, CHIP_R420}, + {0x1002, 0x4A4E, CHIP_R420}, + {0x1002, 0x4A4F, CHIP_R420}, + {0x1002, 0x4A50, CHIP_R420}, + {0x1002, 0x4A54, CHIP_R420}, + {0x1002, 0x4B48, CHIP_R420}, + {0x1002, 0x4B49, CHIP_R420}, + {0x1002, 0x4B4A, CHIP_R420}, + {0x1002, 0x4B4B, CHIP_R420}, + {0x1002, 0x4B4C, CHIP_R420}, + {0x1002, 0x4C57, CHIP_RV200}, + {0x1002, 0x4C58, CHIP_RV200}, + {0x1002, 0x4C59, CHIP_RV100}, + {0x1002, 0x4C5A, CHIP_RV100}, + {0x1002, 0x4C64, CHIP_RV250}, + {0x1002, 0x4C66, CHIP_RV250}, + {0x1002, 0x4C67, CHIP_RV250}, + {0x1002, 0x4E44, CHIP_R300}, + {0x1002, 0x4E45, CHIP_R300}, + {0x1002, 0x4E46, CHIP_R300}, + {0x1002, 0x4E47, CHIP_R300}, + {0x1002, 0x4E48, CHIP_R350}, + {0x1002, 0x4E49, CHIP_R350}, + {0x1002, 0x4E4A, CHIP_R350}, + {0x1002, 0x4E4B, CHIP_R350}, + {0x1002, 0x4E50, CHIP_RV350}, + {0x1002, 0x4E51, CHIP_RV350}, + {0x1002, 0x4E52, CHIP_RV350}, + {0x1002, 0x4E53, CHIP_RV350}, + {0x1002, 0x4E54, CHIP_RV350}, + {0x1002, 0x4E56, CHIP_RV350}, + {0x1002, 0x5144, CHIP_R100}, + {0x1002, 0x5145, CHIP_R100}, + {0x1002, 0x5146, CHIP_R100}, + {0x1002, 0x5147, CHIP_R100}, + {0x1002, 0x5148, CHIP_R200}, + {0x1002, 0x514C, CHIP_R200}, + {0x1002, 0x514D, CHIP_R200}, + {0x1002, 0x5157, CHIP_RV200}, + {0x1002, 0x5158, CHIP_RV200}, + {0x1002, 0x5159, CHIP_RV100}, + {0x1002, 0x515A, CHIP_RV100}, + {0x1002, 0x515E, CHIP_RV100}, + {0x1002, 0x5460, CHIP_RV380}, + {0x1002, 0x5462, CHIP_RV380}, + {0x1002, 0x5464, CHIP_RV380}, + {0x1002, 0x5657, CHIP_RV380}, + {0x1002, 0x5548, CHIP_R423}, + {0x1002, 0x5549, CHIP_R423}, + {0x1002, 0x554A, CHIP_R423}, + {0x1002, 0x554B, CHIP_R423}, + {0x1002, 0x554C, CHIP_R423}, + {0x1002, 0x554D, CHIP_R423}, + {0x1002, 0x554E, CHIP_R423}, + {0x1002, 0x554F, CHIP_R423}, + {0x1002, 0x5550, CHIP_R423}, + {0x1002, 0x5551, CHIP_R423}, + {0x1002, 0x5552, CHIP_R423}, + {0x1002, 0x5554, CHIP_R423}, + {0x1002, 0x564A, CHIP_RV410}, + {0x1002, 0x564B, CHIP_RV410}, + {0x1002, 0x564F, CHIP_RV410}, + {0x1002, 0x5652, CHIP_RV410}, + {0x1002, 0x5653, CHIP_RV410}, + {0x1002, 0x5834, CHIP_RS300}, + {0x1002, 0x5835, CHIP_RS300}, + {0x1002, 0x5954, CHIP_RS480}, + {0x1002, 0x5955, CHIP_RS480}, + {0x1002, 0x5974, CHIP_RS480}, + {0x1002, 0x5975, CHIP_RS480}, + {0x1002, 0x5960, CHIP_RV280}, + {0x1002, 0x5961, CHIP_RV280}, + {0x1002, 0x5962, CHIP_RV280}, + {0x1002, 0x5964, CHIP_RV280}, + {0x1002, 0x5965, CHIP_RV280}, + {0x1002, 0x5969, CHIP_RV100}, + {0x1002, 0x5a41, CHIP_RS400}, + {0x1002, 0x5a42, CHIP_RS400}, + {0x1002, 0x5a61, CHIP_RS400}, + {0x1002, 0x5a62, CHIP_RS400}, + {0x1002, 0x5b60, CHIP_RV380}, + {0x1002, 0x5b62, CHIP_RV380}, + {0x1002, 0x5b63, CHIP_RV380}, + {0x1002, 0x5b64, CHIP_RV380}, + {0x1002, 0x5b65, CHIP_RV380}, + {0x1002, 0x5c61, CHIP_RV280}, + {0x1002, 0x5c63, CHIP_RV280}, + {0x1002, 0x5d48, CHIP_R423}, + {0x1002, 0x5d49, CHIP_R423}, + {0x1002, 0x5d4a, CHIP_R423}, + {0x1002, 0x5d4c, CHIP_R423}, + {0x1002, 0x5d4d, CHIP_R423}, + {0x1002, 0x5d4e, CHIP_R423}, + {0x1002, 0x5d4f, CHIP_R423}, + {0x1002, 0x5d50, CHIP_R423}, + {0x1002, 0x5d52, CHIP_R423}, + {0x1002, 0x5d57, CHIP_R423}, + {0x1002, 0x5e48, CHIP_RV410}, + {0x1002, 0x5e4a, CHIP_RV410}, + {0x1002, 0x5e4b, CHIP_RV410}, + {0x1002, 0x5e4c, CHIP_RV410}, + {0x1002, 0x5e4d, CHIP_RV410}, + {0x1002, 0x5e4f, CHIP_RV410}, + {0x1002, 0x6880, CHIP_CYPRESS}, + {0x1002, 0x6888, CHIP_CYPRESS}, + {0x1002, 0x6889, CHIP_CYPRESS}, + {0x1002, 0x688A, CHIP_CYPRESS}, + {0x1002, 0x6898, CHIP_CYPRESS}, + {0x1002, 0x6899, CHIP_CYPRESS}, + {0x1002, 0x689c, CHIP_HEMLOCK}, + {0x1002, 0x689d, CHIP_HEMLOCK}, + {0x1002, 0x689e, CHIP_CYPRESS}, + {0x1002, 0x68a0, CHIP_JUNIPER}, + {0x1002, 0x68a1, CHIP_JUNIPER}, + {0x1002, 0x68a8, CHIP_JUNIPER}, + {0x1002, 0x68a9, CHIP_JUNIPER}, + {0x1002, 0x68b0, CHIP_JUNIPER}, + {0x1002, 0x68b8, CHIP_JUNIPER}, + {0x1002, 0x68b9, CHIP_JUNIPER}, + {0x1002, 0x68be, CHIP_JUNIPER}, + {0x1002, 0x68c0, CHIP_REDWOOD}, + {0x1002, 0x68c1, CHIP_REDWOOD}, + {0x1002, 0x68c8, CHIP_REDWOOD}, + {0x1002, 0x68c9, CHIP_REDWOOD}, + {0x1002, 0x68d8, CHIP_REDWOOD}, + {0x1002, 0x68d9, CHIP_REDWOOD}, + {0x1002, 0x68da, CHIP_REDWOOD}, + {0x1002, 0x68de, CHIP_REDWOOD}, + {0x1002, 0x68e0, CHIP_CEDAR}, + {0x1002, 0x68e1, CHIP_CEDAR}, + {0x1002, 0x68e4, CHIP_CEDAR}, + {0x1002, 0x68e5, CHIP_CEDAR}, + {0x1002, 0x68e8, CHIP_CEDAR}, + {0x1002, 0x68e9, CHIP_CEDAR}, + {0x1002, 0x68f1, CHIP_CEDAR}, + {0x1002, 0x68f8, CHIP_CEDAR}, + {0x1002, 0x68f9, CHIP_CEDAR}, + {0x1002, 0x68fe, CHIP_CEDAR}, + {0x1002, 0x7100, CHIP_R520}, + {0x1002, 0x7101, CHIP_R520}, + {0x1002, 0x7102, CHIP_R520}, + {0x1002, 0x7103, CHIP_R520}, + {0x1002, 0x7104, CHIP_R520}, + {0x1002, 0x7105, CHIP_R520}, + {0x1002, 0x7106, CHIP_R520}, + {0x1002, 0x7108, CHIP_R520}, + {0x1002, 0x7109, CHIP_R520}, + {0x1002, 0x710A, CHIP_R520}, + {0x1002, 0x710B, CHIP_R520}, + {0x1002, 0x710C, CHIP_R520}, + {0x1002, 0x710E, CHIP_R520}, + {0x1002, 0x710F, CHIP_R520}, + {0x1002, 0x7140, CHIP_RV515}, + {0x1002, 0x7141, CHIP_RV515}, + {0x1002, 0x7142, CHIP_RV515}, + {0x1002, 0x7143, CHIP_RV515}, + {0x1002, 0x7144, CHIP_RV515}, + {0x1002, 0x7145, CHIP_RV515}, + {0x1002, 0x7146, CHIP_RV515}, + {0x1002, 0x7147, CHIP_RV515}, + {0x1002, 0x7149, CHIP_RV515}, + {0x1002, 0x714A, CHIP_RV515}, + {0x1002, 0x714B, CHIP_RV515}, + {0x1002, 0x714C, CHIP_RV515}, + {0x1002, 0x714D, CHIP_RV515}, + {0x1002, 0x714E, CHIP_RV515}, + {0x1002, 0x714F, CHIP_RV515}, + {0x1002, 0x7151, CHIP_RV515}, + {0x1002, 0x7152, CHIP_RV515}, + {0x1002, 0x7153, CHIP_RV515}, + {0x1002, 0x715E, CHIP_RV515}, + {0x1002, 0x715F, CHIP_RV515}, + {0x1002, 0x7180, CHIP_RV515}, + {0x1002, 0x7181, CHIP_RV515}, + {0x1002, 0x7183, CHIP_RV515}, + {0x1002, 0x7186, CHIP_RV515}, + {0x1002, 0x7187, CHIP_RV515}, + {0x1002, 0x7188, CHIP_RV515}, + {0x1002, 0x718A, CHIP_RV515}, + {0x1002, 0x718B, CHIP_RV515}, + {0x1002, 0x718C, CHIP_RV515}, + {0x1002, 0x718D, CHIP_RV515}, + {0x1002, 0x718F, CHIP_RV515}, + {0x1002, 0x7193, CHIP_RV515}, + {0x1002, 0x7196, CHIP_RV515}, + {0x1002, 0x719B, CHIP_RV515}, + {0x1002, 0x719F, CHIP_RV515}, + {0x1002, 0x71C0, CHIP_RV530}, + {0x1002, 0x71C1, CHIP_RV530}, + {0x1002, 0x71C2, CHIP_RV530}, + {0x1002, 0x71C3, CHIP_RV530}, + {0x1002, 0x71C4, CHIP_RV530}, + {0x1002, 0x71C5, CHIP_RV530}, + {0x1002, 0x71C6, CHIP_RV530}, + {0x1002, 0x71C7, CHIP_RV530}, + {0x1002, 0x71CD, CHIP_RV530}, + {0x1002, 0x71CE, CHIP_RV530}, + {0x1002, 0x71D2, CHIP_RV530}, + {0x1002, 0x71D4, CHIP_RV530}, + {0x1002, 0x71D5, CHIP_RV530}, + {0x1002, 0x71D6, CHIP_RV530}, + {0x1002, 0x71DA, CHIP_RV530}, + {0x1002, 0x71DE, CHIP_RV530}, + {0x1002, 0x7200, CHIP_RV515}, + {0x1002, 0x7210, CHIP_RV515}, + {0x1002, 0x7211, CHIP_RV515}, + {0x1002, 0x7240, CHIP_R580}, + {0x1002, 0x7243, CHIP_R580}, + {0x1002, 0x7244, CHIP_R580}, + {0x1002, 0x7245, CHIP_R580}, + {0x1002, 0x7246, CHIP_R580}, + {0x1002, 0x7247, CHIP_R580}, + {0x1002, 0x7248, CHIP_R580}, + {0x1002, 0x7249, CHIP_R580}, + {0x1002, 0x724A, CHIP_R580}, + {0x1002, 0x724B, CHIP_R580}, + {0x1002, 0x724C, CHIP_R580}, + {0x1002, 0x724D, CHIP_R580}, + {0x1002, 0x724E, CHIP_R580}, + {0x1002, 0x724F, CHIP_R580}, + {0x1002, 0x7280, CHIP_RV570}, + {0x1002, 0x7281, CHIP_RV560}, + {0x1002, 0x7283, CHIP_RV560}, + {0x1002, 0x7284, CHIP_R580}, + {0x1002, 0x7287, CHIP_RV560}, + {0x1002, 0x7288, CHIP_RV570}, + {0x1002, 0x7289, CHIP_RV570}, + {0x1002, 0x728B, CHIP_RV570}, + {0x1002, 0x728C, CHIP_RV570}, + {0x1002, 0x7290, CHIP_RV560}, + {0x1002, 0x7291, CHIP_RV560}, + {0x1002, 0x7293, CHIP_RV560}, + {0x1002, 0x7297, CHIP_RV560}, + {0x1002, 0x7834, CHIP_RS300}, + {0x1002, 0x7835, CHIP_RS300}, + {0x1002, 0x791e, CHIP_RS690}, + {0x1002, 0x791f, CHIP_RS690}, + {0x1002, 0x793f, CHIP_RS600}, + {0x1002, 0x7941, CHIP_RS600}, + {0x1002, 0x7942, CHIP_RS600}, + {0x1002, 0x796c, CHIP_RS740}, + {0x1002, 0x796d, CHIP_RS740}, + {0x1002, 0x796e, CHIP_RS740}, + {0x1002, 0x796f, CHIP_RS740}, + {0x1002, 0x9400, CHIP_R600}, + {0x1002, 0x9401, CHIP_R600}, + {0x1002, 0x9402, CHIP_R600}, + {0x1002, 0x9403, CHIP_R600}, + {0x1002, 0x9405, CHIP_R600}, + {0x1002, 0x940A, CHIP_R600}, + {0x1002, 0x940B, CHIP_R600}, + {0x1002, 0x940F, CHIP_R600}, + {0x1002, 0x94A0, CHIP_RV740}, + {0x1002, 0x94A1, CHIP_RV740}, + {0x1002, 0x94A3, CHIP_RV740}, + {0x1002, 0x94B1, CHIP_RV740}, + {0x1002, 0x94B3, CHIP_RV740}, + {0x1002, 0x94B4, CHIP_RV740}, + {0x1002, 0x94B5, CHIP_RV740}, + {0x1002, 0x94B9, CHIP_RV740}, + {0x1002, 0x9440, CHIP_RV770}, + {0x1002, 0x9441, CHIP_RV770}, + {0x1002, 0x9442, CHIP_RV770}, + {0x1002, 0x9443, CHIP_RV770}, + {0x1002, 0x9444, CHIP_RV770}, + {0x1002, 0x9446, CHIP_RV770}, + {0x1002, 0x944A, CHIP_RV770}, + {0x1002, 0x944B, CHIP_RV770}, + {0x1002, 0x944C, CHIP_RV770}, + {0x1002, 0x944E, CHIP_RV770}, + {0x1002, 0x9450, CHIP_RV770}, + {0x1002, 0x9452, CHIP_RV770}, + {0x1002, 0x9456, CHIP_RV770}, + {0x1002, 0x945A, CHIP_RV770}, + {0x1002, 0x945B, CHIP_RV770}, + {0x1002, 0x9460, CHIP_RV770}, + {0x1002, 0x9462, CHIP_RV770}, + {0x1002, 0x946A, CHIP_RV770}, + {0x1002, 0x946B, CHIP_RV770}, + {0x1002, 0x947A, CHIP_RV770}, + {0x1002, 0x947B, CHIP_RV770}, + {0x1002, 0x9480, CHIP_RV730}, + {0x1002, 0x9487, CHIP_RV730}, + {0x1002, 0x9488, CHIP_RV730}, + {0x1002, 0x9489, CHIP_RV730}, + {0x1002, 0x948F, CHIP_RV730}, + {0x1002, 0x9490, CHIP_RV730}, + {0x1002, 0x9491, CHIP_RV730}, + {0x1002, 0x9495, CHIP_RV730}, + {0x1002, 0x9498, CHIP_RV730}, + {0x1002, 0x949C, CHIP_RV730}, + {0x1002, 0x949E, CHIP_RV730}, + {0x1002, 0x949F, CHIP_RV730}, + {0x1002, 0x94C0, CHIP_RV610}, + {0x1002, 0x94C1, CHIP_RV610}, + {0x1002, 0x94C3, CHIP_RV610}, + {0x1002, 0x94C4, CHIP_RV610}, + {0x1002, 0x94C5, CHIP_RV610}, + {0x1002, 0x94C6, CHIP_RV610}, + {0x1002, 0x94C7, CHIP_RV610}, + {0x1002, 0x94C8, CHIP_RV610}, + {0x1002, 0x94C9, CHIP_RV610}, + {0x1002, 0x94CB, CHIP_RV610}, + {0x1002, 0x94CC, CHIP_RV610}, + {0x1002, 0x94CD, CHIP_RV610}, + {0x1002, 0x9500, CHIP_RV670}, + {0x1002, 0x9501, CHIP_RV670}, + {0x1002, 0x9504, CHIP_RV670}, + {0x1002, 0x9505, CHIP_RV670}, + {0x1002, 0x9506, CHIP_RV670}, + {0x1002, 0x9507, CHIP_RV670}, + {0x1002, 0x9508, CHIP_RV670}, + {0x1002, 0x9509, CHIP_RV670}, + {0x1002, 0x950F, CHIP_RV670}, + {0x1002, 0x9511, CHIP_RV670}, + {0x1002, 0x9515, CHIP_RV670}, + {0x1002, 0x9517, CHIP_RV670}, + {0x1002, 0x9519, CHIP_RV670}, + {0x1002, 0x9540, CHIP_RV710}, + {0x1002, 0x9541, CHIP_RV710}, + {0x1002, 0x9542, CHIP_RV710}, + {0x1002, 0x954E, CHIP_RV710}, + {0x1002, 0x954F, CHIP_RV710}, + {0x1002, 0x9552, CHIP_RV710}, + {0x1002, 0x9553, CHIP_RV710}, + {0x1002, 0x9555, CHIP_RV710}, + {0x1002, 0x9557, CHIP_RV710}, + {0x1002, 0x9580, CHIP_RV630}, + {0x1002, 0x9581, CHIP_RV630}, + {0x1002, 0x9583, CHIP_RV630}, + {0x1002, 0x9586, CHIP_RV630}, + {0x1002, 0x9587, CHIP_RV630}, + {0x1002, 0x9588, CHIP_RV630}, + {0x1002, 0x9589, CHIP_RV630}, + {0x1002, 0x958A, CHIP_RV630}, + {0x1002, 0x958B, CHIP_RV630}, + {0x1002, 0x958C, CHIP_RV630}, + {0x1002, 0x958D, CHIP_RV630}, + {0x1002, 0x958E, CHIP_RV630}, + {0x1002, 0x958F, CHIP_RV630}, + {0x1002, 0x9590, CHIP_RV635}, + {0x1002, 0x9591, CHIP_RV635}, + {0x1002, 0x9593, CHIP_RV635}, + {0x1002, 0x9595, CHIP_RV635}, + {0x1002, 0x9596, CHIP_RV635}, + {0x1002, 0x9597, CHIP_RV635}, + {0x1002, 0x9598, CHIP_RV635}, + {0x1002, 0x9599, CHIP_RV635}, + {0x1002, 0x959B, CHIP_RV635}, + {0x1002, 0x95C0, CHIP_RV620}, + {0x1002, 0x95C2, CHIP_RV620}, + {0x1002, 0x95C4, CHIP_RV620}, + {0x1002, 0x95C5, CHIP_RV620}, + {0x1002, 0x95C6, CHIP_RV620}, + {0x1002, 0x95C7, CHIP_RV620}, + {0x1002, 0x95C9, CHIP_RV620}, + {0x1002, 0x95CC, CHIP_RV620}, + {0x1002, 0x95CD, CHIP_RV620}, + {0x1002, 0x95CE, CHIP_RV620}, + {0x1002, 0x95CF, CHIP_RV620}, + {0x1002, 0x9610, CHIP_RS780}, + {0x1002, 0x9611, CHIP_RS780}, + {0x1002, 0x9612, CHIP_RS780}, + {0x1002, 0x9613, CHIP_RS780}, + {0x1002, 0x9614, CHIP_RS780}, + {0x1002, 0x9615, CHIP_RS780}, + {0x1002, 0x9616, CHIP_RS780}, + {0x1002, 0x9710, CHIP_RS880}, + {0x1002, 0x9711, CHIP_RS880}, + {0x1002, 0x9712, CHIP_RS880}, + {0x1002, 0x9713, CHIP_RS880}, + {0x1002, 0x9714, CHIP_RS880}, + {0x1002, 0x9715, CHIP_RS880}, + {0, 0}, +}; + +unsigned radeon_family_from_device(unsigned device) +{ + unsigned i; + + for (i = 0; ; i++) { + if (!radeon_pci_id[i].vendor) + return CHIP_UNKNOWN; + if (radeon_pci_id[i].device == device) + return radeon_pci_id[i].family; + } + return CHIP_UNKNOWN; +} + +int radeon_is_family_compatible(unsigned family1, unsigned family2) +{ + switch (family1) { + case CHIP_R600: + case CHIP_RV610: + case CHIP_RV630: + case CHIP_RV670: + case CHIP_RV620: + case CHIP_RV635: + case CHIP_RS780: + case CHIP_RS880: + case CHIP_RV770: + case CHIP_RV730: + case CHIP_RV710: + case CHIP_RV740: + switch (family2) { + case CHIP_R600: + case CHIP_RV610: + case CHIP_RV630: + case CHIP_RV670: + case CHIP_RV620: + case CHIP_RV635: + case CHIP_RS780: + case CHIP_RS880: + case CHIP_RV770: + case CHIP_RV730: + case CHIP_RV710: + case CHIP_RV740: + return 1; + default: + return 0; + } + break; + case CHIP_R100: + case CHIP_RV100: + case CHIP_RS100: + case CHIP_RV200: + case CHIP_RS200: + case CHIP_R200: + case CHIP_RV250: + case CHIP_RS300: + case CHIP_RV280: + case CHIP_R300: + case CHIP_R350: + case CHIP_RV350: + case CHIP_RV380: + case CHIP_R420: + case CHIP_R423: + case CHIP_RV410: + case CHIP_RS400: + case CHIP_RS480: + case CHIP_RS600: + case CHIP_RS690: + case CHIP_RS740: + case CHIP_RV515: + case CHIP_R520: + case CHIP_RV530: + case CHIP_RV560: + case CHIP_RV570: + case CHIP_R580: + case CHIP_CEDAR: + case CHIP_REDWOOD: + case CHIP_JUNIPER: + case CHIP_CYPRESS: + case CHIP_HEMLOCK: + default: + return 0; + } +} diff --git a/src/gallium/winsys/drm/r600/core/radeon_priv.h b/src/gallium/winsys/drm/r600/core/radeon_priv.h new file mode 100644 index 00000000000..b91421f4389 --- /dev/null +++ b/src/gallium/winsys/drm/r600/core/radeon_priv.h @@ -0,0 +1,130 @@ +/* + * Copyright © 2009 Jerome Glisse <[email protected]> + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License + * as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software Foundation, + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. + */ +#ifndef RADEON_PRIV_H +#define RADEON_PRIV_H + +#include <stdint.h> +#include "xf86drm.h" +#include "xf86drmMode.h" +#include <errno.h> +#include "radeon.h" + +struct radeon; +struct radeon_ctx; + +/* + * radeon functions + */ +typedef int (*radeon_state_pm4_t)(struct radeon_state *state); +struct radeon_register { + unsigned offset; + unsigned need_reloc; + unsigned bo_id; + char name[64]; +}; + +struct radeon_type { + unsigned npm4; + unsigned id; + unsigned range_start; + unsigned range_end; + unsigned stride; + unsigned immediate; + char name[64]; + unsigned nstates; + radeon_state_pm4_t pm4; + const struct radeon_register *regs; +}; + +struct radeon { + int fd; + int refcount; + unsigned device; + unsigned family; + unsigned nstate; + unsigned ntype; + const struct radeon_type *type; +}; + +extern struct radeon *radeon_new(int fd, unsigned device); +extern struct radeon *radeon_incref(struct radeon *radeon); +extern struct radeon *radeon_decref(struct radeon *radeon); +extern unsigned radeon_family_from_device(unsigned device); +extern int radeon_is_family_compatible(unsigned family1, unsigned family2); +extern int radeon_reg_id(struct radeon *radeon, unsigned offset, unsigned *typeid, unsigned *stateid, unsigned *id); +extern unsigned radeon_type_from_id(struct radeon *radeon, unsigned id); + +/* + * radeon context functions + */ +#pragma pack(1) +struct radeon_cs_reloc { + uint32_t handle; + uint32_t read_domain; + uint32_t write_domain; + uint32_t flags; +}; +#pragma pack() + +struct radeon_ctx { + int refcount; + struct radeon *radeon; + u32 *pm4; + u32 cpm4; + u32 draw_cpm4; + unsigned id; + unsigned next_id; + unsigned nreloc; + struct radeon_cs_reloc *reloc; + unsigned nbo; + struct radeon_bo **bo; + unsigned ndraw; + struct radeon_draw *cdraw; + struct radeon_draw **draw; + unsigned nstate; + struct radeon_state **state; +}; + +int radeon_ctx_set_bo_new(struct radeon_ctx *ctx, struct radeon_bo *bo); +struct radeon_bo *radeon_ctx_get_bo(struct radeon_ctx *ctx, unsigned reloc); +void radeon_ctx_get_placement(struct radeon_ctx *ctx, unsigned reloc, u32 *placement); +int radeon_ctx_set_draw_new(struct radeon_ctx *ctx, struct radeon_draw *draw); +int radeon_ctx_draw(struct radeon_ctx *ctx); + +/* + * r600/r700 context functions + */ +extern int r600_init(struct radeon *radeon); +extern int r600_ctx_draw(struct radeon_ctx *ctx); +extern int r600_ctx_next_reloc(struct radeon_ctx *ctx, unsigned *reloc); + +/* + * radeon state functions + */ +extern u32 radeon_state_register_get(struct radeon_state *state, unsigned offset); +extern int radeon_state_register_set(struct radeon_state *state, unsigned offset, u32 value); +extern struct radeon_state *radeon_state_duplicate(struct radeon_state *state); +extern int radeon_state_replace_always(struct radeon_state *ostate, struct radeon_state *nstate); +extern int radeon_state_pm4_generic(struct radeon_state *state); +extern int radeon_state_reloc(struct radeon_state *state, unsigned id, unsigned bo_id); + +/* + * radeon draw functions + */ +extern int radeon_draw_pm4(struct radeon_draw *draw); + +#endif diff --git a/src/gallium/winsys/drm/r600/core/radeon_state.c b/src/gallium/winsys/drm/r600/core/radeon_state.c new file mode 100644 index 00000000000..308288557a4 --- /dev/null +++ b/src/gallium/winsys/drm/r600/core/radeon_state.c @@ -0,0 +1,168 @@ +/* + * Copyright 2010 Jerome Glisse <[email protected]> + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Jerome Glisse + */ +#include <stdio.h> +#include <stdlib.h> +#include <string.h> +#include <errno.h> +#include "radeon_priv.h" + +/* + * state core functions + */ +struct radeon_state *radeon_state(struct radeon *radeon, u32 type, u32 id) +{ + struct radeon_state *state; + + if (type > radeon->ntype) { + fprintf(stderr, "%s invalid type %d\n", __func__, type); + return NULL; + } + if (id > radeon->nstate) { + fprintf(stderr, "%s invalid state id %d\n", __func__, id); + return NULL; + } + state = calloc(1, sizeof(*state)); + if (state == NULL) + return NULL; + state->radeon = radeon; + state->type = type; + state->id = id; + state->refcount = 1; + state->npm4 = radeon->type[type].npm4; + state->nstates = radeon->type[type].nstates; + state->states = calloc(1, state->nstates * 4); + state->pm4 = calloc(1, radeon->type[type].npm4 * 4); + if (state->states == NULL || state->pm4 == NULL) { + radeon_state_decref(state); + return NULL; + } + return state; +} + +struct radeon_state *radeon_state_duplicate(struct radeon_state *state) +{ + struct radeon_state *nstate = radeon_state(state->radeon, state->type, state->id); + unsigned i; + + if (state == NULL) + return NULL; + nstate->cpm4 = state->cpm4; + nstate->nbo = state->nbo; + nstate->nreloc = state->nreloc; + memcpy(nstate->states, state->states, state->nstates * 4); + memcpy(nstate->pm4, state->pm4, state->npm4 * 4); + memcpy(nstate->placement, state->placement, 8 * 4); + memcpy(nstate->reloc_pm4_id, state->reloc_pm4_id, 8 * 4); + memcpy(nstate->reloc_bo_id, state->reloc_bo_id, 8 * 4); + memcpy(nstate->bo_dirty, state->bo_dirty, 4 * 4); + for (i = 0; i < state->nbo; i++) { + nstate->bo[i] = radeon_bo_incref(state->radeon, state->bo[i]); + } + return nstate; +} + +struct radeon_state *radeon_state_incref(struct radeon_state *state) +{ + state->refcount++; + return state; +} + +struct radeon_state *radeon_state_decref(struct radeon_state *state) +{ + unsigned i; + + if (state == NULL) + return NULL; + if (--state->refcount > 0) { + return NULL; + } + for (i = 0; i < state->nbo; i++) { + state->bo[i] = radeon_bo_decref(state->radeon, state->bo[i]); + } + free(state->immd); + free(state->states); + free(state->pm4); + memset(state, 0, sizeof(*state)); + free(state); + return NULL; +} + +int radeon_state_replace_always(struct radeon_state *ostate, + struct radeon_state *nstate) +{ + return 1; +} + +int radeon_state_pm4_generic(struct radeon_state *state) +{ + return -EINVAL; +} + +static u32 crc32(void *d, size_t len) +{ + u16 *data = (uint16_t*)d; + u32 sum1 = 0xffff, sum2 = 0xffff; + + len = len >> 1; + while (len) { + unsigned tlen = len > 360 ? 360 : len; + len -= tlen; + do { + sum1 += *data++; + sum2 += sum1; + } while (--tlen); + sum1 = (sum1 & 0xffff) + (sum1 >> 16); + sum2 = (sum2 & 0xffff) + (sum2 >> 16); + } + /* Second reduction step to reduce sums to 16 bits */ + sum1 = (sum1 & 0xffff) + (sum1 >> 16); + sum2 = (sum2 & 0xffff) + (sum2 >> 16); + return sum2 << 16 | sum1; +} + +int radeon_state_pm4(struct radeon_state *state) +{ + int r; + + if (state == NULL || state->cpm4) + return 0; + r = state->radeon->type[state->type].pm4(state); + if (r) { + fprintf(stderr, "%s failed to build PM4 for state(%d %d)\n", + __func__, state->type, state->id); + return r; + } + state->pm4_crc = crc32(state->pm4, state->cpm4 * 4); + return 0; +} + +int radeon_state_reloc(struct radeon_state *state, unsigned id, unsigned bo_id) +{ + state->reloc_pm4_id[state->nreloc] = id; + state->reloc_bo_id[state->nreloc] = bo_id; + state->nreloc++; + return 0; +} diff --git a/src/gallium/winsys/drm/r600/dri/Makefile b/src/gallium/winsys/drm/r600/dri/Makefile new file mode 100644 index 00000000000..01db99399a0 --- /dev/null +++ b/src/gallium/winsys/drm/r600/dri/Makefile @@ -0,0 +1,20 @@ +TOP = ../../../../../.. +include $(TOP)/configs/current + +LIBNAME = r600_dri.so + +PIPE_DRIVERS = \ + $(TOP)/src/gallium/state_trackers/dri/libdridrm.a \ + $(TOP)/src/gallium/winsys/drm/r600/core/libr600winsys.a \ + $(TOP)/src/gallium/drivers/trace/libtrace.a \ + $(TOP)/src/gallium/drivers/softpipe/libsoftpipe.a \ + $(TOP)/src/gallium/drivers/r600/libr600.a + +C_SOURCES = \ + $(COMMON_GALLIUM_SOURCES) \ + $(DRIVER_SOURCES) + +include ../../Makefile.template + +symlinks: $(TOP)/$(LIB_DIR)/gallium + @rm -f $(TOP)/$(LIB_DIR)/gallium/r600_dri.so diff --git a/src/gallium/winsys/drm/r600/dri/SConscript b/src/gallium/winsys/drm/r600/dri/SConscript new file mode 100644 index 00000000000..c4989d1b595 --- /dev/null +++ b/src/gallium/winsys/drm/r600/dri/SConscript @@ -0,0 +1,17 @@ +Import('*') + +env = drienv.Clone() + +env.ParseConfig('pkg-config --cflags --libs libdrm_radeon') + +drivers = [ + trace, + softpipe, + r300 +] + +env.SharedLibrary( + target ='radeon_dri.so', + source = COMMON_GALLIUM_SOURCES, + LIBS = st_dri + radeonwinsys + mesa + drivers + gallium + env['LIBS'], +) diff --git a/src/gallium/winsys/drm/r600/egl/Makefile b/src/gallium/winsys/drm/r600/egl/Makefile new file mode 100644 index 00000000000..cd4f9b20f06 --- /dev/null +++ b/src/gallium/winsys/drm/r600/egl/Makefile @@ -0,0 +1,14 @@ +TOP = ../../../../../.. +include $(TOP)/configs/current + +EGL_DRIVER_NAME = radeon +EGL_DRIVER_SOURCES = dummy.c +EGL_DRIVER_LIBS = -ldrm_radeon + +EGL_DRIVER_PIPES = \ + $(TOP)/src/gallium/winsys/drm/radeon/core/libradeonwinsys.a \ + $(TOP)/src/gallium/drivers/softpipe/libsoftpipe.a \ + $(TOP)/src/gallium/drivers/trace/libtrace.a \ + $(TOP)/src/gallium/drivers/r300/libr300.a + +include ../../Makefile.egl diff --git a/src/gallium/winsys/drm/r600/egl/dummy.c b/src/gallium/winsys/drm/r600/egl/dummy.c new file mode 100644 index 00000000000..4a1bc28b0b6 --- /dev/null +++ b/src/gallium/winsys/drm/r600/egl/dummy.c @@ -0,0 +1 @@ +/* mklib expects at least one object file */ diff --git a/src/gallium/winsys/drm/r600/python/README b/src/gallium/winsys/drm/r600/python/README new file mode 100644 index 00000000000..d9e49bce67b --- /dev/null +++ b/src/gallium/winsys/drm/r600/python/README @@ -0,0 +1,15 @@ +Python bindings for the radeon gallium driver. + + +See gallium/src/gallium/state_trackers/python/README for more information. + + +Build as: + + scons debug=1 statetrackers=python winsys=drm/radeon/python + +Run as: + + export PYTHONPATH=$PWD/build/linux-x86-debug/gallium/winsys/drm/radeon/python:$PWD/build/linux-x86-debug/gallium/state_trackers/python + + python src/gallium/state_trackers/python/samples/tri.py diff --git a/src/gallium/winsys/drm/r600/python/SConscript b/src/gallium/winsys/drm/r600/python/SConscript new file mode 100644 index 00000000000..91cae986975 --- /dev/null +++ b/src/gallium/winsys/drm/r600/python/SConscript @@ -0,0 +1,33 @@ +import os.path + +Import('*') + +if env['platform'] == 'linux': + + env = env.Clone() + + env.Tool('python') + + env.ParseConfig('pkg-config --cflags --libs libdrm') + + env.Prepend(CPPPATH = [ + '#src/gallium/state_trackers/python', + '../core', + ]) + + drivers = [ + softpipe, + radeon, + trace, + ] + + sources = [ + 'radeon_hardpipe_winsys.c', + 'xf86dri.c', + ] + + env.SharedLibrary( + target ='_gallium', + source = sources, + LIBS = [pyst] + drivers + gallium + env['LIBS'], + ) diff --git a/src/gallium/winsys/drm/r600/python/radeon_hardpipe_winsys.c b/src/gallium/winsys/drm/r600/python/radeon_hardpipe_winsys.c new file mode 100644 index 00000000000..fc63081a4cc --- /dev/null +++ b/src/gallium/winsys/drm/r600/python/radeon_hardpipe_winsys.c @@ -0,0 +1,132 @@ + /************************************************************************** + * + * Copyright 2009 VMware, Inc. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. + * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR + * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + **************************************************************************/ + + +#include <stdio.h> +#include <string.h> +#include <stdlib.h> + +#include <X11/X.h> +#include <X11/Xlib.h> +#include <drm/drm.h> + +#include "pipe/p_screen.h" +#include "pipe/p_context.h" + +#include "st_winsys.h" + +#include "radeon_winsys.h" + +#include "xf86dri.h" + + +/* XXX: Force init_gallium symbol to be linked */ +extern void init_gallium(void); +void (*force_init_gallium_linkage)(void) = &init_gallium; + + +static struct pipe_screen * +radeon_hardpipe_screen_create(void) +{ + Display *dpy; + Window rootWin; + XWindowAttributes winAttr; + int isCapable; + int screen; + char *driverName; + char *curBusID; + unsigned magic; + int ddxDriverMajor; + int ddxDriverMinor; + int ddxDriverPatch; + drm_handle_t sAreaOffset; + int ret; + int drmFD; + drm_context_t hHWContext; + XID id; + + dpy = XOpenDisplay(":0"); + if (!dpy) { + fprintf(stderr, "Open Display Failed\n"); + return NULL; + } + + screen = DefaultScreen(dpy); + rootWin = RootWindow(dpy, screen); + XGetWindowAttributes(dpy, rootWin, &winAttr); + + ret = uniDRIQueryDirectRenderingCapable(dpy, screen, &isCapable); + if (!ret || !isCapable) { + fprintf(stderr, "No DRI on this display:sceen\n"); + goto error; + } + + if (!uniDRIOpenConnection(dpy, screen, &sAreaOffset, + &curBusID)) { + fprintf(stderr, "Could not open DRI connection.\n"); + goto error; + } + + if (!uniDRIGetClientDriverName(dpy, screen, &ddxDriverMajor, + &ddxDriverMinor, &ddxDriverPatch, + &driverName)) { + fprintf(stderr, "Could not get DRI driver name.\n"); + goto error; + } + + if ((drmFD = drmOpen(NULL, curBusID)) < 0) { + perror("DRM Device could not be opened"); + goto error; + } + + drmGetMagic(drmFD, &magic); + if (!uniDRIAuthConnection(dpy, screen, magic)) { + fprintf(stderr, "Could not get X server to authenticate us.\n"); + goto error; + } + + if (!uniDRICreateContext(dpy, screen, winAttr.visual, + &id, &hHWContext)) { + fprintf(stderr, "Could not create DRI context.\n"); + goto error; + } + + /* FIXME: create a radeon pipe_screen from drmFD and hHWContext */ + + return NULL; + +error: + return NULL; +} + + + + +const struct st_winsys st_hardpipe_winsys = { + &radeon_hardpipe_screen_create, +}; + diff --git a/src/gallium/winsys/drm/r600/python/xf86dri.c b/src/gallium/winsys/drm/r600/python/xf86dri.c new file mode 100644 index 00000000000..1736f1e54f8 --- /dev/null +++ b/src/gallium/winsys/drm/r600/python/xf86dri.c @@ -0,0 +1,605 @@ +/************************************************************************** + +Copyright 1998-1999 Precision Insight, Inc., Cedar Park, Texas. +Copyright 2000 VA Linux Systems, Inc. +All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a +copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sub license, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice (including the +next paragraph) shall be included in all copies or substantial portions +of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. +IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR +ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ + +/* + * Authors: + * Kevin E. Martin <[email protected]> + * Jens Owen <[email protected]> + * Rickard E. (Rik) Faith <[email protected]> + * + */ + +/* THIS IS NOT AN X CONSORTIUM STANDARD */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#define NEED_REPLIES +#include <X11/Xlibint.h> +#include <X11/extensions/Xext.h> +#include <X11/extensions/extutil.h> +#include "xf86dristr.h" + +static XExtensionInfo _xf86dri_info_data; +static XExtensionInfo *xf86dri_info = &_xf86dri_info_data; +static char xf86dri_extension_name[] = XF86DRINAME; + +#define uniDRICheckExtension(dpy,i,val) \ + XextCheckExtension (dpy, i, xf86dri_extension_name, val) + +/***************************************************************************** + * * + * private utility routines * + * * + *****************************************************************************/ + +static int close_display(Display * dpy, XExtCodes * extCodes); +static /* const */ XExtensionHooks xf86dri_extension_hooks = { + NULL, /* create_gc */ + NULL, /* copy_gc */ + NULL, /* flush_gc */ + NULL, /* free_gc */ + NULL, /* create_font */ + NULL, /* free_font */ + close_display, /* close_display */ + NULL, /* wire_to_event */ + NULL, /* event_to_wire */ + NULL, /* error */ + NULL, /* error_string */ +}; + +static +XEXT_GENERATE_FIND_DISPLAY(find_display, xf86dri_info, + xf86dri_extension_name, &xf86dri_extension_hooks, + 0, NULL) + + static XEXT_GENERATE_CLOSE_DISPLAY(close_display, xf86dri_info) + +/***************************************************************************** + * * + * public XFree86-DRI Extension routines * + * * + *****************************************************************************/ +#if 0 +#include <stdio.h> +#define TRACE(msg) fprintf(stderr,"uniDRI%s\n", msg); +#else +#define TRACE(msg) +#endif + Bool uniDRIQueryExtension(dpy, event_basep, error_basep) + Display *dpy; + int *event_basep, *error_basep; +{ + XExtDisplayInfo *info = find_display(dpy); + + TRACE("QueryExtension..."); + if (XextHasExtension(info)) { + *event_basep = info->codes->first_event; + *error_basep = info->codes->first_error; + TRACE("QueryExtension... return True"); + return True; + } else { + TRACE("QueryExtension... return False"); + return False; + } +} + +Bool +uniDRIQueryVersion(dpy, majorVersion, minorVersion, patchVersion) + Display *dpy; + int *majorVersion; + int *minorVersion; + int *patchVersion; +{ + XExtDisplayInfo *info = find_display(dpy); + xXF86DRIQueryVersionReply rep; + xXF86DRIQueryVersionReq *req; + + TRACE("QueryVersion..."); + uniDRICheckExtension(dpy, info, False); + + LockDisplay(dpy); + GetReq(XF86DRIQueryVersion, req); + req->reqType = info->codes->major_opcode; + req->driReqType = X_XF86DRIQueryVersion; + if (!_XReply(dpy, (xReply *) & rep, 0, xFalse)) { + UnlockDisplay(dpy); + SyncHandle(); + TRACE("QueryVersion... return False"); + return False; + } + *majorVersion = rep.majorVersion; + *minorVersion = rep.minorVersion; + *patchVersion = rep.patchVersion; + UnlockDisplay(dpy); + SyncHandle(); + TRACE("QueryVersion... return True"); + return True; +} + +Bool +uniDRIQueryDirectRenderingCapable(dpy, screen, isCapable) + Display *dpy; + int screen; + Bool *isCapable; +{ + XExtDisplayInfo *info = find_display(dpy); + xXF86DRIQueryDirectRenderingCapableReply rep; + xXF86DRIQueryDirectRenderingCapableReq *req; + + TRACE("QueryDirectRenderingCapable..."); + uniDRICheckExtension(dpy, info, False); + + LockDisplay(dpy); + GetReq(XF86DRIQueryDirectRenderingCapable, req); + req->reqType = info->codes->major_opcode; + req->driReqType = X_XF86DRIQueryDirectRenderingCapable; + req->screen = screen; + if (!_XReply(dpy, (xReply *) & rep, 0, xFalse)) { + UnlockDisplay(dpy); + SyncHandle(); + TRACE("QueryDirectRenderingCapable... return False"); + return False; + } + *isCapable = rep.isCapable; + UnlockDisplay(dpy); + SyncHandle(); + TRACE("QueryDirectRenderingCapable... return True"); + return True; +} + +Bool +uniDRIOpenConnection(dpy, screen, hSAREA, busIdString) + Display *dpy; + int screen; + drm_handle_t *hSAREA; + char **busIdString; +{ + XExtDisplayInfo *info = find_display(dpy); + xXF86DRIOpenConnectionReply rep; + xXF86DRIOpenConnectionReq *req; + + TRACE("OpenConnection..."); + uniDRICheckExtension(dpy, info, False); + + LockDisplay(dpy); + GetReq(XF86DRIOpenConnection, req); + req->reqType = info->codes->major_opcode; + req->driReqType = X_XF86DRIOpenConnection; + req->screen = screen; + if (!_XReply(dpy, (xReply *) & rep, 0, xFalse)) { + UnlockDisplay(dpy); + SyncHandle(); + TRACE("OpenConnection... return False"); + return False; + } + + *hSAREA = rep.hSAREALow; +#ifdef LONG64 + if (sizeof(drm_handle_t) == 8) { + *hSAREA |= ((unsigned long)rep.hSAREAHigh) << 32; + } +#endif + if (rep.length) { + if (!(*busIdString = (char *)Xcalloc(rep.busIdStringLength + 1, 1))) { + _XEatData(dpy, ((rep.busIdStringLength + 3) & ~3)); + UnlockDisplay(dpy); + SyncHandle(); + TRACE("OpenConnection... return False"); + return False; + } + _XReadPad(dpy, *busIdString, rep.busIdStringLength); + } else { + *busIdString = NULL; + } + UnlockDisplay(dpy); + SyncHandle(); + TRACE("OpenConnection... return True"); + return True; +} + +Bool +uniDRIAuthConnection(dpy, screen, magic) + Display *dpy; + int screen; + drm_magic_t magic; +{ + XExtDisplayInfo *info = find_display(dpy); + xXF86DRIAuthConnectionReq *req; + xXF86DRIAuthConnectionReply rep; + + TRACE("AuthConnection..."); + uniDRICheckExtension(dpy, info, False); + + LockDisplay(dpy); + GetReq(XF86DRIAuthConnection, req); + req->reqType = info->codes->major_opcode; + req->driReqType = X_XF86DRIAuthConnection; + req->screen = screen; + req->magic = magic; + rep.authenticated = 0; + if (!_XReply(dpy, (xReply *) & rep, 0, xFalse) || !rep.authenticated) { + UnlockDisplay(dpy); + SyncHandle(); + TRACE("AuthConnection... return False"); + return False; + } + UnlockDisplay(dpy); + SyncHandle(); + TRACE("AuthConnection... return True"); + return True; +} + +Bool +uniDRICloseConnection(dpy, screen) + Display *dpy; + int screen; +{ + XExtDisplayInfo *info = find_display(dpy); + xXF86DRICloseConnectionReq *req; + + TRACE("CloseConnection..."); + + uniDRICheckExtension(dpy, info, False); + + LockDisplay(dpy); + GetReq(XF86DRICloseConnection, req); + req->reqType = info->codes->major_opcode; + req->driReqType = X_XF86DRICloseConnection; + req->screen = screen; + UnlockDisplay(dpy); + SyncHandle(); + TRACE("CloseConnection... return True"); + return True; +} + +Bool +uniDRIGetClientDriverName(dpy, screen, ddxDriverMajorVersion, + ddxDriverMinorVersion, ddxDriverPatchVersion, + clientDriverName) + Display *dpy; + int screen; + int *ddxDriverMajorVersion; + int *ddxDriverMinorVersion; + int *ddxDriverPatchVersion; + char **clientDriverName; +{ + XExtDisplayInfo *info = find_display(dpy); + xXF86DRIGetClientDriverNameReply rep; + xXF86DRIGetClientDriverNameReq *req; + + TRACE("GetClientDriverName..."); + uniDRICheckExtension(dpy, info, False); + + LockDisplay(dpy); + GetReq(XF86DRIGetClientDriverName, req); + req->reqType = info->codes->major_opcode; + req->driReqType = X_XF86DRIGetClientDriverName; + req->screen = screen; + if (!_XReply(dpy, (xReply *) & rep, 0, xFalse)) { + UnlockDisplay(dpy); + SyncHandle(); + TRACE("GetClientDriverName... return False"); + return False; + } + + *ddxDriverMajorVersion = rep.ddxDriverMajorVersion; + *ddxDriverMinorVersion = rep.ddxDriverMinorVersion; + *ddxDriverPatchVersion = rep.ddxDriverPatchVersion; + + if (rep.length) { + if (!(*clientDriverName = + (char *)Xcalloc(rep.clientDriverNameLength + 1, 1))) { + _XEatData(dpy, ((rep.clientDriverNameLength + 3) & ~3)); + UnlockDisplay(dpy); + SyncHandle(); + TRACE("GetClientDriverName... return False"); + return False; + } + _XReadPad(dpy, *clientDriverName, rep.clientDriverNameLength); + } else { + *clientDriverName = NULL; + } + UnlockDisplay(dpy); + SyncHandle(); + TRACE("GetClientDriverName... return True"); + return True; +} + +Bool +uniDRICreateContextWithConfig(dpy, screen, configID, context, hHWContext) + Display *dpy; + int screen; + int configID; + XID *context; + drm_context_t *hHWContext; +{ + XExtDisplayInfo *info = find_display(dpy); + xXF86DRICreateContextReply rep; + xXF86DRICreateContextReq *req; + + TRACE("CreateContext..."); + uniDRICheckExtension(dpy, info, False); + + LockDisplay(dpy); + GetReq(XF86DRICreateContext, req); + req->reqType = info->codes->major_opcode; + req->driReqType = X_XF86DRICreateContext; + req->visual = configID; + req->screen = screen; + *context = XAllocID(dpy); + req->context = *context; + if (!_XReply(dpy, (xReply *) & rep, 0, xFalse)) { + UnlockDisplay(dpy); + SyncHandle(); + TRACE("CreateContext... return False"); + return False; + } + *hHWContext = rep.hHWContext; + UnlockDisplay(dpy); + SyncHandle(); + TRACE("CreateContext... return True"); + return True; +} + +Bool +uniDRICreateContext(dpy, screen, visual, context, hHWContext) + Display *dpy; + int screen; + Visual *visual; + XID *context; + drm_context_t *hHWContext; +{ + return uniDRICreateContextWithConfig(dpy, screen, visual->visualid, + context, hHWContext); +} + +Bool +uniDRIDestroyContext(Display * ndpy, int screen, XID context) +{ + Display *const dpy = (Display *) ndpy; + XExtDisplayInfo *info = find_display(dpy); + xXF86DRIDestroyContextReq *req; + + TRACE("DestroyContext..."); + uniDRICheckExtension(dpy, info, False); + + LockDisplay(dpy); + GetReq(XF86DRIDestroyContext, req); + req->reqType = info->codes->major_opcode; + req->driReqType = X_XF86DRIDestroyContext; + req->screen = screen; + req->context = context; + UnlockDisplay(dpy); + SyncHandle(); + TRACE("DestroyContext... return True"); + return True; +} + +Bool +uniDRICreateDrawable(Display * ndpy, int screen, + Drawable drawable, drm_drawable_t * hHWDrawable) +{ + Display *const dpy = (Display *) ndpy; + XExtDisplayInfo *info = find_display(dpy); + xXF86DRICreateDrawableReply rep; + xXF86DRICreateDrawableReq *req; + + TRACE("CreateDrawable..."); + uniDRICheckExtension(dpy, info, False); + + LockDisplay(dpy); + GetReq(XF86DRICreateDrawable, req); + req->reqType = info->codes->major_opcode; + req->driReqType = X_XF86DRICreateDrawable; + req->screen = screen; + req->drawable = drawable; + if (!_XReply(dpy, (xReply *) & rep, 0, xFalse)) { + UnlockDisplay(dpy); + SyncHandle(); + TRACE("CreateDrawable... return False"); + return False; + } + *hHWDrawable = rep.hHWDrawable; + UnlockDisplay(dpy); + SyncHandle(); + TRACE("CreateDrawable... return True"); + return True; +} + +Bool +uniDRIDestroyDrawable(Display * ndpy, int screen, Drawable drawable) +{ + Display *const dpy = (Display *) ndpy; + XExtDisplayInfo *info = find_display(dpy); + xXF86DRIDestroyDrawableReq *req; + + TRACE("DestroyDrawable..."); + uniDRICheckExtension(dpy, info, False); + + LockDisplay(dpy); + GetReq(XF86DRIDestroyDrawable, req); + req->reqType = info->codes->major_opcode; + req->driReqType = X_XF86DRIDestroyDrawable; + req->screen = screen; + req->drawable = drawable; + UnlockDisplay(dpy); + SyncHandle(); + TRACE("DestroyDrawable... return True"); + return True; +} + +Bool +uniDRIGetDrawableInfo(Display * dpy, int screen, Drawable drawable, + unsigned int *index, unsigned int *stamp, + int *X, int *Y, int *W, int *H, + int *numClipRects, drm_clip_rect_t ** pClipRects, + int *backX, int *backY, + int *numBackClipRects, + drm_clip_rect_t ** pBackClipRects) +{ + XExtDisplayInfo *info = find_display(dpy); + xXF86DRIGetDrawableInfoReply rep; + xXF86DRIGetDrawableInfoReq *req; + int total_rects; + + TRACE("GetDrawableInfo..."); + uniDRICheckExtension(dpy, info, False); + + LockDisplay(dpy); + GetReq(XF86DRIGetDrawableInfo, req); + req->reqType = info->codes->major_opcode; + req->driReqType = X_XF86DRIGetDrawableInfo; + req->screen = screen; + req->drawable = drawable; + + if (!_XReply(dpy, (xReply *) & rep, 1, xFalse)) { + UnlockDisplay(dpy); + SyncHandle(); + TRACE("GetDrawableInfo... return False"); + return False; + } + *index = rep.drawableTableIndex; + *stamp = rep.drawableTableStamp; + *X = (int)rep.drawableX; + *Y = (int)rep.drawableY; + *W = (int)rep.drawableWidth; + *H = (int)rep.drawableHeight; + *numClipRects = rep.numClipRects; + total_rects = *numClipRects; + + *backX = rep.backX; + *backY = rep.backY; + *numBackClipRects = rep.numBackClipRects; + total_rects += *numBackClipRects; + +#if 0 + /* Because of the fix in Xserver/GL/dri/xf86dri.c, this check breaks + * backwards compatibility (Because of the >> 2 shift) but the fix + * enables multi-threaded apps to work. + */ + if (rep.length != ((((SIZEOF(xXF86DRIGetDrawableInfoReply) - + SIZEOF(xGenericReply) + + total_rects * sizeof(drm_clip_rect_t)) + + 3) & ~3) >> 2)) { + _XEatData(dpy, rep.length); + UnlockDisplay(dpy); + SyncHandle(); + TRACE("GetDrawableInfo... return False"); + return False; + } +#endif + + if (*numClipRects) { + int len = sizeof(drm_clip_rect_t) * (*numClipRects); + + *pClipRects = (drm_clip_rect_t *) Xcalloc(len, 1); + if (*pClipRects) + _XRead(dpy, (char *)*pClipRects, len); + } else { + *pClipRects = NULL; + } + + if (*numBackClipRects) { + int len = sizeof(drm_clip_rect_t) * (*numBackClipRects); + + *pBackClipRects = (drm_clip_rect_t *) Xcalloc(len, 1); + if (*pBackClipRects) + _XRead(dpy, (char *)*pBackClipRects, len); + } else { + *pBackClipRects = NULL; + } + + UnlockDisplay(dpy); + SyncHandle(); + TRACE("GetDrawableInfo... return True"); + return True; +} + +Bool +uniDRIGetDeviceInfo(dpy, screen, hFrameBuffer, + fbOrigin, fbSize, fbStride, devPrivateSize, pDevPrivate) + Display *dpy; + int screen; + drm_handle_t *hFrameBuffer; + int *fbOrigin; + int *fbSize; + int *fbStride; + int *devPrivateSize; + void **pDevPrivate; +{ + XExtDisplayInfo *info = find_display(dpy); + xXF86DRIGetDeviceInfoReply rep; + xXF86DRIGetDeviceInfoReq *req; + + TRACE("GetDeviceInfo..."); + uniDRICheckExtension(dpy, info, False); + + LockDisplay(dpy); + GetReq(XF86DRIGetDeviceInfo, req); + req->reqType = info->codes->major_opcode; + req->driReqType = X_XF86DRIGetDeviceInfo; + req->screen = screen; + if (!_XReply(dpy, (xReply *) & rep, 0, xFalse)) { + UnlockDisplay(dpy); + SyncHandle(); + TRACE("GetDeviceInfo... return False"); + return False; + } + + *hFrameBuffer = rep.hFrameBufferLow; +#ifdef LONG64 + if (sizeof(drm_handle_t) == 8) { + *hFrameBuffer |= ((unsigned long)rep.hFrameBufferHigh) << 32; + } +#endif + + *fbOrigin = rep.framebufferOrigin; + *fbSize = rep.framebufferSize; + *fbStride = rep.framebufferStride; + *devPrivateSize = rep.devPrivateSize; + + if (rep.length) { + if (!(*pDevPrivate = (void *)Xcalloc(rep.devPrivateSize, 1))) { + _XEatData(dpy, ((rep.devPrivateSize + 3) & ~3)); + UnlockDisplay(dpy); + SyncHandle(); + TRACE("GetDeviceInfo... return False"); + return False; + } + _XRead(dpy, (char *)*pDevPrivate, rep.devPrivateSize); + } else { + *pDevPrivate = NULL; + } + + UnlockDisplay(dpy); + SyncHandle(); + TRACE("GetDeviceInfo... return True"); + return True; +} diff --git a/src/gallium/winsys/drm/r600/python/xf86dri.h b/src/gallium/winsys/drm/r600/python/xf86dri.h new file mode 100644 index 00000000000..bf6de37d9dd --- /dev/null +++ b/src/gallium/winsys/drm/r600/python/xf86dri.h @@ -0,0 +1,123 @@ +/************************************************************************** + +Copyright 1998-1999 Precision Insight, Inc., Cedar Park, Texas. +Copyright 2000 VA Linux Systems, Inc. +All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a +copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sub license, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice (including the +next paragraph) shall be included in all copies or substantial portions +of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. +IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR +ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ + +/** + * \file xf86dri.h + * Protocol numbers and function prototypes for DRI X protocol. + * + * \author Kevin E. Martin <[email protected]> + * \author Jens Owen <[email protected]> + * \author Rickard E. (Rik) Faith <[email protected]> + */ + +#ifndef _XF86DRI_H_ +#define _XF86DRI_H_ + +#include <stdint.h> +#include <X11/Xfuncproto.h> +#include <drm/drm.h> + +#define X_XF86DRIQueryVersion 0 +#define X_XF86DRIQueryDirectRenderingCapable 1 +#define X_XF86DRIOpenConnection 2 +#define X_XF86DRICloseConnection 3 +#define X_XF86DRIGetClientDriverName 4 +#define X_XF86DRICreateContext 5 +#define X_XF86DRIDestroyContext 6 +#define X_XF86DRICreateDrawable 7 +#define X_XF86DRIDestroyDrawable 8 +#define X_XF86DRIGetDrawableInfo 9 +#define X_XF86DRIGetDeviceInfo 10 +#define X_XF86DRIAuthConnection 11 +#define X_XF86DRIOpenFullScreen 12 /* Deprecated */ +#define X_XF86DRICloseFullScreen 13 /* Deprecated */ + +#define XF86DRINumberEvents 0 + +#define XF86DRIClientNotLocal 0 +#define XF86DRIOperationNotSupported 1 +#define XF86DRINumberErrors (XF86DRIOperationNotSupported + 1) + +#ifndef _XF86DRI_SERVER_ + +_XFUNCPROTOBEGIN + Bool uniDRIQueryExtension(Display * dpy, int *event_base, + int *error_base); + +Bool uniDRIQueryVersion(Display * dpy, int *majorVersion, int *minorVersion, + int *patchVersion); + +Bool uniDRIQueryDirectRenderingCapable(Display * dpy, int screen, + Bool * isCapable); + +Bool uniDRIOpenConnection(Display * dpy, int screen, drm_handle_t * hSAREA, + char **busIDString); + +Bool uniDRIAuthConnection(Display * dpy, int screen, drm_magic_t magic); + +Bool uniDRICloseConnection(Display * dpy, int screen); + +Bool uniDRIGetClientDriverName(Display * dpy, int screen, + int *ddxDriverMajorVersion, + int *ddxDriverMinorVersion, + int *ddxDriverPatchVersion, + char **clientDriverName); + +Bool uniDRICreateContext(Display * dpy, int screen, Visual * visual, + XID * ptr_to_returned_context_id, + drm_context_t * hHWContext); + +Bool uniDRICreateContextWithConfig(Display * dpy, int screen, int configID, + XID * ptr_to_returned_context_id, + drm_context_t * hHWContext); + +extern Bool uniDRIDestroyContext(Display * dpy, int screen, XID context_id); + +extern Bool uniDRICreateDrawable(Display * dpy, int screen, + Drawable drawable, + drm_drawable_t * hHWDrawable); + +extern Bool uniDRIDestroyDrawable(Display * dpy, int screen, + Drawable drawable); + +Bool uniDRIGetDrawableInfo(Display * dpy, int screen, Drawable drawable, + unsigned int *index, unsigned int *stamp, + int *X, int *Y, int *W, int *H, + int *numClipRects, drm_clip_rect_t ** pClipRects, + int *backX, int *backY, + int *numBackClipRects, + drm_clip_rect_t ** pBackClipRects); + +Bool uniDRIGetDeviceInfo(Display * dpy, int screen, + drm_handle_t * hFrameBuffer, int *fbOrigin, + int *fbSize, int *fbStride, int *devPrivateSize, + void **pDevPrivate); + +_XFUNCPROTOEND +#endif /* _XF86DRI_SERVER_ */ +#endif /* _XF86DRI_H_ */ diff --git a/src/gallium/winsys/drm/r600/python/xf86dristr.h b/src/gallium/winsys/drm/r600/python/xf86dristr.h new file mode 100644 index 00000000000..d8989963609 --- /dev/null +++ b/src/gallium/winsys/drm/r600/python/xf86dristr.h @@ -0,0 +1,389 @@ +/************************************************************************** + +Copyright 1998-1999 Precision Insight, Inc., Cedar Park, Texas. +Copyright 2000 VA Linux Systems, Inc. +All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a +copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sub license, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice (including the +next paragraph) shall be included in all copies or substantial portions +of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. +IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR +ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ + +/* + * Authors: + * Kevin E. Martin <[email protected]> + * Jens Owen <[email protected]> + * Rickard E. (Rik) Fiath <[email protected]> + * + */ + +#ifndef _XF86DRISTR_H_ +#define _XF86DRISTR_H_ + +#include "xf86dri.h" + +#define XF86DRINAME "XFree86-DRI" + +/* The DRI version number. This was originally set to be the same of the + * XFree86 version number. However, this version is really indepedent of + * the XFree86 version. + * + * Version History: + * 4.0.0: Original + * 4.0.1: Patch to bump clipstamp when windows are destroyed, 28 May 02 + * 4.1.0: Add transition from single to multi in DRMInfo rec, 24 Jun 02 + */ +#define XF86DRI_MAJOR_VERSION 4 +#define XF86DRI_MINOR_VERSION 1 +#define XF86DRI_PATCH_VERSION 0 + +typedef struct _XF86DRIQueryVersion +{ + CARD8 reqType; /* always DRIReqCode */ + CARD8 driReqType; /* always X_DRIQueryVersion */ + CARD16 length B16; +} xXF86DRIQueryVersionReq; + +#define sz_xXF86DRIQueryVersionReq 4 + +typedef struct +{ + BYTE type; /* X_Reply */ + BOOL pad1; + CARD16 sequenceNumber B16; + CARD32 length B32; + CARD16 majorVersion B16; /* major version of DRI protocol */ + CARD16 minorVersion B16; /* minor version of DRI protocol */ + CARD32 patchVersion B32; /* patch version of DRI protocol */ + CARD32 pad3 B32; + CARD32 pad4 B32; + CARD32 pad5 B32; + CARD32 pad6 B32; +} xXF86DRIQueryVersionReply; + +#define sz_xXF86DRIQueryVersionReply 32 + +typedef struct _XF86DRIQueryDirectRenderingCapable +{ + CARD8 reqType; /* always DRIReqCode */ + CARD8 driReqType; /* X_DRIQueryDirectRenderingCapable */ + CARD16 length B16; + CARD32 screen B32; +} xXF86DRIQueryDirectRenderingCapableReq; + +#define sz_xXF86DRIQueryDirectRenderingCapableReq 8 + +typedef struct +{ + BYTE type; /* X_Reply */ + BOOL pad1; + CARD16 sequenceNumber B16; + CARD32 length B32; + BOOL isCapable; + BOOL pad2; + BOOL pad3; + BOOL pad4; + CARD32 pad5 B32; + CARD32 pad6 B32; + CARD32 pad7 B32; + CARD32 pad8 B32; + CARD32 pad9 B32; +} xXF86DRIQueryDirectRenderingCapableReply; + +#define sz_xXF86DRIQueryDirectRenderingCapableReply 32 + +typedef struct _XF86DRIOpenConnection +{ + CARD8 reqType; /* always DRIReqCode */ + CARD8 driReqType; /* always X_DRIOpenConnection */ + CARD16 length B16; + CARD32 screen B32; +} xXF86DRIOpenConnectionReq; + +#define sz_xXF86DRIOpenConnectionReq 8 + +typedef struct +{ + BYTE type; /* X_Reply */ + BOOL pad1; + CARD16 sequenceNumber B16; + CARD32 length B32; + CARD32 hSAREALow B32; + CARD32 hSAREAHigh B32; + CARD32 busIdStringLength B32; + CARD32 pad6 B32; + CARD32 pad7 B32; + CARD32 pad8 B32; +} xXF86DRIOpenConnectionReply; + +#define sz_xXF86DRIOpenConnectionReply 32 + +typedef struct _XF86DRIAuthConnection +{ + CARD8 reqType; /* always DRIReqCode */ + CARD8 driReqType; /* always X_DRICloseConnection */ + CARD16 length B16; + CARD32 screen B32; + CARD32 magic B32; +} xXF86DRIAuthConnectionReq; + +#define sz_xXF86DRIAuthConnectionReq 12 + +typedef struct +{ + BYTE type; + BOOL pad1; + CARD16 sequenceNumber B16; + CARD32 length B32; + CARD32 authenticated B32; + CARD32 pad2 B32; + CARD32 pad3 B32; + CARD32 pad4 B32; + CARD32 pad5 B32; + CARD32 pad6 B32; +} xXF86DRIAuthConnectionReply; + +#define zx_xXF86DRIAuthConnectionReply 32 + +typedef struct _XF86DRICloseConnection +{ + CARD8 reqType; /* always DRIReqCode */ + CARD8 driReqType; /* always X_DRICloseConnection */ + CARD16 length B16; + CARD32 screen B32; +} xXF86DRICloseConnectionReq; + +#define sz_xXF86DRICloseConnectionReq 8 + +typedef struct _XF86DRIGetClientDriverName +{ + CARD8 reqType; /* always DRIReqCode */ + CARD8 driReqType; /* always X_DRIGetClientDriverName */ + CARD16 length B16; + CARD32 screen B32; +} xXF86DRIGetClientDriverNameReq; + +#define sz_xXF86DRIGetClientDriverNameReq 8 + +typedef struct +{ + BYTE type; /* X_Reply */ + BOOL pad1; + CARD16 sequenceNumber B16; + CARD32 length B32; + CARD32 ddxDriverMajorVersion B32; + CARD32 ddxDriverMinorVersion B32; + CARD32 ddxDriverPatchVersion B32; + CARD32 clientDriverNameLength B32; + CARD32 pad5 B32; + CARD32 pad6 B32; +} xXF86DRIGetClientDriverNameReply; + +#define sz_xXF86DRIGetClientDriverNameReply 32 + +typedef struct _XF86DRICreateContext +{ + CARD8 reqType; /* always DRIReqCode */ + CARD8 driReqType; /* always X_DRICreateContext */ + CARD16 length B16; + CARD32 screen B32; + CARD32 visual B32; + CARD32 context B32; +} xXF86DRICreateContextReq; + +#define sz_xXF86DRICreateContextReq 16 + +typedef struct +{ + BYTE type; /* X_Reply */ + BOOL pad1; + CARD16 sequenceNumber B16; + CARD32 length B32; + CARD32 hHWContext B32; + CARD32 pad2 B32; + CARD32 pad3 B32; + CARD32 pad4 B32; + CARD32 pad5 B32; + CARD32 pad6 B32; +} xXF86DRICreateContextReply; + +#define sz_xXF86DRICreateContextReply 32 + +typedef struct _XF86DRIDestroyContext +{ + CARD8 reqType; /* always DRIReqCode */ + CARD8 driReqType; /* always X_DRIDestroyContext */ + CARD16 length B16; + CARD32 screen B32; + CARD32 context B32; +} xXF86DRIDestroyContextReq; + +#define sz_xXF86DRIDestroyContextReq 12 + +typedef struct _XF86DRICreateDrawable +{ + CARD8 reqType; /* always DRIReqCode */ + CARD8 driReqType; /* always X_DRICreateDrawable */ + CARD16 length B16; + CARD32 screen B32; + CARD32 drawable B32; +} xXF86DRICreateDrawableReq; + +#define sz_xXF86DRICreateDrawableReq 12 + +typedef struct +{ + BYTE type; /* X_Reply */ + BOOL pad1; + CARD16 sequenceNumber B16; + CARD32 length B32; + CARD32 hHWDrawable B32; + CARD32 pad2 B32; + CARD32 pad3 B32; + CARD32 pad4 B32; + CARD32 pad5 B32; + CARD32 pad6 B32; +} xXF86DRICreateDrawableReply; + +#define sz_xXF86DRICreateDrawableReply 32 + +typedef struct _XF86DRIDestroyDrawable +{ + CARD8 reqType; /* always DRIReqCode */ + CARD8 driReqType; /* always X_DRIDestroyDrawable */ + CARD16 length B16; + CARD32 screen B32; + CARD32 drawable B32; +} xXF86DRIDestroyDrawableReq; + +#define sz_xXF86DRIDestroyDrawableReq 12 + +typedef struct _XF86DRIGetDrawableInfo +{ + CARD8 reqType; /* always DRIReqCode */ + CARD8 driReqType; /* always X_DRIGetDrawableInfo */ + CARD16 length B16; + CARD32 screen B32; + CARD32 drawable B32; +} xXF86DRIGetDrawableInfoReq; + +#define sz_xXF86DRIGetDrawableInfoReq 12 + +typedef struct +{ + BYTE type; /* X_Reply */ + BOOL pad1; + CARD16 sequenceNumber B16; + CARD32 length B32; + CARD32 drawableTableIndex B32; + CARD32 drawableTableStamp B32; + INT16 drawableX B16; + INT16 drawableY B16; + INT16 drawableWidth B16; + INT16 drawableHeight B16; + CARD32 numClipRects B32; + INT16 backX B16; + INT16 backY B16; + CARD32 numBackClipRects B32; +} xXF86DRIGetDrawableInfoReply; + +#define sz_xXF86DRIGetDrawableInfoReply 36 + +typedef struct _XF86DRIGetDeviceInfo +{ + CARD8 reqType; /* always DRIReqCode */ + CARD8 driReqType; /* always X_DRIGetDeviceInfo */ + CARD16 length B16; + CARD32 screen B32; +} xXF86DRIGetDeviceInfoReq; + +#define sz_xXF86DRIGetDeviceInfoReq 8 + +typedef struct +{ + BYTE type; /* X_Reply */ + BOOL pad1; + CARD16 sequenceNumber B16; + CARD32 length B32; + CARD32 hFrameBufferLow B32; + CARD32 hFrameBufferHigh B32; + CARD32 framebufferOrigin B32; + CARD32 framebufferSize B32; + CARD32 framebufferStride B32; + CARD32 devPrivateSize B32; +} xXF86DRIGetDeviceInfoReply; + +#define sz_xXF86DRIGetDeviceInfoReply 32 + +typedef struct _XF86DRIOpenFullScreen +{ + CARD8 reqType; /* always DRIReqCode */ + CARD8 driReqType; /* always X_DRIOpenFullScreen */ + CARD16 length B16; + CARD32 screen B32; + CARD32 drawable B32; +} xXF86DRIOpenFullScreenReq; + +#define sz_xXF86DRIOpenFullScreenReq 12 + +typedef struct +{ + BYTE type; + BOOL pad1; + CARD16 sequenceNumber B16; + CARD32 length B32; + CARD32 isFullScreen B32; + CARD32 pad2 B32; + CARD32 pad3 B32; + CARD32 pad4 B32; + CARD32 pad5 B32; + CARD32 pad6 B32; +} xXF86DRIOpenFullScreenReply; + +#define sz_xXF86DRIOpenFullScreenReply 32 + +typedef struct _XF86DRICloseFullScreen +{ + CARD8 reqType; /* always DRIReqCode */ + CARD8 driReqType; /* always X_DRICloseFullScreen */ + CARD16 length B16; + CARD32 screen B32; + CARD32 drawable B32; +} xXF86DRICloseFullScreenReq; + +#define sz_xXF86DRICloseFullScreenReq 12 + +typedef struct +{ + BYTE type; + BOOL pad1; + CARD16 sequenceNumber B16; + CARD32 length B32; + CARD32 pad2 B32; + CARD32 pad3 B32; + CARD32 pad4 B32; + CARD32 pad5 B32; + CARD32 pad6 B32; + CARD32 pad7 B32; +} xXF86DRICloseFullScreenReply; + +#define sz_xXF86DRICloseFullScreenReply 32 + +#endif /* _XF86DRISTR_H_ */ |