diff options
| -rw-r--r-- | src/amd/common/ac_gpu_info.c | 2 | ||||
| -rw-r--r-- | src/amd/common/ac_gpu_info.h | 1 | ||||
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_state.c | 2 |
3 files changed, 5 insertions, 0 deletions
diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c index 79d83a7effc..596a9ebe508 100644 --- a/src/amd/common/ac_gpu_info.c +++ b/src/amd/common/ac_gpu_info.c @@ -405,6 +405,7 @@ bool ac_query_gpu_info(int fd, void *dev_p, info->has_read_registers_query = true; info->has_scheduled_fence_dependency = info->drm_minor >= 28; + info->pa_sc_tile_steering_override = device_info.pa_sc_tile_steering_override; info->num_render_backends = amdinfo->rb_pipes; /* The value returned by the kernel driver was wrong. */ if (info->family == CHIP_KAVERI) @@ -599,6 +600,7 @@ void ac_print_gpu_info(struct radeon_info *info) printf(" max_sh_per_se = %i\n", info->max_sh_per_se); printf("Render backend info:\n"); + printf(" pa_sc_tile_steering_override = 0x%x\n", info->pa_sc_tile_steering_override); printf(" num_render_backends = %i\n", info->num_render_backends); printf(" num_tile_pipes = %i\n", info->num_tile_pipes); printf(" pipe_interleave_bytes = %i\n", info->pipe_interleave_bytes); diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h index cea6181dc7e..c42548f8352 100644 --- a/src/amd/common/ac_gpu_info.h +++ b/src/amd/common/ac_gpu_info.h @@ -138,6 +138,7 @@ struct radeon_info { bool r600_gb_backend_map_valid; uint32_t r600_num_banks; uint32_t gb_addr_config; + uint32_t pa_sc_tile_steering_override; /* CLEAR_STATE also sets this */ uint32_t num_render_backends; uint32_t num_tile_pipes; /* pipe count from PIPE_CONFIG */ uint32_t pipe_interleave_bytes; diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index 3b3ee913c79..e9388e6252c 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -5564,6 +5564,8 @@ static void si_init_config(struct si_context *sctx) */ si_pm4_set_reg(pm4, R_028C50_PA_SC_NGG_MODE_CNTL, S_028C50_MAX_DEALLOCS_IN_WAVE(512)); + si_pm4_set_reg(pm4, R_02835C_PA_SC_TILE_STEERING_OVERRIDE, + sscreen->info.pa_sc_tile_steering_override); } if (sctx->chip_class >= GFX8) { |