diff options
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_pipe.h | 1 | ||||
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_shader.h | 3 | ||||
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_state.c | 21 | ||||
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_state_shaders.c | 16 |
4 files changed, 25 insertions, 16 deletions
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h index 791145e9c50..108929c10c6 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.h +++ b/src/gallium/drivers/radeonsi/si_pipe.h @@ -67,6 +67,7 @@ #define SI_CONTEXT_VGT_STREAMOUT_SYNC (R600_CONTEXT_PRIVATE_FLAG << 13) #define SI_MAX_BORDER_COLORS 4096 +#define SIX_BITS 0x3F struct si_compute; struct hash_table; diff --git a/src/gallium/drivers/radeonsi/si_shader.h b/src/gallium/drivers/radeonsi/si_shader.h index f739769af3f..7c04b7e2535 100644 --- a/src/gallium/drivers/radeonsi/si_shader.h +++ b/src/gallium/drivers/radeonsi/si_shader.h @@ -326,6 +326,9 @@ struct si_shader_selector { /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */ unsigned type; bool vs_needs_prolog; + unsigned pa_cl_vs_out_cntl; + ubyte clipdist_mask; + ubyte culldist_mask; /* GS parameters. */ unsigned esgs_itemsize; diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index 458bc109eeb..3f471a3672e 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -663,22 +663,19 @@ static void si_emit_clip_state(struct si_context *sctx, struct r600_atom *atom) radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4); } -#define SIX_BITS 0x3F - static void si_emit_clip_regs(struct si_context *sctx, struct r600_atom *atom) { struct radeon_winsys_cs *cs = sctx->b.gfx.cs; struct si_shader *vs = si_get_vs_state(sctx); - struct tgsi_shader_info *info = si_get_vs_info(sctx); + struct si_shader_selector *vs_sel = vs->selector; + struct tgsi_shader_info *info = &vs_sel->info; struct si_state_rasterizer *rs = sctx->queued.named.rasterizer; unsigned window_space = info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION]; - unsigned clipdist_mask = - info->writes_clipvertex ? SIX_BITS : info->clipdist_writemask; + unsigned clipdist_mask = vs_sel->clipdist_mask; unsigned ucp_mask = clipdist_mask ? 0 : rs->clip_plane_enable & SIX_BITS; - unsigned culldist_mask = info->culldist_writemask << info->num_written_clipdistance; + unsigned culldist_mask = vs_sel->culldist_mask; unsigned total_mask; - bool misc_vec_ena; if (vs->key.opt.hw_vs.clip_disable) { assert(!info->culldist_writemask); @@ -696,18 +693,10 @@ static void si_emit_clip_regs(struct si_context *sctx, struct r600_atom *atom) clipdist_mask &= rs->clip_plane_enable; culldist_mask |= clipdist_mask; - misc_vec_ena = info->writes_psize || info->writes_edgeflag || - info->writes_layer || info->writes_viewport_index; - radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL, - S_02881C_USE_VTX_POINT_SIZE(info->writes_psize) | - S_02881C_USE_VTX_EDGE_FLAG(info->writes_edgeflag) | - S_02881C_USE_VTX_RENDER_TARGET_INDX(info->writes_layer) | - S_02881C_USE_VTX_VIEWPORT_INDX(info->writes_viewport_index) | + vs_sel->pa_cl_vs_out_cntl | S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0F) != 0) | S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xF0) != 0) | - S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) | - S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) | clipdist_mask | (culldist_mask << 8)); radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL, rs->pa_cl_clip_cntl | diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c index 078b5e6250d..2e33138695e 100644 --- a/src/gallium/drivers/radeonsi/si_state_shaders.c +++ b/src/gallium/drivers/radeonsi/si_state_shaders.c @@ -2087,6 +2087,22 @@ static void *si_create_shader_selector(struct pipe_context *ctx, break; } + /* PA_CL_VS_OUT_CNTL */ + bool misc_vec_ena = + sel->info.writes_psize || sel->info.writes_edgeflag || + sel->info.writes_layer || sel->info.writes_viewport_index; + sel->pa_cl_vs_out_cntl = + S_02881C_USE_VTX_POINT_SIZE(sel->info.writes_psize) | + S_02881C_USE_VTX_EDGE_FLAG(sel->info.writes_edgeflag) | + S_02881C_USE_VTX_RENDER_TARGET_INDX(sel->info.writes_layer) | + S_02881C_USE_VTX_VIEWPORT_INDX(sel->info.writes_viewport_index) | + S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) | + S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena); + sel->clipdist_mask = sel->info.writes_clipvertex ? + SIX_BITS : sel->info.clipdist_writemask; + sel->culldist_mask = sel->info.culldist_writemask << + sel->info.num_written_clipdistance; + /* DB_SHADER_CONTROL */ sel->db_shader_control = S_02880C_Z_EXPORT_ENABLE(sel->info.writes_z) | |