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-rw-r--r--src/amd/vulkan/radv_nir_to_llvm.c10
-rw-r--r--src/amd/vulkan/radv_shader_info.c20
2 files changed, 20 insertions, 10 deletions
diff --git a/src/amd/vulkan/radv_nir_to_llvm.c b/src/amd/vulkan/radv_nir_to_llvm.c
index e2d3447879f..334ee1883b4 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -2788,10 +2788,6 @@ handle_vs_outputs_post(struct radv_shader_context *ctx,
sizeof(outinfo->vs_output_param_offset));
outinfo->pos_exports = 0;
- if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
- outinfo->writes_layer = true;
- }
-
if (ctx->shader_info->so.num_outputs &&
!ctx->is_gs_copy_shader) {
/* The GS copy shader emission already emits streamout. */
@@ -3506,10 +3502,6 @@ static void gfx10_ngg_gs_emit_epilogue_2(struct radv_shader_context *ctx)
tmp = LLVMBuildZExt(builder, tmp, ctx->ac.i32, "");
const LLVMValueRef vertexptr = ngg_gs_vertex_ptr(ctx, tmp);
- if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
- outinfo->writes_layer = true;
- }
-
unsigned out_idx = 0;
gep_idx[1] = ctx->ac.i32_0;
for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
@@ -3544,8 +3536,6 @@ static void gfx10_ngg_gs_emit_epilogue_2(struct radv_shader_context *ctx)
/* Export ViewIndex. */
if (export_view_index) {
- outinfo->writes_layer = true;
-
outputs[noutput].slot_name = VARYING_SLOT_LAYER;
outputs[noutput].slot_index = 0;
outputs[noutput].usage_mask = 0x1;
diff --git a/src/amd/vulkan/radv_shader_info.c b/src/amd/vulkan/radv_shader_info.c
index 614a20d5921..ce9823f8485 100644
--- a/src/amd/vulkan/radv_shader_info.c
+++ b/src/amd/vulkan/radv_shader_info.c
@@ -574,6 +574,9 @@ gather_info_output_decl(const nir_shader *nir, const nir_variable *var,
case VARYING_SLOT_VIEWPORT:
vs_info->writes_viewport_index = true;
break;
+ case VARYING_SLOT_LAYER:
+ vs_info->writes_layer = true;
+ break;
default:
break;
}
@@ -667,6 +670,23 @@ radv_nir_shader_info_pass(const struct nir_shader *nir,
}
}
+ /* Make sure to export the LayerID if the subpass has multiviews. */
+ if (options->key.has_multiview_view_index) {
+ switch (nir->info.stage) {
+ case MESA_SHADER_VERTEX:
+ info->vs.outinfo.writes_layer = true;
+ break;
+ case MESA_SHADER_TESS_EVAL:
+ info->tes.outinfo.writes_layer = true;
+ break;
+ case MESA_SHADER_GEOMETRY:
+ info->vs.outinfo.writes_layer = true;
+ break;
+ default:
+ break;
+ }
+ }
+
if (nir->info.stage == MESA_SHADER_FRAGMENT)
info->ps.num_interp = nir->num_inputs;