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-rw-r--r--src/amd/common/ac_gpu_info.c10
-rw-r--r--src/amd/common/ac_gpu_info.h1
-rw-r--r--src/amd/vulkan/radv_cmd_buffer.c2
-rw-r--r--src/amd/vulkan/radv_device.c9
-rw-r--r--src/amd/vulkan/radv_pipeline.c2
-rw-r--r--src/amd/vulkan/radv_private.h2
-rw-r--r--src/gallium/drivers/radeonsi/si_pipe.c14
-rw-r--r--src/gallium/drivers/radeonsi/si_pipe.h1
-rw-r--r--src/gallium/drivers/radeonsi/si_state.c6
-rw-r--r--src/gallium/drivers/radeonsi/si_state_shaders.c2
10 files changed, 17 insertions, 32 deletions
diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index 3f3a236ba80..49ad93407ec 100644
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -457,6 +457,16 @@ bool ac_query_gpu_info(int fd, void *dev_p,
info->has_rbplus = info->family == CHIP_STONEY ||
info->chip_class >= GFX9;
+ /* Some chips have RB+ registers, but don't support RB+. Those must
+ * always disable it.
+ */
+ info->rbplus_allowed = info->has_rbplus &&
+ (info->family == CHIP_STONEY ||
+ info->family == CHIP_VEGA12 ||
+ info->family == CHIP_RAVEN ||
+ info->family == CHIP_RAVEN2 ||
+ info->family == CHIP_RENOIR);
+
info->has_out_of_order_rast = info->chip_class >= GFX8 &&
info->max_se >= 2;
diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
index 0f802216bdc..f676600e5b9 100644
--- a/src/amd/common/ac_gpu_info.h
+++ b/src/amd/common/ac_gpu_info.h
@@ -62,6 +62,7 @@ struct radeon_info {
bool has_distributed_tess;
bool has_dcc_constant_encode;
bool has_rbplus; /* if RB+ registers exist */
+ bool rbplus_allowed; /* if RB+ is allowed */
bool has_load_ctx_reg_pkt;
bool has_out_of_order_rast;
bool cpdma_prefetch_writes_memory;
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 7031428a996..aed2e9f8909 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -988,7 +988,7 @@ radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
static void
radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
{
- if (!cmd_buffer->device->physical_device->rbplus_allowed)
+ if (!cmd_buffer->device->physical_device->rad_info.rbplus_allowed)
return;
struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index ce487aa2eda..265a7bd7912 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -354,15 +354,6 @@ radv_physical_device_init(struct radv_physical_device *device,
radv_get_driver_uuid(&device->driver_uuid);
radv_get_device_uuid(&device->rad_info, &device->device_uuid);
- if (device->rad_info.family == CHIP_STONEY ||
- device->rad_info.chip_class >= GFX9) {
- device->rbplus_allowed = device->rad_info.family == CHIP_STONEY ||
- device->rad_info.family == CHIP_VEGA12 ||
- device->rad_info.family == CHIP_RAVEN ||
- device->rad_info.family == CHIP_RAVEN2 ||
- device->rad_info.family == CHIP_RENOIR;
- }
-
device->out_of_order_rast_allowed = device->rad_info.has_out_of_order_rast &&
!(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 0a5d94fd5f3..ecd4edf6500 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -4055,7 +4055,7 @@ radv_compute_db_shader_control(const struct radv_device *device,
z_order = V_02880C_LATE_Z;
bool disable_rbplus = device->physical_device->rad_info.has_rbplus &&
- !device->physical_device->rbplus_allowed;
+ !device->physical_device->rad_info.rbplus_allowed;
/* It shouldn't be needed to export gl_SampleMask when MSAA is disabled
* but this appears to break Project Cars (DXVK). See
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index b3d6d56e4ac..219495ef3d6 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -280,8 +280,6 @@ struct radv_physical_device {
int master_fd;
struct wsi_device wsi_device;
- bool rbplus_allowed; /* if RB+ is allowed */
-
bool out_of_order_rast_allowed;
/* Whether DCC should be enabled for MSAA textures. */
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
index fccf8233891..abb18236956 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -1173,20 +1173,6 @@ radeonsi_screen_create_impl(struct radeon_winsys *ws,
*/
sscreen->llvm_has_working_vgpr_indexing = sscreen->info.chip_class != GFX9;
- /* Some chips have RB+ registers, but don't support RB+. Those must
- * always disable it.
- */
- if (sscreen->info.family == CHIP_STONEY ||
- sscreen->info.chip_class >= GFX9) {
- sscreen->rbplus_allowed =
- !(sscreen->debug_flags & DBG(NO_RB_PLUS)) &&
- (sscreen->info.family == CHIP_STONEY ||
- sscreen->info.family == CHIP_VEGA12 ||
- sscreen->info.family == CHIP_RAVEN ||
- sscreen->info.family == CHIP_RAVEN2 ||
- sscreen->info.family == CHIP_RENOIR);
- }
-
sscreen->dcc_msaa_allowed =
!(sscreen->debug_flags & DBG(NO_DCC_MSAA));
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
index b8dfb8ac882..6e69f1717f6 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -511,7 +511,6 @@ struct si_screen {
/* Whether shaders are monolithic (1-part) or separate (3-part). */
bool use_monolithic_shaders;
bool record_llvm_ir;
- bool rbplus_allowed; /* if RB+ is allowed */
bool dcc_msaa_allowed;
struct slab_parent_pool pool_transfers;
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index dcd627467bc..d957e76c26d 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -131,7 +131,7 @@ static void si_emit_cb_render_state(struct si_context *sctx)
}
/* RB+ register settings. */
- if (sctx->screen->rbplus_allowed) {
+ if (sctx->screen->info.rbplus_allowed) {
unsigned spi_shader_col_format =
sctx->ps_shader.cso ?
sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format : 0;
@@ -640,7 +640,7 @@ static void *si_create_blend_state_mode(struct pipe_context *ctx,
color_control |= S_028808_MODE(V_028808_CB_DISABLE);
}
- if (sctx->screen->rbplus_allowed) {
+ if (sctx->screen->info.rbplus_allowed) {
/* Disable RB+ blend optimizations for dual source blending.
* Vulkan does this.
*/
@@ -1483,7 +1483,7 @@ static void si_emit_db_render_state(struct si_context *sctx)
db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
if (sctx->screen->info.has_rbplus &&
- !sctx->screen->rbplus_allowed)
+ !sctx->screen->info.rbplus_allowed)
db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
radeon_opt_set_context_reg(sctx, R_02880C_DB_SHADER_CONTROL,
diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c
index 003d116e8eb..1c80a227209 100644
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -3992,7 +3992,7 @@ bool si_update_shaders(struct si_context *sctx)
si_mark_atom_dirty(sctx, &sctx->atoms.s.spi_map);
}
- if (sctx->screen->rbplus_allowed &&
+ if (sctx->screen->info.rbplus_allowed &&
si_pm4_state_changed(sctx, ps) &&
(!old_ps ||
old_spi_shader_col_format !=
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-25 04:53:20 +0000