diff options
| -rw-r--r-- | src/mesa/drivers/dri/i965/intel_fbo.c | 33 |
1 files changed, 30 insertions, 3 deletions
diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c b/src/mesa/drivers/dri/i965/intel_fbo.c index 478e7b88842..e49f6df408d 100644 --- a/src/mesa/drivers/dri/i965/intel_fbo.c +++ b/src/mesa/drivers/dri/i965/intel_fbo.c @@ -670,14 +670,41 @@ intel_validate_framebuffer(struct gl_context *ctx, struct gl_framebuffer *fb) if (depth_mt && stencil_mt) { if (brw->gen >= 6) { + unsigned d_width, d_height, d_depth; + unsigned s_width, s_height, s_depth; + + if (depth_mt->surf.size > 0) { + d_width = depth_mt->surf.phys_level0_sa.width; + d_height = depth_mt->surf.phys_level0_sa.height; + d_depth = depth_mt->surf.dim == ISL_SURF_DIM_3D ? + depth_mt->surf.phys_level0_sa.depth : + depth_mt->surf.phys_level0_sa.array_len; + } else { + d_width = depth_mt->physical_width0; + d_height = depth_mt->physical_height0; + d_depth = depth_mt->physical_depth0; + } + + if (stencil_mt->surf.size > 0) { + s_width = stencil_mt->surf.phys_level0_sa.width; + s_height = stencil_mt->surf.phys_level0_sa.height; + s_depth = stencil_mt->surf.dim == ISL_SURF_DIM_3D ? + stencil_mt->surf.phys_level0_sa.depth : + stencil_mt->surf.phys_level0_sa.array_len; + } else { + s_width = stencil_mt->physical_width0; + s_height = stencil_mt->physical_height0; + s_depth = stencil_mt->physical_depth0; + } + /* For gen >= 6, we are using the lod/minimum-array-element fields * and supporting layered rendering. This means that we must restrict * the depth & stencil attachments to match in various more retrictive * ways. (width, height, depth, LOD and layer) */ - if (depth_mt->physical_width0 != stencil_mt->physical_width0 || - depth_mt->physical_height0 != stencil_mt->physical_height0 || - depth_mt->physical_depth0 != stencil_mt->physical_depth0 || + if (d_width != s_width || + d_height != s_height || + d_depth != s_depth || depthRb->mt_level != stencilRb->mt_level || depthRb->mt_layer != stencilRb->mt_layer) { fbo_incomplete(fb, |