diff options
| -rw-r--r-- | src/intel/blorp/blorp_genX_exec.h | 5 | ||||
| -rw-r--r-- | src/intel/isl/isl.c | 4 | ||||
| -rw-r--r-- | src/intel/isl/isl.h | 6 | ||||
| -rw-r--r-- | src/intel/vulkan/anv_image.c | 6 | ||||
| -rw-r--r-- | src/intel/vulkan/anv_private.h | 6 | ||||
| -rw-r--r-- | src/intel/vulkan/genX_cmd_buffer.c | 23 |
6 files changed, 35 insertions, 15 deletions
diff --git a/src/intel/blorp/blorp_genX_exec.h b/src/intel/blorp/blorp_genX_exec.h index 992bc9959a1..f3a96fbd58c 100644 --- a/src/intel/blorp/blorp_genX_exec.h +++ b/src/intel/blorp/blorp_genX_exec.h @@ -310,10 +310,11 @@ blorp_emit_vertex_buffers(struct blorp_batch *batch, uint32_t num_vbs = 2; if (params->dst_clear_color_as_input) { + const unsigned clear_color_size = + GEN_GEN < 10 ? batch->blorp->isl_dev->ss.clear_value_size : 4 * 4; blorp_fill_vertex_buffer_state(batch, vb, num_vbs++, params->dst.clear_color_addr, - batch->blorp->isl_dev->ss.clear_value_size, - 0); + clear_color_size, 0); } const unsigned num_dwords = 1 + num_vbs * GENX(VERTEX_BUFFER_STATE_length); diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c index 1a32c028183..875c691b43e 100644 --- a/src/intel/isl/isl.c +++ b/src/intel/isl/isl.c @@ -73,6 +73,10 @@ isl_device_init(struct isl_device *dev, dev->ss.size = RENDER_SURFACE_STATE_length(info) * 4; dev->ss.align = isl_align(dev->ss.size, 32); + dev->ss.clear_color_state_size = CLEAR_COLOR_length(info) * 4; + dev->ss.clear_color_state_offset = + RENDER_SURFACE_STATE_ClearValueAddress_start(info) / 32 * 4; + dev->ss.clear_value_size = isl_align(RENDER_SURFACE_STATE_RedClearColor_bits(info) + RENDER_SURFACE_STATE_GreenClearColor_bits(info) + diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h index 0da6abb71d4..2edf0522e32 100644 --- a/src/intel/isl/isl.h +++ b/src/intel/isl/isl.h @@ -963,6 +963,12 @@ struct isl_device { uint8_t aux_addr_offset; /* Rounded up to the nearest dword to simplify GPU memcpy operations. */ + + /* size of the state buffer used to store the clear color + extra + * additional space used by the hardware */ + uint8_t clear_color_state_size; + uint8_t clear_color_state_offset; + /* size of the clear color itself - used to copy it to/from a BO */ uint8_t clear_value_size; uint8_t clear_value_offset; } ss; diff --git a/src/intel/vulkan/anv_image.c b/src/intel/vulkan/anv_image.c index b20d791751d..d9b5d266020 100644 --- a/src/intel/vulkan/anv_image.c +++ b/src/intel/vulkan/anv_image.c @@ -267,8 +267,12 @@ add_aux_state_tracking_buffer(struct anv_image *image, (image->planes[plane].offset + image->planes[plane].size)); } + const unsigned clear_color_state_size = device->info.gen >= 10 ? + device->isl_dev.ss.clear_color_state_size : + device->isl_dev.ss.clear_value_size; + /* Clear color and fast clear type */ - unsigned state_size = device->isl_dev.ss.clear_value_size + 4; + unsigned state_size = clear_color_state_size + 4; /* We only need to track compression on CCS_E surfaces. */ if (image->planes[plane].aux_usage == ISL_AUX_USAGE_CCS_E) { diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h index 3b08939f6cc..d7a04438165 100644 --- a/src/intel/vulkan/anv_private.h +++ b/src/intel/vulkan/anv_private.h @@ -2614,7 +2614,11 @@ anv_image_get_fast_clear_type_addr(const struct anv_device *device, { struct anv_address addr = anv_image_get_clear_color_addr(device, image, aspect); - addr.offset += device->isl_dev.ss.clear_value_size; + + const unsigned clear_color_state_size = device->info.gen >= 10 ? + device->isl_dev.ss.clear_color_state_size : + device->isl_dev.ss.clear_value_size; + addr.offset += clear_color_state_size; return addr; } diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index 3da6dffa1a9..8287d67a53d 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -826,35 +826,36 @@ init_fast_clear_color(struct anv_cmd_buffer *cmd_buffer, */ struct anv_address addr = anv_image_get_clear_color_addr(cmd_buffer->device, image, aspect); - unsigned i = 0; - for (; i < cmd_buffer->device->isl_dev.ss.clear_value_size; i += 4) { - anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_DATA_IMM), sdi) { - sdi.Address = addr; - if (GEN_GEN >= 9) { + if (GEN_GEN >= 9) { + for (unsigned i = 0; i < 4; i++) { + anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_DATA_IMM), sdi) { + sdi.Address = addr; + sdi.Address.offset += i * 4; /* MCS buffers on SKL+ can only have 1/0 clear colors. */ assert(image->samples > 1); sdi.ImmediateData = 0; - } else if (GEN_VERSIONx10 >= 75) { + } + } + } else { + anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_DATA_IMM), sdi) { + sdi.Address = addr; + if (GEN_GEN >= 8 || GEN_IS_HASWELL) { /* Pre-SKL, the dword containing the clear values also contains * other fields, so we need to initialize those fields to match the * values that would be in a color attachment. */ - assert(i == 0); sdi.ImmediateData = ISL_CHANNEL_SELECT_RED << 25 | ISL_CHANNEL_SELECT_GREEN << 22 | ISL_CHANNEL_SELECT_BLUE << 19 | ISL_CHANNEL_SELECT_ALPHA << 16; - } else if (GEN_VERSIONx10 == 70) { + } else if (GEN_GEN == 7) { /* On IVB, the dword containing the clear values also contains * other fields that must be zero or can be zero. */ - assert(i == 0); sdi.ImmediateData = 0; } } - - addr.offset += 4; } } |