diff options
| -rw-r--r-- | src/intel/vulkan/anv_private.h | 1 | ||||
| -rw-r--r-- | src/intel/vulkan/gen7_cmd_buffer.c | 4 | ||||
| -rw-r--r-- | src/intel/vulkan/gen8_cmd_buffer.c | 8 | ||||
| -rw-r--r-- | src/intel/vulkan/genX_pipeline.c | 6 |
4 files changed, 17 insertions, 2 deletions
diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h index ec791a42871..89ae8183799 100644 --- a/src/intel/vulkan/anv_private.h +++ b/src/intel/vulkan/anv_private.h @@ -1471,6 +1471,7 @@ struct anv_pipeline { uint32_t cs_right_mask; + bool writes_stencil; bool depth_clamp_enable; struct { diff --git a/src/intel/vulkan/gen7_cmd_buffer.c b/src/intel/vulkan/gen7_cmd_buffer.c index 8d68aba9c9a..013ed8718a4 100644 --- a/src/intel/vulkan/gen7_cmd_buffer.c +++ b/src/intel/vulkan/gen7_cmd_buffer.c @@ -212,6 +212,10 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer) .BackfaceStencilTestMask = d->stencil_compare_mask.back & 0xff, .BackfaceStencilWriteMask = d->stencil_write_mask.back & 0xff, + + .StencilBufferWriteEnable = + (d->stencil_write_mask.front || d->stencil_write_mask.back) && + pipeline->writes_stencil, }; GENX(DEPTH_STENCIL_STATE_pack)(NULL, depth_stencil_dw, &depth_stencil); diff --git a/src/intel/vulkan/gen8_cmd_buffer.c b/src/intel/vulkan/gen8_cmd_buffer.c index ab68872a260..8c8de622eb8 100644 --- a/src/intel/vulkan/gen8_cmd_buffer.c +++ b/src/intel/vulkan/gen8_cmd_buffer.c @@ -224,6 +224,10 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer) .BackfaceStencilTestMask = d->stencil_compare_mask.back & 0xff, .BackfaceStencilWriteMask = d->stencil_write_mask.back & 0xff, + + .StencilBufferWriteEnable = + (d->stencil_write_mask.front || d->stencil_write_mask.back) && + pipeline->writes_stencil, }; GENX(3DSTATE_WM_DEPTH_STENCIL_pack)(NULL, wm_depth_stencil_dw, &wm_depth_stencil); @@ -271,6 +275,10 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer) .StencilReferenceValue = d->stencil_reference.front & 0xff, .BackfaceStencilReferenceValue = d->stencil_reference.back & 0xff, + + .StencilBufferWriteEnable = + (d->stencil_write_mask.front || d->stencil_write_mask.back) && + pipeline->writes_stencil, }; GEN9_3DSTATE_WM_DEPTH_STENCIL_pack(NULL, dwords, &wm_depth_stencil); diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c index 55d1e5571d7..f641661db1b 100644 --- a/src/intel/vulkan/genX_pipeline.c +++ b/src/intel/vulkan/genX_pipeline.c @@ -663,12 +663,15 @@ emit_ds_state(struct anv_pipeline *pipeline, /* We're going to OR this together with the dynamic state. We need * to make sure it's initialized to something useful. */ + pipeline->writes_stencil = false; memset(depth_stencil_dw, 0, sizeof(depth_stencil_dw)); return; } /* VkBool32 depthBoundsTestEnable; // optional (depth_bounds_test) */ + pipeline->writes_stencil = info->stencilTestEnable; + #if GEN_GEN <= 7 struct GENX(DEPTH_STENCIL_STATE) depth_stencil = { #else @@ -680,7 +683,6 @@ emit_ds_state(struct anv_pipeline *pipeline, .DoubleSidedStencilEnable = true, .StencilTestEnable = info->stencilTestEnable, - .StencilBufferWriteEnable = info->stencilTestEnable, .StencilFailOp = vk_to_gen_stencil_op[info->front.failOp], .StencilPassDepthPassOp = vk_to_gen_stencil_op[info->front.passOp], .StencilPassDepthFailOp = vk_to_gen_stencil_op[info->front.depthFailOp], @@ -707,7 +709,7 @@ emit_ds_state(struct anv_pipeline *pipeline, } if (!(aspects & VK_IMAGE_ASPECT_STENCIL_BIT)) { - depth_stencil.StencilBufferWriteEnable = false; + pipeline->writes_stencil = false; depth_stencil.StencilTestFunction = PREFILTEROPALWAYS; depth_stencil.BackfaceStencilTestFunction = PREFILTEROPALWAYS; } |