diff options
| -rw-r--r-- | src/gallium/auxiliary/gallivm/lp_bld_gather.c | 30 |
1 files changed, 28 insertions, 2 deletions
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_gather.c b/src/gallium/auxiliary/gallivm/lp_bld_gather.c index ccd03765c73..7d11dcd3b64 100644 --- a/src/gallium/auxiliary/gallivm/lp_bld_gather.c +++ b/src/gallium/auxiliary/gallivm/lp_bld_gather.c @@ -234,13 +234,39 @@ lp_build_gather_elem_vec(struct gallivm_state *gallivm, */ res = LLVMBuildZExt(gallivm->builder, res, dst_elem_type, ""); - if (vector_justify) { #ifdef PIPE_ARCH_BIG_ENDIAN + if (vector_justify) { res = LLVMBuildShl(gallivm->builder, res, LLVMConstInt(dst_elem_type, dst_type.width - src_width, 0), ""); -#endif } + if (src_width == 48) { + /* Load 3x16 bit vector. + * The sequence of loads on big-endian hardware proceeds as follows. + * 16-bit fields are denoted by X, Y, Z, and 0. In memory, the sequence + * of three fields appears in the order X, Y, Z. + * + * Load 32-bit word: 0.0.X.Y + * Load 16-bit halfword: 0.0.0.Z + * Rotate left: 0.X.Y.0 + * Bitwise OR: 0.X.Y.Z + * + * The order in which we need the fields in the result is 0.Z.Y.X, + * the same as on little-endian; permute 16-bit fields accordingly + * within 64-bit register: + */ + LLVMValueRef shuffles[4] = { + lp_build_const_int32(gallivm, 2), + lp_build_const_int32(gallivm, 1), + lp_build_const_int32(gallivm, 0), + lp_build_const_int32(gallivm, 3), + }; + res = LLVMBuildBitCast(gallivm->builder, res, + lp_build_vec_type(gallivm, lp_type_uint_vec(16, 4*16)), ""); + res = LLVMBuildShuffleVector(gallivm->builder, res, res, LLVMConstVector(shuffles, 4), ""); + res = LLVMBuildBitCast(gallivm->builder, res, dst_elem_type, ""); + } +#endif } } return res; |