diff options
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_clear.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_clear.c b/src/mesa/drivers/dri/i965/brw_clear.c index 1dfff090c08..18b8fcbe200 100644 --- a/src/mesa/drivers/dri/i965/brw_clear.c +++ b/src/mesa/drivers/dri/i965/brw_clear.c @@ -239,6 +239,14 @@ brw_clear(struct gl_context *ctx, GLbitfield mask) } } + if (mask & BUFFER_BIT_STENCIL) { + struct intel_renderbuffer *stencil_irb = + intel_get_renderbuffer(fb, BUFFER_STENCIL); + struct intel_mipmap_tree *mt = stencil_irb->mt; + if (mt && mt->stencil_mt) + mt->stencil_mt->r8stencil_needs_update = true; + } + /* BLORP is currently only supported on Gen6+. */ if (brw->gen >= 6 && (mask & BUFFER_BITS_COLOR)) { const bool encode_srgb = ctx->Color.sRGBEnabled; |