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-rw-r--r--src/intel/blorp/blorp.h10
-rw-r--r--src/intel/blorp/blorp_clear.c12
-rw-r--r--src/intel/blorp/blorp_priv.h7
-rw-r--r--src/mesa/drivers/dri/i965/brw_blorp.c15
4 files changed, 29 insertions, 15 deletions
diff --git a/src/intel/blorp/blorp.h b/src/intel/blorp/blorp.h
index 4e5a3a33ad6..823475b6075 100644
--- a/src/intel/blorp/blorp.h
+++ b/src/intel/blorp/blorp.h
@@ -167,10 +167,18 @@ blorp_clear_attachments(struct blorp_batch *batch,
bool clear_depth, float depth_value,
uint8_t stencil_mask, uint8_t stencil_value);
+enum blorp_fast_clear_op {
+ BLORP_FAST_CLEAR_OP_NONE = 0,
+ BLORP_FAST_CLEAR_OP_CLEAR,
+ BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL,
+ BLORP_FAST_CLEAR_OP_RESOLVE_FULL,
+};
+
void
blorp_ccs_resolve(struct blorp_batch *batch,
struct blorp_surf *surf, uint32_t level, uint32_t layer,
- enum isl_format format);
+ enum isl_format format,
+ enum blorp_fast_clear_op resolve_op);
/**
* For an overview of the HiZ operations, see the following sections of the
diff --git a/src/intel/blorp/blorp_clear.c b/src/intel/blorp/blorp_clear.c
index 5c40e2f0557..83ec57e556c 100644
--- a/src/intel/blorp/blorp_clear.c
+++ b/src/intel/blorp/blorp_clear.c
@@ -543,7 +543,8 @@ blorp_clear_attachments(struct blorp_batch *batch,
void
blorp_ccs_resolve(struct blorp_batch *batch,
struct blorp_surf *surf, uint32_t level, uint32_t layer,
- enum isl_format format)
+ enum isl_format format,
+ enum blorp_fast_clear_op resolve_op)
{
struct blorp_params params;
blorp_params_init(&params);
@@ -586,14 +587,13 @@ blorp_ccs_resolve(struct blorp_batch *batch,
params.y1 = ALIGN(params.y1, y_scaledown) / y_scaledown;
if (batch->blorp->isl_dev->info->gen >= 9) {
- if (params.dst.aux_usage == ISL_AUX_USAGE_CCS_E)
- params.fast_clear_op = BLORP_FAST_CLEAR_OP_RESOLVE_FULL;
- else
- params.fast_clear_op = BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL;
+ assert(resolve_op == BLORP_FAST_CLEAR_OP_RESOLVE_FULL ||
+ resolve_op == BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL);
} else {
/* Broadwell and earlier do not have a partial resolve */
- params.fast_clear_op = BLORP_FAST_CLEAR_OP_RESOLVE_FULL;
+ assert(resolve_op == BLORP_FAST_CLEAR_OP_RESOLVE_FULL);
}
+ params.fast_clear_op = resolve_op;
/* Note: there is no need to initialize push constants because it doesn't
* matter what data gets dispatched to the render target. However, we must
diff --git a/src/intel/blorp/blorp_priv.h b/src/intel/blorp/blorp_priv.h
index 71805ade157..409c69d2332 100644
--- a/src/intel/blorp/blorp_priv.h
+++ b/src/intel/blorp/blorp_priv.h
@@ -44,13 +44,6 @@ enum {
BLORP_NUM_BT_ENTRIES
};
-enum blorp_fast_clear_op {
- BLORP_FAST_CLEAR_OP_NONE = 0,
- BLORP_FAST_CLEAR_OP_CLEAR,
- BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL,
- BLORP_FAST_CLEAR_OP_RESOLVE_FULL,
-};
-
struct brw_blorp_surface_info
{
bool enabled;
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c
index 2771f1466db..95a2bb7bb3c 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -943,10 +943,23 @@ brw_blorp_resolve_color(struct brw_context *brw, struct intel_mipmap_tree *mt)
unsigned level = 0;
blorp_surf_for_miptree(brw, &surf, mt, true, &level, isl_tmp);
+ enum blorp_fast_clear_op resolve_op;
+ if (brw->gen >= 9) {
+ if (surf.aux_usage == ISL_AUX_USAGE_CCS_E)
+ resolve_op = BLORP_FAST_CLEAR_OP_RESOLVE_FULL;
+ else
+ resolve_op = BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL;
+ } else {
+ assert(surf.aux_usage == ISL_AUX_USAGE_CCS_D);
+ /* Broadwell and earlier do not have a partial resolve */
+ resolve_op = BLORP_FAST_CLEAR_OP_RESOLVE_FULL;
+ }
+
struct blorp_batch batch;
blorp_batch_init(&brw->blorp, &batch, brw, 0);
blorp_ccs_resolve(&batch, &surf, 0 /* level */, 0 /* layer */,
- brw_blorp_to_isl_format(brw, format, true));
+ brw_blorp_to_isl_format(brw, format, true),
+ resolve_op);
blorp_batch_finish(&batch);
mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_RESOLVED;