diff options
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_context.c | 56 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 55 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 6 |
3 files changed, 71 insertions, 46 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c index 94a166b4f3c..5e901dfac71 100644 --- a/src/mesa/drivers/dri/i965/brw_context.c +++ b/src/mesa/drivers/dri/i965/brw_context.c @@ -186,42 +186,6 @@ intel_disable_rb_aux_buffer(struct brw_context *brw, const struct brw_bo *bo) return found; } -/* On Gen9 color buffers may be compressed by the hardware (lossless - * compression). There are, however, format restrictions and care needs to be - * taken that the sampler engine is capable for re-interpreting a buffer with - * format different the buffer was originally written with. - * - * For example, SRGB formats are not compressible and the sampler engine isn't - * capable of treating RGBA_UNORM as SRGB_ALPHA. In such a case the underlying - * color buffer needs to be resolved so that the sampling surface can be - * sampled as non-compressed (i.e., without the auxiliary MCS buffer being - * set). - */ -static bool -intel_texture_view_requires_resolve(struct brw_context *brw, - struct intel_texture_object *intel_tex) -{ - if (brw->gen < 9 || - !intel_miptree_is_lossless_compressed(brw, intel_tex->mt)) - return false; - - const enum isl_format isl_format = - brw_isl_format_for_mesa_format(intel_tex->_Format); - - if (isl_format_supports_ccs_e(&brw->screen->devinfo, isl_format)) - return false; - - perf_debug("Incompatible sampling format (%s) for rbc (%s)\n", - _mesa_get_format_name(intel_tex->_Format), - _mesa_get_format_name(intel_tex->mt->format)); - - if (intel_disable_rb_aux_buffer(brw, intel_tex->mt->bo)) - perf_debug("Sampling renderbuffer with non-compressible format - " - "turning off compression"); - - return true; -} - static void intel_update_state(struct gl_context * ctx, GLuint new_state) { @@ -260,16 +224,16 @@ intel_update_state(struct gl_context * ctx, GLuint new_state) /* We need inte_texture_object::_Format to be valid */ intel_finalize_mipmap_tree(brw, i); - if (intel_miptree_sample_with_hiz(brw, tex_obj->mt)) - intel_miptree_all_slices_resolve_hiz(brw, tex_obj->mt); - else - intel_miptree_all_slices_resolve_depth(brw, tex_obj->mt); - /* Sampling engine understands lossless compression and resolving - * those surfaces should be skipped for performance reasons. - */ - const int flags = intel_texture_view_requires_resolve(brw, tex_obj) ? - 0 : INTEL_MIPTREE_IGNORE_CCS_E; - intel_miptree_all_slices_resolve_color(brw, tex_obj->mt, flags); + bool aux_supported; + intel_miptree_prepare_texture(brw, tex_obj->mt, tex_obj->_Format, + &aux_supported); + + if (!aux_supported && brw->gen >= 9 && + intel_disable_rb_aux_buffer(brw, tex_obj->mt->bo)) { + perf_debug("Sampling renderbuffer with non-compressible format - " + "turning off compression"); + } + brw_render_cache_set_check_flush(brw, tex_obj->mt->bo); if (tex_obj->base.StencilSampling || diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index 800b1626964..033dd80e121 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c @@ -2399,6 +2399,61 @@ intel_miptree_set_aux_state(struct brw_context *brw, } } +/* On Gen9 color buffers may be compressed by the hardware (lossless + * compression). There are, however, format restrictions and care needs to be + * taken that the sampler engine is capable for re-interpreting a buffer with + * format different the buffer was originally written with. + * + * For example, SRGB formats are not compressible and the sampler engine isn't + * capable of treating RGBA_UNORM as SRGB_ALPHA. In such a case the underlying + * color buffer needs to be resolved so that the sampling surface can be + * sampled as non-compressed (i.e., without the auxiliary MCS buffer being + * set). + */ +static bool +intel_texture_view_requires_resolve(struct brw_context *brw, + struct intel_mipmap_tree *mt, + mesa_format format) +{ + if (brw->gen < 9 || + !intel_miptree_is_lossless_compressed(brw, mt)) + return false; + + const enum isl_format isl_format = brw_isl_format_for_mesa_format(format); + + if (isl_format_supports_ccs_e(&brw->screen->devinfo, isl_format)) + return false; + + perf_debug("Incompatible sampling format (%s) for rbc (%s)\n", + _mesa_get_format_name(format), + _mesa_get_format_name(mt->format)); + + return true; +} + +void +intel_miptree_prepare_texture(struct brw_context *brw, + struct intel_mipmap_tree *mt, + mesa_format view_format, + bool *aux_supported_out) +{ + bool aux_supported; + if (_mesa_is_format_color_format(mt->format)) { + aux_supported = intel_miptree_is_lossless_compressed(brw, mt) && + !intel_texture_view_requires_resolve(brw, mt, view_format); + } else if (mt->format == MESA_FORMAT_S_UINT8) { + aux_supported = false; + } else { + aux_supported = intel_miptree_sample_with_hiz(brw, mt); + } + + intel_miptree_prepare_access(brw, mt, 0, INTEL_REMAINING_LEVELS, + 0, INTEL_REMAINING_LAYERS, + aux_supported, aux_supported); + if (aux_supported_out) + *aux_supported_out = aux_supported; +} + /** * Make it possible to share the BO backing the given miptree with another * process or another miptree. diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h index a3d68e62f37..52008d73b73 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h @@ -1046,6 +1046,12 @@ intel_miptree_access_raw(struct brw_context *brw, } void +intel_miptree_prepare_texture(struct brw_context *brw, + struct intel_mipmap_tree *mt, + mesa_format view_format, + bool *aux_supported_out); + +void intel_miptree_make_shareable(struct brw_context *brw, struct intel_mipmap_tree *mt); |