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-rw-r--r--src/mesa/drivers/dri/intel/intel_fbo.c13
-rw-r--r--src/mesa/drivers/dri/intel/intel_fbo.h7
-rw-r--r--src/mesa/drivers/dri/intel/intel_screen.c39
-rw-r--r--src/mesa/drivers/dri/intel/intel_screen.h6
-rw-r--r--src/mesa/drivers/dri/intel/intel_span.c7
-rw-r--r--src/mesa/drivers/dri/intel/intel_span.h7
6 files changed, 52 insertions, 27 deletions
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c b/src/mesa/drivers/dri/intel/intel_fbo.c
index bc0b5794295..3a3ce68c595 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.c
+++ b/src/mesa/drivers/dri/intel/intel_fbo.c
@@ -376,7 +376,8 @@ intel_renderbuffer_set_region(struct intel_renderbuffer *rb,
* not a user-created renderbuffer.
*/
struct intel_renderbuffer *
-intel_create_renderbuffer(GLenum intFormat, int tiling)
+intel_create_renderbuffer(intelScreenPrivate *intelScreen,
+ GLenum intFormat, enum tiling_mode tiling)
{
GET_CURRENT_CONTEXT(ctx);
@@ -449,8 +450,14 @@ intel_create_renderbuffer(GLenum intFormat, int tiling)
irb->Base.Delete = intel_delete_renderbuffer;
irb->Base.AllocStorage = intel_alloc_window_storage;
irb->Base.GetPointer = intel_get_pointer;
- /* This sets the Get/PutRow/Value functions */
- intel_set_span_functions(&irb->Base, tiling);
+ /* This sets the Get/PutRow/Value functions. In classic mode, all access
+ * is through the aperture and will be swizzled by the fence registers, so
+ * we don't need the span functions to perfom tile swizzling
+ */
+ if (intelScreen->ttm)
+ intel_set_span_functions(&irb->Base, tiling);
+ else
+ intel_set_span_functions(&irb->Base, INTEL_TILE_NONE);
return irb;
}
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.h b/src/mesa/drivers/dri/intel/intel_fbo.h
index 9e085a1992f..23af5939605 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.h
+++ b/src/mesa/drivers/dri/intel/intel_fbo.h
@@ -28,9 +28,9 @@
#ifndef INTEL_FBO_H
#define INTEL_FBO_H
+#include "intel_screen.h"
struct intel_context;
-struct intel_region;
/**
* Intel framebuffer, derived from gl_framebuffer.
@@ -72,7 +72,7 @@ struct intel_renderbuffer
struct intel_region *region;
void *pfMap; /* possibly paged flipped map pointer */
GLuint pfPitch; /* possibly paged flipped pitch */
- int tiling;
+ enum tiling_mode tiling;
GLboolean RenderToTexture; /* RTT? */
GLuint PairedDepth; /**< only used if this is a depth renderbuffer */
@@ -91,7 +91,8 @@ intel_renderbuffer_set_region(struct intel_renderbuffer *irb,
struct intel_region *region);
extern struct intel_renderbuffer *
-intel_create_renderbuffer(GLenum intFormat, int tiling);
+intel_create_renderbuffer(intelScreenPrivate *intelScreen,
+ GLenum intFormat, enum tiling_mode tiling);
extern void intel_fbo_init(struct intel_context *intel);
diff --git a/src/mesa/drivers/dri/intel/intel_screen.c b/src/mesa/drivers/dri/intel/intel_screen.c
index 6597dbffed8..9e4f48fbd77 100644
--- a/src/mesa/drivers/dri/intel/intel_screen.c
+++ b/src/mesa/drivers/dri/intel/intel_screen.c
@@ -528,6 +528,7 @@ intelCreateBuffer(__DRIscreenPrivate * driScrnPriv,
GLboolean swStencil = (mesaVis->stencilBits > 0 &&
mesaVis->depthBits != 24);
GLenum rgbFormat = (mesaVis->redBits == 5 ? GL_RGB5 : GL_RGBA8);
+ enum tiling_mode tiling;
struct intel_framebuffer *intel_fb = CALLOC_STRUCT(intel_framebuffer);
@@ -537,34 +538,46 @@ intelCreateBuffer(__DRIscreenPrivate * driScrnPriv,
_mesa_initialize_framebuffer(&intel_fb->Base, mesaVis);
/* setup the hardware-based renderbuffers */
+ /* We get only a boolean value from the DDX for whether tiling is
+ * enabled, so we have to guess when it's Y and not X (965 depth).
+ */
{
- intel_fb->color_rb[0] = intel_create_renderbuffer(rgbFormat,
- screen->ttm ? screen->front.tiled : INTEL_TILE_NONE);
+ tiling = screen->front.tiled ? INTEL_TILE_X : INTEL_TILE_NONE;
+ intel_fb->color_rb[0] = intel_create_renderbuffer(screen,
+ rgbFormat, tiling);
_mesa_add_renderbuffer(&intel_fb->Base, BUFFER_FRONT_LEFT,
&intel_fb->color_rb[0]->Base);
}
if (mesaVis->doubleBufferMode) {
- intel_fb->color_rb[1] = intel_create_renderbuffer(rgbFormat,
- screen->ttm ? screen->back.tiled : INTEL_TILE_NONE);
+ tiling = screen->back.tiled ? INTEL_TILE_X : INTEL_TILE_NONE;
+ intel_fb->color_rb[1] = intel_create_renderbuffer(screen,
+ rgbFormat, tiling);
+
_mesa_add_renderbuffer(&intel_fb->Base, BUFFER_BACK_LEFT,
&intel_fb->color_rb[1]->Base);
if (screen->third.handle) {
struct gl_renderbuffer *tmp_rb = NULL;
-
- intel_fb->color_rb[2] = intel_create_renderbuffer(rgbFormat,
- screen->ttm ? screen->third.tiled : INTEL_TILE_NONE);
+ tiling = screen->third.tiled ? INTEL_TILE_X : INTEL_TILE_NONE;
+ intel_fb->color_rb[2] = intel_create_renderbuffer(screen,
+ rgbFormat,
+ tiling);
_mesa_reference_renderbuffer(&tmp_rb, &intel_fb->color_rb[2]->Base);
}
}
+#ifdef I915
+ tiling = screen->depth.tiled ? INTEL_TILE_X : INTEL_TILE_NONE;
+#else
+ tiling = screen->depth.tiled ? INTEL_TILE_Y : INTEL_TILE_NONE;
+#endif
if (mesaVis->depthBits == 24) {
if (mesaVis->stencilBits == 8) {
/* combined depth/stencil buffer */
struct intel_renderbuffer *depthStencilRb
- = intel_create_renderbuffer(GL_DEPTH24_STENCIL8_EXT,
- screen->ttm ? screen->depth.tiled : INTEL_TILE_NONE);
+ = intel_create_renderbuffer(screen,
+ GL_DEPTH24_STENCIL8_EXT, tiling);
/* note: bind RB to two attachment points */
_mesa_add_renderbuffer(&intel_fb->Base, BUFFER_DEPTH,
&depthStencilRb->Base);
@@ -572,8 +585,8 @@ intelCreateBuffer(__DRIscreenPrivate * driScrnPriv,
&depthStencilRb->Base);
} else {
struct intel_renderbuffer *depthRb
- = intel_create_renderbuffer(GL_DEPTH_COMPONENT24,
- screen->ttm ? screen->depth.tiled : INTEL_TILE_NONE);
+ = intel_create_renderbuffer(screen,
+ GL_DEPTH_COMPONENT24, tiling);
_mesa_add_renderbuffer(&intel_fb->Base, BUFFER_DEPTH,
&depthRb->Base);
}
@@ -581,8 +594,8 @@ intelCreateBuffer(__DRIscreenPrivate * driScrnPriv,
else if (mesaVis->depthBits == 16) {
/* just 16-bit depth buffer, no hw stencil */
struct intel_renderbuffer *depthRb
- = intel_create_renderbuffer(GL_DEPTH_COMPONENT16,
- screen->ttm ? screen->depth.tiled : INTEL_TILE_NONE);
+ = intel_create_renderbuffer(screen,
+ GL_DEPTH_COMPONENT16, tiling);
_mesa_add_renderbuffer(&intel_fb->Base, BUFFER_DEPTH, &depthRb->Base);
}
diff --git a/src/mesa/drivers/dri/intel/intel_screen.h b/src/mesa/drivers/dri/intel/intel_screen.h
index 9a73b139517..648bf61240f 100644
--- a/src/mesa/drivers/dri/intel/intel_screen.h
+++ b/src/mesa/drivers/dri/intel/intel_screen.h
@@ -33,6 +33,12 @@
#include "i915_drm.h"
#include "xmlconfig.h"
+enum tiling_mode {
+ INTEL_TILE_NONE,
+ INTEL_TILE_X,
+ INTEL_TILE_Y
+};
+
/* XXX: change name or eliminate to avoid conflict with "struct
* intel_region"!!!
*/
diff --git a/src/mesa/drivers/dri/intel/intel_span.c b/src/mesa/drivers/dri/intel/intel_span.c
index 8d7d913ca9a..6138b262f47 100644
--- a/src/mesa/drivers/dri/intel/intel_span.c
+++ b/src/mesa/drivers/dri/intel/intel_span.c
@@ -168,7 +168,7 @@ static GLubyte *y_tile_swizzle(struct intel_renderbuffer *irb, struct intel_cont
int x_tile_number, y_tile_number;
int tile_off, tile_base;
- tile_stride = (irb->pfPitch * irb->region->cpp) << 3;
+ tile_stride = (irb->pfPitch * irb->region->cpp) << 5;
x += intel->drawX;
y += intel->drawY;
@@ -181,7 +181,8 @@ static GLubyte *y_tile_swizzle(struct intel_renderbuffer *irb, struct intel_cont
x_tile_number = xbyte >> 7;
y_tile_number = y >> 5;
- tile_off = ((x_tile_off & ~0xf) << 5) + (y_tile_off << 4) + (x_tile_off & 0xf);
+ tile_off = ((x_tile_off & ~0xf) << 5) + (y_tile_off << 4) +
+ (x_tile_off & 0xf);
tile_base = (x_tile_number << 12) + y_tile_number * tile_stride;
return buf + tile_base + tile_off;
@@ -670,7 +671,7 @@ intelInitSpanFuncs(GLcontext * ctx)
* These are used for the software fallbacks.
*/
void
-intel_set_span_functions(struct gl_renderbuffer *rb, int tiling)
+intel_set_span_functions(struct gl_renderbuffer *rb, enum tiling_mode tiling)
{
if (rb->_ActualFormat == GL_RGB5) {
/* 565 RGB */
diff --git a/src/mesa/drivers/dri/intel/intel_span.h b/src/mesa/drivers/dri/intel/intel_span.h
index c56e5e1611d..1b47c2829c9 100644
--- a/src/mesa/drivers/dri/intel/intel_span.h
+++ b/src/mesa/drivers/dri/intel/intel_span.h
@@ -33,10 +33,7 @@ extern void intelInitSpanFuncs(GLcontext * ctx);
extern void intelSpanRenderFinish(GLcontext * ctx);
extern void intelSpanRenderStart(GLcontext * ctx);
-extern void intel_set_span_functions(struct gl_renderbuffer *rb, int tiling);
-
-#define INTEL_TILE_NONE 0
-#define INTEL_TILE_X 1
-#define INTEL_TILE_Y 2
+extern void intel_set_span_functions(struct gl_renderbuffer *rb,
+ enum tiling_mode tiling);
#endif
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-28 06:22:45 +0000