diff options
| -rw-r--r-- | src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp index ade315dc3ce..7da9b0be7e8 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp @@ -567,6 +567,31 @@ NVC0LoweringPass::handleTEX(TexInstruction *i) const int lyr = arg - (i->tex.target.isMS() ? 2 : 1); const int chipset = prog->getTarget()->getChipset(); + // Arguments to the TEX instruction are a little insane. Even though the + // encoding is identical between SM20 and SM30, the arguments mean + // different things between Fermi and Kepler+. A lot of arguments are + // optional based on flags passed to the instruction. This summarizes the + // order of things. + // + // Fermi: + // array/indirect + // coords + // sample + // lod bias + // depth compare + // offsets: + // - tg4: 8 bits each, either 2 (1 offset reg) or 8 (2 offset reg) + // - other: 4 bits each, single reg + // + // Kepler+: + // indirect handle + // array (+ offsets for txd in upper 16 bits) + // coords + // sample + // lod bias + // depth compare + // offsets (same as fermi, except txd which takes it with array) + if (chipset >= NVISA_GK104_CHIPSET) { if (i->tex.rIndirectSrc >= 0 || i->tex.sIndirectSrc >= 0) { // XXX this ignores tsc, and assumes a 1:1 mapping |