diff options
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 6 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 6 |
2 files changed, 8 insertions, 4 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp index 0ed0ee35799..d860700d6d8 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp @@ -1483,6 +1483,7 @@ void fs_generator::generate_code(const cfg_t *cfg) { int start_offset = p->next_insn_offset; + int loop_count = 0; struct annotation_info annotation; memset(&annotation, 0, sizeof(annotation)); @@ -1739,6 +1740,7 @@ fs_generator::generate_code(const cfg_t *cfg) case BRW_OPCODE_WHILE: brw_WHILE(p); + loop_count++; break; case SHADER_OPCODE_RCP: @@ -1966,9 +1968,9 @@ fs_generator::generate_code(const cfg_t *cfg) fprintf(stderr, "Native code for blorp program (SIMD%d dispatch):\n", dispatch_width); } - fprintf(stderr, "SIMD%d shader: %d instructions. Compacted %d to %d" + fprintf(stderr, "SIMD%d shader: %d instructions. %d loops. Compacted %d to %d" " bytes (%.0f%%)\n", - dispatch_width, before_size / 16, before_size, after_size, + dispatch_width, before_size / 16, loop_count, before_size, after_size, 100.0f * (before_size - after_size) / before_size); const struct gl_program *prog = fp ? &fp->Base : NULL; diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp index c727f1a5c5f..954ce640baa 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp @@ -982,6 +982,7 @@ vec4_generator::generate_code(const cfg_t *cfg) { struct annotation_info annotation; memset(&annotation, 0, sizeof(annotation)); + int loop_count = 0; foreach_block_and_inst (block, vec4_instruction, inst, cfg) { struct brw_reg src[3], dst; @@ -1199,6 +1200,7 @@ vec4_generator::generate_code(const cfg_t *cfg) case BRW_OPCODE_WHILE: brw_WHILE(p); + loop_count++; break; case SHADER_OPCODE_RCP: @@ -1351,9 +1353,9 @@ vec4_generator::generate_code(const cfg_t *cfg) } else { fprintf(stderr, "Native code for vertex program %d:\n", prog->Id); } - fprintf(stderr, "vec4 shader: %d instructions. Compacted %d to %d" + fprintf(stderr, "vec4 shader: %d instructions. %d loops. Compacted %d to %d" " bytes (%.0f%%)\n", - before_size / 16, before_size, after_size, + before_size / 16, loop_count, before_size, after_size, 100.0f * (before_size - after_size) / before_size); dump_assembly(p->store, annotation.ann_count, annotation.ann, brw, prog); |