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-rw-r--r--src/gallium/drivers/radeon/AMDGPUInstructions.td7
-rw-r--r--src/gallium/drivers/radeon/R600ISelLowering.cpp16
-rw-r--r--src/gallium/drivers/radeon/R600Instructions.td7
-rw-r--r--src/gallium/drivers/radeon/R600LowerShaderInstructions.cpp27
4 files changed, 23 insertions, 34 deletions
diff --git a/src/gallium/drivers/radeon/AMDGPUInstructions.td b/src/gallium/drivers/radeon/AMDGPUInstructions.td
index d126c7902aa..abe90a4f12f 100644
--- a/src/gallium/drivers/radeon/AMDGPUInstructions.td
+++ b/src/gallium/drivers/radeon/AMDGPUInstructions.td
@@ -55,13 +55,6 @@ let isCodeGenOnly = 1 in {
"RESERVE_REG $dst, $src",
[(set GPRF32:$dst, (int_AMDGPU_reserve_reg imm:$src))]
>;
-
- def STORE_OUTPUT: AMDGPUShaderInst <
- (outs GPRF32:$dst),
- (ins GPRF32:$src0, i32imm:$src1),
- "STORE_OUTPUT $dst, $src0, $src1",
- [(set GPRF32:$dst, (int_AMDGPU_store_output GPRF32:$src0, imm:$src1))]
- >;
}
/* Generic helper patterns for intrinsics */
diff --git a/src/gallium/drivers/radeon/R600ISelLowering.cpp b/src/gallium/drivers/radeon/R600ISelLowering.cpp
index d35669e1174..9870b7ba820 100644
--- a/src/gallium/drivers/radeon/R600ISelLowering.cpp
+++ b/src/gallium/drivers/radeon/R600ISelLowering.cpp
@@ -96,6 +96,22 @@ MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter(
MI->eraseFromParent();
break;
}
+ case AMDIL::STORE_OUTPUT:
+ {
+ MachineBasicBlock::iterator I = *MI;
+ int64_t OutputIndex = MI->getOperand(2).getImm();
+ unsigned OutputReg = AMDIL::R600_TReg32RegClass.getRegister(OutputIndex);
+
+ BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDIL::COPY), OutputReg)
+ .addOperand(MI->getOperand(1));
+
+ MRI.replaceRegWith(MI->getOperand(0).getReg(), OutputReg);
+ if (!MRI.isLiveOut(OutputReg)) {
+ MRI.addLiveOut(OutputReg);
+ }
+ MI->eraseFromParent();
+ break;
+ }
}
return BB;
}
diff --git a/src/gallium/drivers/radeon/R600Instructions.td b/src/gallium/drivers/radeon/R600Instructions.td
index b462a05ea24..99e4b4fd0b8 100644
--- a/src/gallium/drivers/radeon/R600Instructions.td
+++ b/src/gallium/drivers/radeon/R600Instructions.td
@@ -998,6 +998,13 @@ def LOAD_INPUT : AMDGPUShaderInst <
[(set R600_Reg32:$dst, (int_R600_load_input imm:$src))]
>;
+def STORE_OUTPUT: AMDGPUShaderInst <
+ (outs R600_Reg32:$dst),
+ (ins R600_Reg32:$src0, i32imm:$src1),
+ "STORE_OUTPUT $dst, $src0, $src1",
+ [(set R600_Reg32:$dst, (int_AMDGPU_store_output R600_Reg32:$src0, imm:$src1))]
+>;
+
} // End usesCustomInserter = 1, isPseudo = 1
} // End isCodeGenOnly = 1
diff --git a/src/gallium/drivers/radeon/R600LowerShaderInstructions.cpp b/src/gallium/drivers/radeon/R600LowerShaderInstructions.cpp
index 58b1f0824d7..f3dd65b47e7 100644
--- a/src/gallium/drivers/radeon/R600LowerShaderInstructions.cpp
+++ b/src/gallium/drivers/radeon/R600LowerShaderInstructions.cpp
@@ -31,8 +31,6 @@ namespace {
void lowerEXPORT_REG_FAKE(MachineInstr &MI, MachineBasicBlock &MBB,
MachineBasicBlock::iterator I);
- bool lowerSTORE_OUTPUT(MachineInstr & MI, MachineBasicBlock &MBB,
- MachineBasicBlock::iterator I);
public:
R600LowerShaderInstructionsPass(TargetMachine &tm) :
@@ -79,10 +77,6 @@ bool R600LowerShaderInstructionsPass::runOnMachineFunction(MachineFunction &MF)
deleteInstr = true;
break;
- case AMDIL::STORE_OUTPUT:
- deleteInstr = lowerSTORE_OUTPUT(MI, MBB, I);
- break;
-
}
++I;
@@ -95,24 +89,3 @@ bool R600LowerShaderInstructionsPass::runOnMachineFunction(MachineFunction &MF)
return false;
}
-
-bool R600LowerShaderInstructionsPass::lowerSTORE_OUTPUT(MachineInstr &MI,
- MachineBasicBlock &MBB, MachineBasicBlock::iterator I)
-{
- MachineOperand &valueOp = MI.getOperand(1);
- MachineOperand &indexOp = MI.getOperand(2);
- unsigned valueReg = valueOp.getReg();
- int64_t outputIndex = indexOp.getImm();
- const TargetRegisterClass * outputClass = TM.getRegisterInfo()->getRegClass(AMDIL::R600_TReg32RegClassID);
- unsigned newRegister = outputClass->getRegister(outputIndex);
-
- BuildMI(MBB, I, MBB.findDebugLoc(I), TM.getInstrInfo()->get(AMDIL::COPY),
- newRegister)
- .addReg(valueReg);
-
- if (!MRI->isLiveOut(newRegister))
- MRI->addLiveOut(newRegister);
-
- return true;
-
-}