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-rw-r--r--src/gallium/auxiliary/gallivm/lp_bld_init.c10
-rw-r--r--src/gallium/auxiliary/util/u_cpu_detect.c5
-rw-r--r--src/gallium/auxiliary/util/u_cpu_detect.h1
3 files changed, 15 insertions, 1 deletions
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_init.c b/src/gallium/auxiliary/gallivm/lp_bld_init.c
index 068a2cd7915..ffbe3eaed2c 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_init.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_init.c
@@ -434,8 +434,16 @@ lp_build_init(void)
util_cpu_detect();
+ /* AMD Bulldozer AVX's throughput is the same as SSE2; and because using
+ * 8-wide vector needs more floating ops than 4-wide (due to padding), it is
+ * actually more efficient to use 4-wide vectors on this processor.
+ *
+ * See also:
+ * - http://www.anandtech.com/show/4955/the-bulldozer-review-amd-fx8150-tested/2
+ */
if (HAVE_AVX &&
- util_cpu_caps.has_avx) {
+ util_cpu_caps.has_avx &&
+ util_cpu_caps.has_intel) {
lp_native_vector_width = 256;
} else {
/* Leave it at 128, even when no SIMD extensions are available.
diff --git a/src/gallium/auxiliary/util/u_cpu_detect.c b/src/gallium/auxiliary/util/u_cpu_detect.c
index 945f0b0a910..d7f0be40e3d 100644
--- a/src/gallium/auxiliary/util/u_cpu_detect.c
+++ b/src/gallium/auxiliary/util/u_cpu_detect.c
@@ -286,6 +286,11 @@ util_cpu_detect(void)
util_cpu_caps.cacheline = cacheline;
}
+ if (regs[1] == 0x756e6547 && regs[2] == 0x6c65746e && regs[3] == 0x49656e69) {
+ /* GenuineIntel */
+ util_cpu_caps.has_intel = 1;
+ }
+
cpuid(0x80000000, regs);
if (regs[0] >= 0x80000001) {
diff --git a/src/gallium/auxiliary/util/u_cpu_detect.h b/src/gallium/auxiliary/util/u_cpu_detect.h
index b44d9d9a0fe..acac6865849 100644
--- a/src/gallium/auxiliary/util/u_cpu_detect.h
+++ b/src/gallium/auxiliary/util/u_cpu_detect.h
@@ -52,6 +52,7 @@ struct util_cpu_caps {
int x86_cpu_type;
unsigned cacheline;
+ unsigned has_intel:1;
unsigned has_tsc:1;
unsigned has_mmx:1;
unsigned has_mmx2:1;
93 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419
#include "draw/draw_context.h"
#include "pipe/p_defines.h"
#include "pipe/p_winsys.h"

#include "nv20_context.h"
#include "nv20_screen.h"

static void
nv20_flush(struct pipe_context *pipe, unsigned flags,
	   struct pipe_fence_handle **fence)
{
	struct nv20_context *nv20 = nv20_context(pipe);

	draw_flush(nv20->draw);

	FIRE_RING(fence);
}

static void
nv20_destroy(struct pipe_context *pipe)
{
	struct nv20_context *nv20 = nv20_context(pipe);

	if (nv20->draw)
		draw_destroy(nv20->draw);

	FREE(nv20);
}

static void nv20_init_hwctx(struct nv20_context *nv20)
{
	struct nv20_screen *screen = nv20->screen;
	struct nouveau_winsys *nvws = screen->nvws;
	int i;
	float projectionmatrix[16];
	const boolean is_nv25tcl = (nv20->screen->kelvin->grclass == NV25TCL);

	BEGIN_RING(kelvin, NV20TCL_DMA_NOTIFY, 1);
	OUT_RING  (screen->sync->handle);
	BEGIN_RING(kelvin, NV20TCL_DMA_TEXTURE0, 2);
	OUT_RING  (nvws->channel->vram->handle);
	OUT_RING  (nvws->channel->gart->handle); /* TEXTURE1 */
	BEGIN_RING(kelvin, NV20TCL_DMA_COLOR, 2);
	OUT_RING  (nvws->channel->vram->handle);
	OUT_RING  (nvws->channel->vram->handle); /* ZETA */

	BEGIN_RING(kelvin, NV20TCL_DMA_QUERY, 1);
	OUT_RING  (0); /* renouveau: beef0351, unique */

	BEGIN_RING(kelvin, NV20TCL_RT_HORIZ, 2);
	OUT_RING  (0);
	OUT_RING  (0);

	BEGIN_RING(kelvin, NV20TCL_VIEWPORT_CLIP_HORIZ(0), 1);
	OUT_RING  ((0xfff << 16) | 0x0);
	BEGIN_RING(kelvin, NV20TCL_VIEWPORT_CLIP_VERT(0), 1);
	OUT_RING  ((0xfff << 16) | 0x0);

	for (i = 1; i < NV20TCL_VIEWPORT_CLIP_HORIZ__SIZE; i++) {
		BEGIN_RING(kelvin, NV20TCL_VIEWPORT_CLIP_HORIZ(i), 1);
		OUT_RING  (0);
		BEGIN_RING(kelvin, NV20TCL_VIEWPORT_CLIP_VERT(i), 1);
		OUT_RING  (0);
	}

	BEGIN_RING(kelvin, NV20TCL_VIEWPORT_CLIP_MODE, 1);
	OUT_RING  (0);

	BEGIN_RING(kelvin, 0x17e0, 3);
	OUT_RINGf (0.0);
	OUT_RINGf (0.0);
	OUT_RINGf (1.0);

	if (is_nv25tcl) {
		BEGIN_RING(kelvin, NV20TCL_TX_RCOMP, 1);
		OUT_RING  (NV20TCL_TX_RCOMP_LEQUAL | 0xdb0);
	} else {
		BEGIN_RING(kelvin, 0x1e68, 1);
		OUT_RING  (0x4b800000); /* 16777216.000000 */
		BEGIN_RING(kelvin, NV20TCL_TX_RCOMP, 1);
		OUT_RING  (NV20TCL_TX_RCOMP_LEQUAL);
	}

	BEGIN_RING(kelvin, 0x290, 1);
	OUT_RING  ((0x10 << 16) | 1);
	BEGIN_RING(kelvin, 0x9fc, 1);
	OUT_RING  (0);
	BEGIN_RING(kelvin, 0x1d80, 1);
	OUT_RING  (1);
	BEGIN_RING(kelvin, 0x9f8, 1);
	OUT_RING  (4);
	BEGIN_RING(kelvin, 0x17ec, 3);
	OUT_RINGf (0.0);
	OUT_RINGf (1.0);
	OUT_RINGf (0.0);

	if (is_nv25tcl) {
		BEGIN_RING(kelvin, 0x1d88, 1);
		OUT_RING  (3);

		BEGIN_RING(kelvin, NV25TCL_DMA_IN_MEMORY9, 1);
		OUT_RING  (nvws->channel->vram->handle);
		BEGIN_RING(kelvin, NV25TCL_DMA_IN_MEMORY8, 1);
		OUT_RING  (nvws->channel->vram->handle);
	}
	BEGIN_RING(kelvin, NV20TCL_DMA_FENCE, 1);
	OUT_RING  (0);	/* renouveau: beef1e10 */

	BEGIN_RING(kelvin, 0x1e98, 1);
	OUT_RING  (0);
#if 0
	if (is_nv25tcl) {
		BEGIN_RING(NvSub3D, NV25TCL_DMA_IN_MEMORY4, 2);
		OUT_RING  (NvDmaTT);	/* renouveau: beef0202 */
		OUT_RING  (NvDmaFB);	/* renouveau: beef0201 */

		BEGIN_RING(NvSub3D, NV20TCL_DMA_TEXTURE1, 1);
		OUT_RING  (NvDmaTT);	/* renouveau: beef0202 */
	}
#endif
	BEGIN_RING(kelvin, NV20TCL_NOTIFY, 1);
	OUT_RING  (0);

	BEGIN_RING(kelvin, 0x120, 3);
	OUT_RING  (0);
	OUT_RING  (1);
	OUT_RING  (2);

/* error: ILLEGAL_MTHD, PROTECTION_FAULT
	BEGIN_RING(kelvin, NV20TCL_VIEWPORT_TRANSLATE_X, 4);
	OUT_RINGf (0.0);
	OUT_RINGf (512.0);
	OUT_RINGf (0.0);
	OUT_RINGf (0.0);
*/

	if (is_nv25tcl) {
		BEGIN_RING(kelvin, 0x022c, 2);
		OUT_RING  (0x280);
		OUT_RING  (0x07d28000);
	}

/* * illegal method, protection fault
	BEGIN_RING(NvSub3D, 0x1c2c, 1);
	OUT_RING  (0); */

	if (is_nv25tcl) {
		BEGIN_RING(kelvin, 0x1da4, 1);
		OUT_RING  (0);
	}

/* * crashes with illegal method, protection fault
	BEGIN_RING(NvSub3D, 0x1c18, 1);
	OUT_RING  (0x200); */

	BEGIN_RING(kelvin, NV20TCL_RT_HORIZ, 2);
	OUT_RING  ((0 << 16) | 0);
	OUT_RING  ((0 << 16) | 0);

	/* *** Set state *** */

	BEGIN_RING(kelvin, NV20TCL_ALPHA_FUNC_ENABLE, 1);
	OUT_RING  (0);
	BEGIN_RING(kelvin, NV20TCL_ALPHA_FUNC_FUNC, 2);
	OUT_RING  (NV20TCL_ALPHA_FUNC_FUNC_ALWAYS);
	OUT_RING  (0);			/* NV20TCL_ALPHA_FUNC_REF */

	for (i = 0; i < NV20TCL_TX_ENABLE__SIZE; ++i) {
		BEGIN_RING(kelvin, NV20TCL_TX_ENABLE(i), 1);
		OUT_RING  (0);
	}
	BEGIN_RING(kelvin, NV20TCL_TX_SHADER_OP, 1);
	OUT_RING  (0);
	BEGIN_RING(kelvin, NV20TCL_TX_SHADER_CULL_MODE, 1);
	OUT_RING  (0);
	BEGIN_RING(kelvin, NV20TCL_RC_IN_ALPHA(0), 4);
	OUT_RING  (0x30d410d0);
	OUT_RING  (0);
	OUT_RING  (0);
	OUT_RING  (0);
	BEGIN_RING(kelvin, NV20TCL_RC_OUT_RGB(0), 4);
	OUT_RING  (0x00000c00);
	OUT_RING  (0);
	OUT_RING  (0);
	OUT_RING  (0);
	BEGIN_RING(kelvin, NV20TCL_RC_ENABLE, 1);
	OUT_RING  (0x00011101);
	BEGIN_RING(kelvin, NV20TCL_RC_FINAL0, 2);
	OUT_RING  (0x130e0300);
	OUT_RING  (0x0c091c80);
	BEGIN_RING(kelvin, NV20TCL_RC_OUT_ALPHA(0), 4);
	OUT_RING  (0x00000c00);
	OUT_RING  (0);
	OUT_RING  (0);
	OUT_RING  (0);
	BEGIN_RING(kelvin, NV20TCL_RC_IN_RGB(0), 4);
	OUT_RING  (0x20c400c0);
	OUT_RING  (0);
	OUT_RING  (0);
	OUT_RING  (0);
	BEGIN_RING(kelvin, NV20TCL_RC_COLOR0, 2);
	OUT_RING  (0);
	OUT_RING  (0);
	BEGIN_RING(kelvin, NV20TCL_RC_CONSTANT_COLOR0(0), 4);
	OUT_RING  (0x035125a0);
	OUT_RING  (0);
	OUT_RING  (0x40002000);
	OUT_RING  (0);
	BEGIN_RING(kelvin, NV20TCL_MULTISAMPLE_CONTROL, 1);
	OUT_RING  (0xffff0000);

	BEGIN_RING(kelvin, NV20TCL_BLEND_FUNC_ENABLE, 1);
	OUT_RING  (0);
	BEGIN_RING(kelvin, NV20TCL_DITHER_ENABLE, 1);
	OUT_RING  (0);
	BEGIN_RING(kelvin, NV20TCL_STENCIL_ENABLE, 1);
	OUT_RING  (0);
	BEGIN_RING(kelvin, NV20TCL_BLEND_FUNC_SRC, 4);
	OUT_RING  (NV20TCL_BLEND_FUNC_SRC_ONE);
	OUT_RING  (NV20TCL_BLEND_FUNC_DST_ZERO);
	OUT_RING  (0);			/* NV20TCL_BLEND_COLOR */
	OUT_RING  (NV20TCL_BLEND_EQUATION_FUNC_ADD);
	BEGIN_RING(kelvin, NV20TCL_STENCIL_MASK, 7);
	OUT_RING  (0xff);
	OUT_RING  (NV20TCL_STENCIL_FUNC_FUNC_ALWAYS);
	OUT_RING  (0);			/* NV20TCL_STENCIL_FUNC_REF */
	OUT_RING  (0xff);		/* NV20TCL_STENCIL_FUNC_MASK */
	OUT_RING  (NV20TCL_STENCIL_OP_FAIL_KEEP);
	OUT_RING  (NV20TCL_STENCIL_OP_ZFAIL_KEEP);
	OUT_RING  (NV20TCL_STENCIL_OP_ZPASS_KEEP);

	BEGIN_RING(kelvin, NV20TCL_COLOR_LOGIC_OP_ENABLE, 2);
	OUT_RING  (0);
	OUT_RING  (NV20TCL_COLOR_LOGIC_OP_OP_COPY);
	BEGIN_RING(kelvin, 0x17cc, 1);
	OUT_RING  (0);
	if (is_nv25tcl) {
		BEGIN_RING(kelvin, 0x1d84, 1);
		OUT_RING  (1);
	}
	BEGIN_RING(kelvin, NV20TCL_LIGHTING_ENABLE, 1);
	OUT_RING  (0);
	BEGIN_RING(kelvin, NV20TCL_LIGHT_CONTROL, 1);
	OUT_RING  (0x00020000);
	BEGIN_RING(kelvin, NV20TCL_SEPARATE_SPECULAR_ENABLE, 1);
	OUT_RING  (0);
	BEGIN_RING(kelvin, NV20TCL_LIGHT_MODEL_TWO_SIDE_ENABLE, 1);
	OUT_RING  (0);
	BEGIN_RING(kelvin, NV20TCL_ENABLED_LIGHTS, 1);
	OUT_RING  (0);
	BEGIN_RING(kelvin, NV20TCL_NORMALIZE_ENABLE, 1);
	OUT_RING  (0);
	BEGIN_RING(kelvin, NV20TCL_POLYGON_STIPPLE_PATTERN(0),
					NV20TCL_POLYGON_STIPPLE_PATTERN__SIZE);
	for (i = 0; i < NV20TCL_POLYGON_STIPPLE_PATTERN__SIZE; ++i) {
		OUT_RING(0xffffffff);
	}

	BEGIN_RING(kelvin, NV20TCL_POLYGON_OFFSET_POINT_ENABLE, 3);
	OUT_RING  (0);
	OUT_RING  (0);		/* NV20TCL.POLYGON_OFFSET_LINE_ENABLE */
	OUT_RING  (0);		/* NV20TCL.POLYGON_OFFSET_FILL_ENABLE */
	BEGIN_RING(kelvin, NV20TCL_DEPTH_FUNC, 1);
	OUT_RING  (NV20TCL_DEPTH_FUNC_LESS);
	BEGIN_RING(kelvin, NV20TCL_DEPTH_WRITE_ENABLE, 1);
	OUT_RING  (1);
	BEGIN_RING(kelvin, NV20TCL_DEPTH_TEST_ENABLE, 1);
	OUT_RING  (0);
	BEGIN_RING(kelvin, NV20TCL_POLYGON_OFFSET_FACTOR, 2);
	OUT_RINGf (0.0);
	OUT_RINGf (0.0);	/* NV20TCL.POLYGON_OFFSET_UNITS */
	BEGIN_RING(kelvin, NV20TCL_DEPTH_UNK17D8, 1);
	OUT_RING  (1);
	if (!is_nv25tcl) {
		BEGIN_RING(kelvin, 0x1d84, 1);
		OUT_RING  (3);
	}
	BEGIN_RING(kelvin, NV20TCL_POINT_SIZE, 1);
	if (!is_nv25tcl) {
		OUT_RING  (8);
	} else {
		OUT_RINGf (1.0);
	}
	if (!is_nv25tcl) {
		BEGIN_RING(kelvin, NV20TCL_POINT_PARAMETERS_ENABLE, 2);
		OUT_RING  (0);
		OUT_RING  (0);		/* NV20TCL.POINT_SMOOTH_ENABLE */
	} else {
		BEGIN_RING(kelvin, NV20TCL_POINT_PARAMETERS_ENABLE, 1);
		OUT_RING  (0);
		BEGIN_RING(kelvin, 0x0a1c, 1);
		OUT_RING  (0x800);
	}
	BEGIN_RING(kelvin, NV20TCL_LINE_WIDTH, 1);
	OUT_RING  (8);
	BEGIN_RING(kelvin, NV20TCL_LINE_SMOOTH_ENABLE, 1);
	OUT_RING  (0);
	BEGIN_RING(kelvin, NV20TCL_POLYGON_MODE_FRONT, 2);
	OUT_RING  (NV20TCL_POLYGON_MODE_FRONT_FILL);
	OUT_RING  (NV20TCL_POLYGON_MODE_BACK_FILL);
	BEGIN_RING(kelvin, NV20TCL_CULL_FACE, 2);
	OUT_RING  (NV20TCL_CULL_FACE_BACK);
	OUT_RING  (NV20TCL_FRONT_FACE_CCW);
	BEGIN_RING(kelvin, NV20TCL_POLYGON_SMOOTH_ENABLE, 1);
	OUT_RING  (0);
	BEGIN_RING(kelvin, NV20TCL_CULL_FACE_ENABLE, 1);
	OUT_RING  (0);
	BEGIN_RING(kelvin, NV20TCL_SHADE_MODEL, 1);
	OUT_RING  (NV20TCL_SHADE_MODEL_SMOOTH);
	BEGIN_RING(kelvin, NV20TCL_POLYGON_STIPPLE_ENABLE, 1);
	OUT_RING  (0);
	BEGIN_RING(kelvin, NV20TCL_TX_GEN_S(0), 4 * NV20TCL_TX_GEN_S__SIZE);
	for (i=0; i < 4 * NV20TCL_TX_GEN_S__SIZE; ++i) {
		OUT_RING(0);
	}
	BEGIN_RING(kelvin, NV20TCL_FOG_EQUATION_CONSTANT, 3);
	OUT_RINGf (1.5);
	OUT_RINGf (-0.090168);		/* NV20TCL.FOG_EQUATION_LINEAR */
	OUT_RINGf (0.0);		/* NV20TCL.FOG_EQUATION_QUADRATIC */
	BEGIN_RING(kelvin, NV20TCL_FOG_MODE, 2);
	OUT_RING  (NV20TCL_FOG_MODE_EXP_2);
	OUT_RING  (NV20TCL_FOG_COORD_DIST_COORD_FOG);
	BEGIN_RING(kelvin, NV20TCL_FOG_ENABLE, 2);
	OUT_RING  (0);
	OUT_RING  (0);			/* NV20TCL.FOG_COLOR */
	BEGIN_RING(kelvin, NV20TCL_ENGINE, 1);
	OUT_RING  (NV20TCL_ENGINE_FIXED);

	for (i = 0; i < NV20TCL_TX_MATRIX_ENABLE__SIZE; ++i) {
		BEGIN_RING(kelvin, NV20TCL_TX_MATRIX_ENABLE(i), 1);
		OUT_RING  (0);
	}

	BEGIN_RING(kelvin, NV20TCL_VTX_ATTR_4F_X(1), 4 * 15);
	OUT_RINGf(1.0); OUT_RINGf(0.0); OUT_RINGf(0.0); OUT_RINGf(1.0);
	OUT_RINGf(0.0); OUT_RINGf(0.0); OUT_RINGf(1.0); OUT_RINGf(1.0);
	OUT_RINGf(1.0); OUT_RINGf(1.0); OUT_RINGf(1.0); OUT_RINGf(1.0);
	for (i = 4; i < 16; ++i) {
		OUT_RINGf(0.0); OUT_RINGf(0.0); OUT_RINGf(0.0);	OUT_RINGf(1.0);
	}

	BEGIN_RING(kelvin, NV20TCL_EDGEFLAG_ENABLE, 1);
	OUT_RING  (1);
	BEGIN_RING(kelvin, NV20TCL_COLOR_MASK, 1);
	OUT_RING (0x00010101);
	BEGIN_RING(kelvin, NV20TCL_CLEAR_VALUE, 1);
	OUT_RING (0);

	memset(projectionmatrix, 0, sizeof(projectionmatrix));
	projectionmatrix[0*4+0] = 1.0;
	projectionmatrix[1*4+1] = 1.0;
	projectionmatrix[2*4+2] = 1.0;
	projectionmatrix[3*4+3] = 1.0;
	BEGIN_RING(kelvin, NV20TCL_PROJECTION_MATRIX(0), 16);
	for (i = 0; i < 16; i++) {
		OUT_RINGf  (projectionmatrix[i]);
	}

	BEGIN_RING(kelvin, NV20TCL_DEPTH_RANGE_NEAR, 2);
	OUT_RINGf  (0.0);
	OUT_RINGf  (16777216.0); /* bpp dependant? */

	BEGIN_RING(kelvin, NV20TCL_VIEWPORT_SCALE0_X, 4);
	OUT_RINGf  (-2048.0);
	OUT_RINGf  (-2048.0);
	OUT_RINGf  (16777215.0 * 0.5);
	OUT_RING  (0);

	BEGIN_RING(kelvin, NV20TCL_VIEWPORT_SCALE1_X, 4);
	OUT_RINGf  (-2048.0);
	OUT_RINGf  (-2048.0);
	OUT_RINGf  (16777215.0 * 0.5);
	OUT_RING  (0);

	FIRE_RING (NULL);
}

static void
nv20_set_edgeflags(struct pipe_context *pipe, const unsigned *bitfield)
{
}

struct pipe_context *
nv20_create(struct pipe_screen *pscreen, unsigned pctx_id)
{
	struct nv20_screen *screen = nv20_screen(pscreen);
	struct pipe_winsys *ws = pscreen->winsys;
	struct nv20_context *nv20;
	struct nouveau_winsys *nvws = screen->nvws;

	nv20 = CALLOC(1, sizeof(struct nv20_context));
	if (!nv20)
		return NULL;
	nv20->screen = screen;
	nv20->pctx_id = pctx_id;

	nv20->nvws = nvws;

	nv20->pipe.winsys = ws;
	nv20->pipe.screen = pscreen;
	nv20->pipe.destroy = nv20_destroy;
	nv20->pipe.set_edgeflags = nv20_set_edgeflags;
	nv20->pipe.draw_arrays = nv20_draw_arrays;
	nv20->pipe.draw_elements = nv20_draw_elements;
	nv20->pipe.clear = nv20_clear;
	nv20->pipe.flush = nv20_flush;

	nv20_init_surface_functions(nv20);
	nv20_init_state_functions(nv20);

	nv20->draw = draw_create();
	assert(nv20->draw);
	draw_set_rasterize_stage(nv20->draw, nv20_draw_vbuf_stage(nv20));

	nv20_init_hwctx(nv20);

	return &nv20->pipe;
}