diff options
| -rw-r--r-- | src/amd/vulkan/radv_image.c | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c index a1b660a74cd..d57df536d15 100644 --- a/src/amd/vulkan/radv_image.c +++ b/src/amd/vulkan/radv_image.c @@ -240,7 +240,7 @@ si_set_mutable_tex_desc_fields(struct radv_device *device, const struct legacy_surf_level *base_level_info, unsigned base_level, unsigned first_level, unsigned block_width, bool is_stencil, - uint32_t *state) + bool is_storage_image, uint32_t *state) { uint64_t gpu_address = image->bo ? radv_buffer_get_va(image->bo) + image->offset : 0; uint64_t va = gpu_address; @@ -264,11 +264,12 @@ si_set_mutable_tex_desc_fields(struct radv_device *device, if (chip_class >= VI) { state[6] &= C_008F28_COMPRESSION_EN; state[7] = 0; - if (radv_vi_dcc_enabled(image, first_level)) { + if (!is_storage_image && radv_vi_dcc_enabled(image, first_level)) { meta_va = gpu_address + image->dcc_offset; if (chip_class <= VI) meta_va += base_level_info->dcc_offset; - } else if(image->tc_compatible_htile && image->surface.htile_size) { + } else if(!is_storage_image && image->tc_compatible_htile && + image->surface.htile_size) { meta_va = gpu_address + image->htile_offset; } @@ -600,7 +601,7 @@ radv_query_opaque_metadata(struct radv_device *device, desc, NULL); si_set_mutable_tex_desc_fields(device, image, &image->surface.u.legacy.level[0], 0, 0, - image->surface.blk_w, false, desc); + image->surface.blk_w, false, false, desc); /* Clear the base address and set the relative DCC offset. */ desc[0] = 0; @@ -1013,7 +1014,7 @@ radv_image_view_make_descriptor(struct radv_image_view *iview, base_level_info, iview->base_mip, iview->base_mip, - blk_w, is_stencil, descriptor); + blk_w, is_stencil, is_storage_image, descriptor); } void |