diff options
| -rw-r--r-- | src/amd/addrlib/gfx9/gfx9addrlib.cpp | 57 | ||||
| -rw-r--r-- | src/amd/addrlib/gfx9/gfx9addrlib.h | 8 | ||||
| -rw-r--r-- | src/amd/common/amdgpu_id.h | 10 |
3 files changed, 72 insertions, 3 deletions
diff --git a/src/amd/addrlib/gfx9/gfx9addrlib.cpp b/src/amd/addrlib/gfx9/gfx9addrlib.cpp index 96b05de3dfe..9b2537151ac 100644 --- a/src/amd/addrlib/gfx9/gfx9addrlib.cpp +++ b/src/amd/addrlib/gfx9/gfx9addrlib.cpp @@ -1193,6 +1193,20 @@ ChipFamily Gfx9Lib::HwlConvertChipFamily( m_settings.depthPipeXorDisable = 1; break; + case FAMILY_RV: + m_settings.isArcticIsland = 1; + m_settings.isRaven = ASICREV_IS_RAVEN(uChipRevision); + + if (m_settings.isRaven) + { + m_settings.isDcn1 = 1; + } + + m_settings.metaBaseAlignFix = 1; + + m_settings.depthPipeXorDisable = 1; + break; + default: ADDR_ASSERT(!"This should be a Fusion"); break; @@ -2734,6 +2748,35 @@ BOOL_32 Gfx9Lib::IsValidDisplaySwizzleMode( break; } } + else if (m_settings.isDcn1) + { + switch (swizzleMode) + { + case ADDR_SW_4KB_D: + case ADDR_SW_64KB_D: + case ADDR_SW_VAR_D: + case ADDR_SW_64KB_D_T: + case ADDR_SW_4KB_D_X: + case ADDR_SW_64KB_D_X: + case ADDR_SW_VAR_D_X: + support = (pIn->bpp == 64); + break; + + case ADDR_SW_LINEAR: + case ADDR_SW_4KB_S: + case ADDR_SW_64KB_S: + case ADDR_SW_VAR_S: + case ADDR_SW_64KB_S_T: + case ADDR_SW_4KB_S_X: + case ADDR_SW_64KB_S_X: + case ADDR_SW_VAR_S_X: + support = (pIn->bpp <= 64); + break; + + default: + break; + } + } else { ADDR_NOT_IMPLEMENTED(); @@ -3195,6 +3238,20 @@ ADDR_E_RETURNCODE Gfx9Lib::HwlGetPreferredSurfaceSetting( // DCE12 does not support display surface to be _T swizzle mode prtXor = FALSE; } + else if (m_settings.isDcn1) + { + // _R is not supported by Dcn1 + if (pIn->bpp == 64) + { + swType = ADDR_SW_D; + } + else + { + swType = ADDR_SW_S; + } + + blockSet.micro = FALSE; + } else { ADDR_NOT_IMPLEMENTED(); diff --git a/src/amd/addrlib/gfx9/gfx9addrlib.h b/src/amd/addrlib/gfx9/gfx9addrlib.h index 73d51f1ef7a..96236103d04 100644 --- a/src/amd/addrlib/gfx9/gfx9addrlib.h +++ b/src/amd/addrlib/gfx9/gfx9addrlib.h @@ -54,11 +54,13 @@ struct Gfx9ChipSettings // Asic/Generation name UINT_32 isArcticIsland : 1; UINT_32 isVega10 : 1; - UINT_32 reserved0 : 30; + UINT_32 isRaven : 1; + UINT_32 reserved0 : 29; // Display engine IP version name UINT_32 isDce12 : 1; - UINT_32 reserved1 : 31; + UINT_32 isDcn1 : 1; + UINT_32 reserved1 : 29; // Misc configuration bits UINT_32 metaBaseAlignFix : 1; @@ -201,7 +203,7 @@ protected: if (IsXor(swizzleMode)) { - if (m_settings.isVega10) + if (m_settings.isVega10 || m_settings.isRaven) { baseAlign = GetBlockSize(swizzleMode); } diff --git a/src/amd/common/amdgpu_id.h b/src/amd/common/amdgpu_id.h index 316b30ffa38..6f254f0740f 100644 --- a/src/amd/common/amdgpu_id.h +++ b/src/amd/common/amdgpu_id.h @@ -49,6 +49,7 @@ enum { FAMILY_CZ, FAMILY_PI, FAMILY_AI, + FAMILY_RV, FAMILY_LAST, }; @@ -185,4 +186,13 @@ enum { #define ASICREV_IS_VEGA10_P(eChipRev) \ ((eChipRev) >= AI_VEGA10_P_A0 && (eChipRev) < AI_UNKNOWN) +/* RV specific rev IDs */ +enum { + RAVEN_A0 = 0x01, + RAVEN_UNKNOWN = 0xFF +}; + +#define ASICREV_IS_RAVEN(eChipRev) \ + ((eChipRev) >= RAVEN_A0 && (eChipRev) < RAVEN_UNKNOWN) + #endif /* AMDGPU_ID_H */ |