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-rw-r--r--src/mesa/drivers/dri/i965/brw_conditional_render.c6
-rw-r--r--src/mesa/drivers/dri/i965/brw_queryobj.c19
2 files changed, 11 insertions, 14 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_conditional_render.c b/src/mesa/drivers/dri/i965/brw_conditional_render.c
index 6d37c3b6928..122a4ecc0f6 100644
--- a/src/mesa/drivers/dri/i965/brw_conditional_render.c
+++ b/src/mesa/drivers/dri/i965/brw_conditional_render.c
@@ -56,6 +56,12 @@ set_predicate_for_result(struct brw_context *brw,
assert(query->bo != NULL);
+ /* Needed to ensure the memory is coherent for the MI_LOAD_REGISTER_MEM
+ * command when loading the values into the predicate source registers for
+ * conditional rendering.
+ */
+ brw_emit_pipe_control_flush(brw, PIPE_CONTROL_FLUSH_ENABLE);
+
brw_load_register_mem64(brw,
MI_PREDICATE_SRC0,
query->bo,
diff --git a/src/mesa/drivers/dri/i965/brw_queryobj.c b/src/mesa/drivers/dri/i965/brw_queryobj.c
index d6b012c392e..a8e5ababba4 100644
--- a/src/mesa/drivers/dri/i965/brw_queryobj.c
+++ b/src/mesa/drivers/dri/i965/brw_queryobj.c
@@ -66,20 +66,11 @@ brw_write_timestamp(struct brw_context *brw, drm_intel_bo *query_bo, int idx)
void
brw_write_depth_count(struct brw_context *brw, drm_intel_bo *query_bo, int idx)
{
- uint32_t flags;
-
- flags = (PIPE_CONTROL_WRITE_DEPTH_COUNT |
- PIPE_CONTROL_DEPTH_STALL);
-
- /* Needed to ensure the memory is coherent for the MI_LOAD_REGISTER_MEM
- * command when loading the values into the predicate source registers for
- * conditional rendering.
- */
- if (brw->predicate.supported)
- flags |= PIPE_CONTROL_FLUSH_ENABLE;
-
- brw_emit_pipe_control_write(brw, flags, query_bo,
- idx * sizeof(uint64_t), 0, 0);
+ brw_emit_pipe_control_write(brw,
+ PIPE_CONTROL_WRITE_DEPTH_COUNT |
+ PIPE_CONTROL_DEPTH_STALL,
+ query_bo, idx * sizeof(uint64_t),
+ 0, 0);
}
/**