diff options
| -rw-r--r-- | src/gallium/drivers/nouveau/nv50/nv50_query.c | 14 | ||||
| -rw-r--r-- | src/gallium/drivers/nouveau/nvc0/nvc0_query.c | 14 |
2 files changed, 12 insertions, 16 deletions
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_query.c b/src/gallium/drivers/nouveau/nv50/nv50_query.c index 9a1397a9860..e57e3ac8c3b 100644 --- a/src/gallium/drivers/nouveau/nv50/nv50_query.c +++ b/src/gallium/drivers/nouveau/nv50/nv50_query.c @@ -208,13 +208,11 @@ nv50_screen_get_driver_query_group_info(struct pipe_screen *pscreen, if (screen->base.class_3d >= NV84_3D_CLASS) { info->name = "MP counters"; - /* Because we can't expose the number of hardware counters needed - * for each different query, we don't want to allow more than one - * active query simultaneously to avoid failure when the maximum - * number of counters is reached. Note that these groups of GPU - * counters are currently only used by AMD_performance_monitor. - */ - info->max_active_queries = 1; + /* Expose the maximum number of hardware counters available, + * although some queries use more than one counter. Expect failures + * in that case but as performance counters are for developers, + * this should not have a real impact. */ + info->max_active_queries = 4; info->num_queries = NV50_HW_SM_QUERY_COUNT; return 1; } @@ -224,7 +222,7 @@ nv50_screen_get_driver_query_group_info(struct pipe_screen *pscreen, if (screen->compute) { if (screen->base.class_3d >= NV84_3D_CLASS) { info->name = "Performance metrics"; - info->max_active_queries = 1; + info->max_active_queries = 2; /* A metric uses at least 2 queries */ info->num_queries = NV50_HW_METRIC_QUERY_COUNT; return 1; } diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_query.c b/src/gallium/drivers/nouveau/nvc0/nvc0_query.c index 91fb72f90b5..8b9e6b69d3e 100644 --- a/src/gallium/drivers/nouveau/nvc0/nvc0_query.c +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_query.c @@ -218,13 +218,11 @@ nvc0_screen_get_driver_query_group_info(struct pipe_screen *pscreen, if (screen->compute) { info->name = "MP counters"; - /* Because we can't expose the number of hardware counters needed for - * each different query, we don't want to allow more than one active - * query simultaneously to avoid failure when the maximum number of - * counters is reached. Note that these groups of GPU counters are - * currently only used by AMD_performance_monitor. - */ - info->max_active_queries = 1; + /* Expose the maximum number of hardware counters available, although + * some queries use more than one counter. Expect failures in that + * case but as performance counters are for developers, this should + * not have a real impact. */ + info->max_active_queries = 8; info->num_queries = nvc0_hw_sm_get_num_queries(screen); return 1; } @@ -233,7 +231,7 @@ nvc0_screen_get_driver_query_group_info(struct pipe_screen *pscreen, if (screen->compute) { if (screen->base.class_3d <= NVF0_3D_CLASS) { info->name = "Performance metrics"; - info->max_active_queries = 1; + info->max_active_queries = 4; /* A metric uses at least 2 queries */ info->num_queries = nvc0_hw_metric_get_num_queries(screen); return 1; } |