diff options
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_compiler.h | 1 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_shader.cpp | 7 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_shader.h | 2 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_wm.c | 13 |
4 files changed, 16 insertions, 7 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_compiler.h b/src/mesa/drivers/dri/i965/brw_compiler.h index 0c300e7cff0..933ab118e6e 100644 --- a/src/mesa/drivers/dri/i965/brw_compiler.h +++ b/src/mesa/drivers/dri/i965/brw_compiler.h @@ -389,6 +389,7 @@ struct brw_wm_prog_data { * surface indices the WM-specific surfaces */ uint32_t render_target_start; + uint32_t render_target_read_start; /** @} */ } binding_table; diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp b/src/mesa/drivers/dri/i965/brw_shader.cpp index 62bad9bbd9f..aa2c9d432fe 100644 --- a/src/mesa/drivers/dri/i965/brw_shader.cpp +++ b/src/mesa/drivers/dri/i965/brw_shader.cpp @@ -1148,7 +1148,7 @@ backend_shader::calculate_cfg() * unused but also make sure that addition of small offsets to them will * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES. */ -void +uint32_t brw_assign_common_binding_table_offsets(gl_shader_stage stage, const struct brw_device_info *devinfo, const struct gl_shader_program *shader_prog, @@ -1224,9 +1224,10 @@ brw_assign_common_binding_table_offsets(gl_shader_stage stage, stage_prog_data->binding_table.plane_start[2] = next_binding_table_offset; next_binding_table_offset += num_textures; - assert(next_binding_table_offset <= BRW_MAX_SURFACES); - /* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */ + + assert(next_binding_table_offset <= BRW_MAX_SURFACES); + return next_binding_table_offset; } static void diff --git a/src/mesa/drivers/dri/i965/brw_shader.h b/src/mesa/drivers/dri/i965/brw_shader.h index e61c080311e..3b3be07b5ec 100644 --- a/src/mesa/drivers/dri/i965/brw_shader.h +++ b/src/mesa/drivers/dri/i965/brw_shader.h @@ -261,7 +261,7 @@ struct brw_gs_compile unsigned control_data_header_size_bits; }; -void +uint32_t brw_assign_common_binding_table_offsets(gl_shader_stage stage, const struct brw_device_info *devinfo, const struct gl_shader_program *shader_prog, diff --git a/src/mesa/drivers/dri/i965/brw_wm.c b/src/mesa/drivers/dri/i965/brw_wm.c index c513dbcc367..3f929c46cf5 100644 --- a/src/mesa/drivers/dri/i965/brw_wm.c +++ b/src/mesa/drivers/dri/i965/brw_wm.c @@ -56,9 +56,16 @@ assign_fs_binding_table_offsets(const struct brw_device_info *devinfo, prog_data->binding_table.render_target_start = next_binding_table_offset; next_binding_table_offset += MAX2(key->nr_color_regions, 1); - brw_assign_common_binding_table_offsets(MESA_SHADER_FRAGMENT, devinfo, - shader_prog, prog, &prog_data->base, - next_binding_table_offset); + next_binding_table_offset = + brw_assign_common_binding_table_offsets(MESA_SHADER_FRAGMENT, devinfo, + shader_prog, prog, &prog_data->base, + next_binding_table_offset); + + if (prog->nir->info.outputs_read && !key->coherent_fb_fetch) { + prog_data->binding_table.render_target_read_start = + next_binding_table_offset; + next_binding_table_offset += key->nr_color_regions; + } } /** |