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-rw-r--r--src/mesa/drivers/dri/i965/brw_defines.h1
-rw-r--r--src/mesa/drivers/dri/i965/gen8_blorp.c2
-rw-r--r--src/mesa/drivers/dri/i965/gen8_surface_state.c3
3 files changed, 5 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index 4696faf082e..fce510c8fe0 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -656,6 +656,7 @@
#define GEN8_SURFACE_AUX_MODE_MCS 1
#define GEN8_SURFACE_AUX_MODE_APPEND 2
#define GEN8_SURFACE_AUX_MODE_HIZ 3
+#define GEN9_SURFACE_AUX_MODE_CCS_E 5
/* Surface state DW7 */
#define GEN9_SURFACE_RT_COMPRESSION_SHIFT 30
diff --git a/src/mesa/drivers/dri/i965/gen8_blorp.c b/src/mesa/drivers/dri/i965/gen8_blorp.c
index 5cd070fa473..05ef54c4d0a 100644
--- a/src/mesa/drivers/dri/i965/gen8_blorp.c
+++ b/src/mesa/drivers/dri/i965/gen8_blorp.c
@@ -77,7 +77,7 @@ gen8_blorp_emit_surface_state(struct brw_context *brw,
surf[6] = SET_FIELD(surface->mt->qpitch / 4, GEN8_SURFACE_AUX_QPITCH) |
SET_FIELD((surface->mt->mcs_mt->pitch / 128) - 1,
GEN8_SURFACE_AUX_PITCH) |
- GEN8_SURFACE_AUX_MODE_MCS;
+ gen8_get_aux_mode(brw, mt);
} else {
surf[6] = 0;
}
diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c b/src/mesa/drivers/dri/i965/gen8_surface_state.c
index 4f9a6e96fe9..4b9896fe7d6 100644
--- a/src/mesa/drivers/dri/i965/gen8_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_surface_state.c
@@ -216,6 +216,9 @@ gen8_get_aux_mode(const struct brw_context *brw,
if (brw->gen >= 9 || mt->num_samples == 1)
assert(mt->halign == 16);
+ if (intel_miptree_is_lossless_compressed(brw, mt))
+ return GEN9_SURFACE_AUX_MODE_CCS_E;
+
return GEN8_SURFACE_AUX_MODE_MCS;
}