diff options
| -rw-r--r-- | src/compiler/nir/nir_intrinsics.h | 2 | ||||
| -rw-r--r-- | src/compiler/nir/nir_print.c | 2 | ||||
| -rw-r--r-- | src/gallium/drivers/radeon/radeon_uvd.c | 12 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/common/dri_util.c | 25 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_surface_formats.c | 1 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_surface_formats.h | 2 |
6 files changed, 36 insertions, 8 deletions
diff --git a/src/compiler/nir/nir_intrinsics.h b/src/compiler/nir/nir_intrinsics.h index 3cb4f95394c..bd00fbbe6cc 100644 --- a/src/compiler/nir/nir_intrinsics.h +++ b/src/compiler/nir/nir_intrinsics.h @@ -179,7 +179,7 @@ INTRINSIC(image_samples, 0, ARR(0), true, 1, 1, 0, xx, xx, xx, * Vulkan descriptor set intrinsic * * The Vulkan API uses a different binding model from GL. In the Vulkan - * API, all external resources are represented by a tripple: + * API, all external resources are represented by a tuple: * * (descriptor set, binding, array index) * diff --git a/src/compiler/nir/nir_print.c b/src/compiler/nir/nir_print.c index bbb4edf3260..84e926905b4 100644 --- a/src/compiler/nir/nir_print.c +++ b/src/compiler/nir/nir_print.c @@ -518,6 +518,8 @@ print_intrinsic_instr(nir_intrinsic_instr *instr, print_state *state) [NIR_INTRINSIC_STREAM_ID] = "stream-id", [NIR_INTRINSIC_UCP_ID] = "ucp-id", [NIR_INTRINSIC_RANGE] = "range", + [NIR_INTRINSIC_DESC_SET] = "desc-set", + [NIR_INTRINSIC_BINDING] = "binding", }; for (unsigned idx = 1; idx < NIR_INTRINSIC_NUM_INDEX_FLAGS; idx++) { if (!info->index_map[idx]) diff --git a/src/gallium/drivers/radeon/radeon_uvd.c b/src/gallium/drivers/radeon/radeon_uvd.c index 098baf20797..b775cd34083 100644 --- a/src/gallium/drivers/radeon/radeon_uvd.c +++ b/src/gallium/drivers/radeon/radeon_uvd.c @@ -57,6 +57,7 @@ #define FB_BUFFER_OFFSET 0x1000 #define FB_BUFFER_SIZE 2048 +#define FB_BUFFER_SIZE_TONGA (2048 * 64) #define IT_SCALING_TABLE_SIZE 992 /* UVD decoder representation */ @@ -78,6 +79,7 @@ struct ruvd_decoder { struct rvid_buffer msg_fb_it_buffers[NUM_BUFFERS]; struct ruvd_msg *msg; uint32_t *fb; + unsigned fb_size; uint8_t *it; struct rvid_buffer bs_buffers[NUM_BUFFERS]; @@ -148,7 +150,7 @@ static void map_msg_fb_it_buf(struct ruvd_decoder *dec) dec->msg = (struct ruvd_msg *)ptr; dec->fb = (uint32_t *)(ptr + FB_BUFFER_OFFSET); if (have_it(dec)) - dec->it = (uint8_t *)(ptr + FB_BUFFER_OFFSET + FB_BUFFER_SIZE); + dec->it = (uint8_t *)(ptr + FB_BUFFER_OFFSET + dec->fb_size); } /* unmap and send a message command to the VCPU */ @@ -1050,7 +1052,7 @@ static void ruvd_end_frame(struct pipe_video_codec *decoder, dec->msg->body.decode.extension_support = 0x1; /* set at least the feedback buffer size */ - dec->fb[0] = FB_BUFFER_SIZE; + dec->fb[0] = dec->fb_size; send_msg_buf(dec); @@ -1068,7 +1070,7 @@ static void ruvd_end_frame(struct pipe_video_codec *decoder, FB_BUFFER_OFFSET, RADEON_USAGE_WRITE, RADEON_DOMAIN_GTT); if (have_it(dec)) send_cmd(dec, RUVD_CMD_ITSCALING_TABLE_BUFFER, msg_fb_it_buf->res->buf, - FB_BUFFER_OFFSET + FB_BUFFER_SIZE, RADEON_USAGE_READ, RADEON_DOMAIN_GTT); + FB_BUFFER_OFFSET + dec->fb_size, RADEON_USAGE_READ, RADEON_DOMAIN_GTT); set_reg(dec, RUVD_ENGINE_CNTL, 1); flush(dec); @@ -1148,9 +1150,11 @@ struct pipe_video_codec *ruvd_create_decoder(struct pipe_context *context, goto error; } + dec->fb_size = (info.family == CHIP_TONGA) ? FB_BUFFER_SIZE_TONGA : + FB_BUFFER_SIZE; bs_buf_size = width * height * 512 / (16 * 16); for (i = 0; i < NUM_BUFFERS; ++i) { - unsigned msg_fb_it_size = FB_BUFFER_OFFSET + FB_BUFFER_SIZE; + unsigned msg_fb_it_size = FB_BUFFER_OFFSET + dec->fb_size; STATIC_ASSERT(sizeof(struct ruvd_msg) <= FB_BUFFER_OFFSET); if (have_it(dec)) msg_fb_it_size += IT_SCALING_TABLE_SIZE; diff --git a/src/mesa/drivers/dri/common/dri_util.c b/src/mesa/drivers/dri/common/dri_util.c index a6545084e31..79cb0506dd8 100644 --- a/src/mesa/drivers/dri/common/dri_util.c +++ b/src/mesa/drivers/dri/common/dri_util.c @@ -376,11 +376,32 @@ driCreateContextAttribs(__DRIscreen *screen, int api, * EGL_CONTEXT_FLAGS_KHR, then a <debug context> will be created. * [...] This bit is supported for OpenGL and OpenGL ES contexts. * - * None of the other flags have any meaning in an ES context, so this seems safe. + * No other EGL_CONTEXT_OPENGL_*_BIT is legal for an ES context. + * + * However, Mesa's EGL layer translates the context attribute + * EGL_CONTEXT_OPENGL_ROBUST_ACCESS into the context flag + * __DRI_CTX_FLAG_ROBUST_BUFFER_ACCESS. That attribute is legal for ES + * (with EGL 1.5 or EGL_EXT_create_context_robustness) and GL (only with + * EGL 1.5). + * + * From the EGL_EXT_create_context_robustness spec: + * + * This extension is written against the OpenGL ES 2.0 Specification + * but can apply to OpenGL ES 1.1 and up. + * + * From the EGL 1.5 (2014.08.27) spec, p55: + * + * If the EGL_CONTEXT_OPENGL_ROBUST_ACCESS attribute is set to + * EGL_TRUE, a context supporting robust buffer access will be created. + * OpenGL contexts must support the GL_ARB_robustness extension, or + * equivalent core API functional- ity. OpenGL ES contexts must support + * the GL_EXT_robustness extension, or equivalent core API + * functionality. */ if (mesa_api != API_OPENGL_COMPAT && mesa_api != API_OPENGL_CORE - && (flags & ~__DRI_CTX_FLAG_DEBUG)) { + && (flags & ~(__DRI_CTX_FLAG_DEBUG | + __DRI_CTX_FLAG_ROBUST_BUFFER_ACCESS))) { *error = __DRI_CTX_ERROR_BAD_FLAG; return NULL; } diff --git a/src/mesa/drivers/dri/i965/brw_surface_formats.c b/src/mesa/drivers/dri/i965/brw_surface_formats.c index fa7878dec82..61e14080264 100644 --- a/src/mesa/drivers/dri/i965/brw_surface_formats.c +++ b/src/mesa/drivers/dri/i965/brw_surface_formats.c @@ -25,7 +25,6 @@ #include "brw_context.h" #include "brw_state.h" #include "brw_defines.h" -#include "brw_wm.h" #include "brw_surface_formats.h" /* This macro allows us to write the table almost as it appears in the PRM, diff --git a/src/mesa/drivers/dri/i965/brw_surface_formats.h b/src/mesa/drivers/dri/i965/brw_surface_formats.h index a5cd49f5260..8e4d35e5512 100644 --- a/src/mesa/drivers/dri/i965/brw_surface_formats.h +++ b/src/mesa/drivers/dri/i965/brw_surface_formats.h @@ -23,6 +23,8 @@ #pragma once +#include <stdbool.h> + struct brw_surface_format_info { bool exists; int sampling; |