diff options
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_defines.h | 8 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_structs.h | 9 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 21 |
3 files changed, 37 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index 2d47ef85520..01bad5c1892 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -464,6 +464,14 @@ #define BRW_SURFACE_Y_OFFSET_SHIFT 20 #define BRW_SURFACE_Y_OFFSET_MASK INTEL_MASK(23, 20) +/* Surface state DW7 */ +#define HSW_SCS_ZERO 0 +#define HSW_SCS_ONE 1 +#define HSW_SCS_RED 4 +#define HSW_SCS_GREEN 5 +#define HSW_SCS_BLUE 6 +#define HSW_SCS_ALPHA 7 + #define BRW_TEXCOORDMODE_WRAP 0 #define BRW_TEXCOORDMODE_MIRROR 1 #define BRW_TEXCOORDMODE_CLAMP 2 diff --git a/src/mesa/drivers/dri/i965/brw_structs.h b/src/mesa/drivers/dri/i965/brw_structs.h index 8283abfd375..41c88d010f5 100644 --- a/src/mesa/drivers/dri/i965/brw_structs.h +++ b/src/mesa/drivers/dri/i965/brw_structs.h @@ -860,7 +860,14 @@ struct gen7_surface_state struct { GLuint resource_min_lod:12; - GLuint pad0:16; + + /* Only on Haswell */ + GLuint pad0:4; + GLuint shader_chanel_select_a:3; + GLuint shader_chanel_select_b:3; + GLuint shader_chanel_select_g:3; + GLuint shader_chanel_select_r:3; + GLuint alpha_clear_color:1; GLuint blue_clear_color:1; GLuint green_clear_color:1; diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c index c52f6aacef7..cd044dffd67 100644 --- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c @@ -121,6 +121,13 @@ gen7_update_texture_surface(struct gl_context *ctx, GLuint unit) * - cache_control */ + if (brw->intel.is_haswell) { + surf->ss7.shader_chanel_select_r = HSW_SCS_RED; + surf->ss7.shader_chanel_select_g = HSW_SCS_GREEN; + surf->ss7.shader_chanel_select_b = HSW_SCS_BLUE; + surf->ss7.shader_chanel_select_a = HSW_SCS_ALPHA; + } + /* Emit relocation to surface contents */ drm_intel_bo_emit_reloc(brw->intel.batch.bo, brw->wm.surf_offset[surf_index] + @@ -160,6 +167,13 @@ gen7_create_constant_surface(struct brw_context *brw, surf->ss3.pitch = (16 - 1); /* ignored */ gen7_set_surface_tiling(surf, I915_TILING_NONE); /* tiling now allowed */ + if (brw->intel.is_haswell) { + surf->ss7.shader_chanel_select_r = HSW_SCS_RED; + surf->ss7.shader_chanel_select_g = HSW_SCS_GREEN; + surf->ss7.shader_chanel_select_b = HSW_SCS_BLUE; + surf->ss7.shader_chanel_select_a = HSW_SCS_ALPHA; + } + /* Emit relocation to surface contents. Section 5.1.1 of the gen4 * bspec ("Data Cache") says that the data cache does not exist as * a separate cache and is just the sampler cache. @@ -249,6 +263,13 @@ gen7_update_renderbuffer_surface(struct brw_context *brw, gen7_set_surface_tiling(surf, region->tiling); surf->ss3.pitch = (region->pitch * region->cpp) - 1; + if (intel->is_haswell) { + surf->ss7.shader_chanel_select_r = HSW_SCS_RED; + surf->ss7.shader_chanel_select_g = HSW_SCS_GREEN; + surf->ss7.shader_chanel_select_b = HSW_SCS_BLUE; + surf->ss7.shader_chanel_select_a = HSW_SCS_ALPHA; + } + drm_intel_bo_emit_reloc(brw->intel.batch.bo, brw->wm.surf_offset[unit] + offsetof(struct gen7_surface_state, ss1), |