5 files changed, 43 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index 3605c188d37..6dc470768a2 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -1037,6 +1037,9 @@ enum brw_message_target {
 # define GEN6_URB_GS_ENTRIES_SHIFT			8
 # define GEN6_URB_GS_SIZE_SHIFT				0
 
+#define _3DSTATE_VF                             0x780c /* GEN7.5+ */
+#define HSW_CUT_INDEX_ENABLE                            (1 << 8)
+
 #define _3DSTATE_URB_VS                         0x7830 /* GEN7+ */
 #define _3DSTATE_URB_HS                         0x7831 /* GEN7+ */
 #define _3DSTATE_URB_DS                         0x7832 /* GEN7+ */
diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c
index e40c7d555de..33cce8fdf3a 100644
--- a/src/mesa/drivers/dri/i965/brw_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c
@@ -930,7 +930,7 @@ static void brw_emit_index_buffer(struct brw_context *brw)
    if (index_buffer == NULL)
       return;
 
-   if (brw->prim_restart.enable_cut_index) {
+   if (brw->prim_restart.enable_cut_index && !intel->is_haswell) {
       cut_index_setting = BRW_CUT_INDEX_ENABLE;
    } else {
       cut_index_setting = 0;
diff --git a/src/mesa/drivers/dri/i965/brw_primitive_restart.c b/src/mesa/drivers/dri/i965/brw_primitive_restart.c
index 02deba4fbb6..38b52438c09 100644
--- a/src/mesa/drivers/dri/i965/brw_primitive_restart.c
+++ b/src/mesa/drivers/dri/i965/brw_primitive_restart.c
@@ -29,8 +29,11 @@
 #include "main/bufferobj.h"
 
 #include "brw_context.h"
+#include "brw_defines.h"
 #include "brw_draw.h"
 
+#include "intel_batchbuffer.h"
+
 /**
  * Check if the hardware's cut index support can handle the primitive
  * restart index value.
@@ -39,6 +42,12 @@ static bool
 can_cut_index_handle_restart_index(struct gl_context *ctx,
                                    const struct _mesa_index_buffer *ib)
 {
+   struct intel_context *intel = intel_context(ctx);
+
+   /* Haswell supports an arbitrary cut index. */
+   if (intel->is_haswell)
+      return true;
+
    bool cut_index_will_work;
 
    switch (ib->type) {
@@ -176,3 +185,30 @@ brw_handle_primitive_restart(struct gl_context *ctx,
    return GL_TRUE;
 }
 
+static void
+haswell_upload_cut_index(struct brw_context *brw)
+{
+   struct intel_context *intel = &brw->intel;
+   struct gl_context *ctx = &intel->ctx;
+
+   /* Don't trigger on Ivybridge */
+   if (!intel->is_haswell)
+      return;
+
+   const unsigned cut_index_setting =
+      ctx->Array.PrimitiveRestart ? HSW_CUT_INDEX_ENABLE : 0;
+
+   BEGIN_BATCH(2);
+   OUT_BATCH(_3DSTATE_VF << 16 | cut_index_setting | (2 - 2));
+   OUT_BATCH(ctx->Array.RestartIndex);
+   ADVANCE_BATCH();
+}
+
+const struct brw_tracked_state haswell_cut_index = {
+   .dirty = {
+      .mesa  = _NEW_TRANSFORM,
+      .brw   = 0,
+      .cache = 0,
+   },
+   .emit = haswell_upload_cut_index,
+};
diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h
index a80ee865a9e..99fa088a90f 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -133,6 +133,7 @@ extern const struct brw_tracked_state gen7_wm_constants;
 extern const struct brw_tracked_state gen7_wm_constant_surface;
 extern const struct brw_tracked_state gen7_wm_state;
 extern const struct brw_tracked_state gen7_wm_surfaces;
+extern const struct brw_tracked_state haswell_cut_index;
 
 /* brw_misc_state.c */
 uint32_t
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c
index 7291988c8a4..ec0f765635b 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -246,6 +246,8 @@ const struct brw_tracked_state *gen7_atoms[] =
    &brw_indices,
    &brw_index_buffer,
    &brw_vertices,
+
+   &haswell_cut_index,
 };