diff options
| -rw-r--r-- | src/amd/vulkan/radv_image.c | 12 | ||||
| -rw-r--r-- | src/amd/vulkan/radv_radeon_winsys.h | 5 | ||||
| -rw-r--r-- | src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c | 8 |
3 files changed, 13 insertions, 12 deletions
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c index 8b3eb49f5f4..e49a05383f7 100644 --- a/src/amd/vulkan/radv_image.c +++ b/src/amd/vulkan/radv_image.c @@ -463,8 +463,8 @@ radv_image_get_fmask_info(struct radv_device *device, struct radeon_surf_info info = image->info; memset(out, 0, sizeof(*out)); - fmask.bo_alignment = 0; - fmask.bo_size = 0; + fmask.surf_alignment = 0; + fmask.surf_size = 0; fmask.flags |= RADEON_SURF_FMASK; info.samples = 1; /* Force 2D tiling if it wasn't set. This may occur when creating @@ -497,8 +497,8 @@ radv_image_get_fmask_info(struct radv_device *device, out->tile_mode_index = fmask.tiling_index[0]; out->pitch_in_pixels = fmask.level[0].nblk_x; out->bank_height = fmask.bankh; - out->alignment = MAX2(256, fmask.bo_alignment); - out->size = fmask.bo_size; + out->alignment = MAX2(256, fmask.surf_alignment); + out->size = fmask.surf_size; } static void @@ -653,8 +653,8 @@ radv_image_create(VkDevice _device, device->ws->surface_init(device->ws, &image->info, &image->surface); - image->size = image->surface.bo_size; - image->alignment = image->surface.bo_alignment; + image->size = image->surface.surf_size; + image->alignment = image->surface.surf_alignment; if (image->exclusive || image->queue_family_mask == 1) can_cmask_dcc = true; diff --git a/src/amd/vulkan/radv_radeon_winsys.h b/src/amd/vulkan/radv_radeon_winsys.h index 660bea58255..1d68629a247 100644 --- a/src/amd/vulkan/radv_radeon_winsys.h +++ b/src/amd/vulkan/radv_radeon_winsys.h @@ -188,8 +188,6 @@ struct radeon_surf { * they will be treated as hints (e.g. bankw, bankh) and might be * changed by the calculator. */ - uint64_t bo_size; - uint64_t bo_alignment; /* This applies to EG and later. */ uint32_t bankw; uint32_t bankh; @@ -214,6 +212,9 @@ struct radeon_surf { bool depth_adjusted; bool stencil_adjusted; + uint64_t surf_size; + uint64_t surf_alignment; + uint64_t dcc_size; uint64_t dcc_alignment; diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c index 44b1c8f6190..eb9c11c44ae 100644 --- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c +++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c @@ -201,7 +201,7 @@ static int radv_compute_level(ADDR_HANDLE addrlib, return ret; surf_level = is_stencil ? &surf->stencil_level[level] : &surf->level[level]; - surf_level->offset = align64(surf->bo_size, AddrSurfInfoOut->baseAlign); + surf_level->offset = align64(surf->surf_size, AddrSurfInfoOut->baseAlign); surf_level->slice_size = AddrSurfInfoOut->sliceSize; surf_level->nblk_x = AddrSurfInfoOut->pitch; surf_level->nblk_y = AddrSurfInfoOut->height; @@ -225,7 +225,7 @@ static int radv_compute_level(ADDR_HANDLE addrlib, else surf->tiling_index[level] = AddrSurfInfoOut->tileIndex; - surf->bo_size = surf_level->offset + AddrSurfInfoOut->surfSize; + surf->surf_size = surf_level->offset + AddrSurfInfoOut->surfSize; /* Clear DCC fields at the beginning. */ surf_level->dcc_offset = 0; @@ -470,7 +470,7 @@ static int radv_amdgpu_winsys_surface_init(struct radeon_winsys *_ws, } } - surf->bo_size = 0; + surf->surf_size = 0; surf->num_dcc_levels = 0; surf->dcc_size = 0; surf->dcc_alignment = 1; @@ -485,7 +485,7 @@ static int radv_amdgpu_winsys_surface_init(struct radeon_winsys *_ws, break; if (level == 0) { - surf->bo_alignment = AddrSurfInfoOut.baseAlign; + surf->surf_alignment = AddrSurfInfoOut.baseAlign; surf->pipe_config = AddrSurfInfoOut.pTileInfo->pipeConfig - 1; radv_set_micro_tile_mode(surf, &ws->info); |