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-rw-r--r--src/gallium/drivers/radeon/radeon_winsys.h2
-rw-r--r--src/gallium/drivers/radeonsi/si_debug.c4
-rw-r--r--src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c6
-rw-r--r--src/gallium/winsys/radeon/drm/radeon_drm_winsys.c6
4 files changed, 10 insertions, 8 deletions
diff --git a/src/gallium/drivers/radeon/radeon_winsys.h b/src/gallium/drivers/radeon/radeon_winsys.h
index 7ab6e56e099..a4a2ae15acd 100644
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -680,7 +680,7 @@ struct radeon_winsys {
uint64_t (*query_value)(struct radeon_winsys *ws,
enum radeon_value_id value);
- void (*read_registers)(struct radeon_winsys *ws, unsigned reg_offset,
+ bool (*read_registers)(struct radeon_winsys *ws, unsigned reg_offset,
unsigned num_registers, uint32_t *out);
};
diff --git a/src/gallium/drivers/radeonsi/si_debug.c b/src/gallium/drivers/radeonsi/si_debug.c
index 22d6f250b03..d3fd201ae26 100644
--- a/src/gallium/drivers/radeonsi/si_debug.c
+++ b/src/gallium/drivers/radeonsi/si_debug.c
@@ -349,8 +349,8 @@ static void si_dump_mmapped_reg(struct si_context *sctx, FILE *f,
struct radeon_winsys *ws = sctx->b.ws;
uint32_t value;
- ws->read_registers(ws, offset, 1, &value);
- si_dump_reg(f, offset, value, ~0);
+ if (ws->read_registers(ws, offset, 1, &value))
+ si_dump_reg(f, offset, value, ~0);
}
static void si_dump_debug_registers(struct si_context *sctx, FILE *f)
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
index 012c9003b69..875dcd09c6b 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
@@ -350,14 +350,14 @@ static uint64_t amdgpu_query_value(struct radeon_winsys *rws,
return 0;
}
-static void amdgpu_read_registers(struct radeon_winsys *rws,
+static bool amdgpu_read_registers(struct radeon_winsys *rws,
unsigned reg_offset,
unsigned num_registers, uint32_t *out)
{
struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
- amdgpu_read_mm_registers(ws->dev, reg_offset / 4, num_registers,
- 0xffffffff, 0, out);
+ return amdgpu_read_mm_registers(ws->dev, reg_offset / 4, num_registers,
+ 0xffffffff, 0, out) == 0;
}
static unsigned hash_dev(void *key)
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
index f7784fb795e..384d7280380 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
@@ -583,7 +583,7 @@ static uint64_t radeon_query_value(struct radeon_winsys *rws,
return 0;
}
-static void radeon_read_registers(struct radeon_winsys *rws,
+static bool radeon_read_registers(struct radeon_winsys *rws,
unsigned reg_offset,
unsigned num_registers, uint32_t *out)
{
@@ -593,9 +593,11 @@ static void radeon_read_registers(struct radeon_winsys *rws,
for (i = 0; i < num_registers; i++) {
uint32_t reg = reg_offset + i*4;
- radeon_get_drm_value(ws->fd, RADEON_INFO_READ_REG, "read-reg", &reg);
+ if (!radeon_get_drm_value(ws->fd, RADEON_INFO_READ_REG, NULL, &reg))
+ return false;
out[i] = reg;
}
+ return true;
}
static unsigned hash_fd(void *key)